CN115223494A

CN115223494A - Drive circuit and display panel

Info

Publication number: CN115223494A
Application number: CN202210838775.0A
Authority: CN
Inventors: 张蒙蒙
Original assignee: Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
Current assignee: Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
Priority date: 2022-07-18
Filing date: 2022-07-18
Publication date: 2022-10-21
Anticipated expiration: 2042-07-18
Also published as: CN115223494B

Abstract

The application discloses a driving circuit and a display panel, wherein the driving circuit comprises a first transistor, a first capacitor, a light-emitting device, a pulse width modulation module and a first external detection module; the pulse width modulation module comprises a second transistor; a gate of the first transistor is electrically connected to a first node, one of a source and a drain of the first transistor is electrically connected to a first power source terminal, and the other of the source and the drain of the first transistor is electrically connected to a second node; one end of the light-emitting device is electrically connected with the second node, and the other end of the light-emitting device is electrically connected with a second power supply end; the first external detection module is connected with the pulse width modulation signal and is electrically connected with the first node. The threshold voltage of the second transistor in the pulse width modulation module is detected and compensated through the first external detection module, so that the uniformity of picture display is ensured, and the display effect of the display panel is improved.

Description

Drive circuit and display panel

Technical Field

The application relates to the technical field of display, in particular to a driving circuit and a display panel.

Background

At present, there are two common pixel driving methods for a display panel, namely Pulse Amplitude Modulation (PAM) driving and Pulse Width Modulation (PWM) driving. The PAM driving realizes different brightness display by controlling the magnitude of the driving current of the light-emitting device in each pixel unit, but the PAM driving mode has the problem of color point drift under low gray scale, thereby influencing the display effect; the PWM driving is to realize different luminance display by controlling the light emitting time of the light emitting device in each pixel unit, but the PWM driving method has a high demand for a Gate driving chip (Gate IC).

Therefore, by combining the advantages of the PWM driving method and the PAM driving method, those skilled in the art have developed a PHM hybrid circuit, which uses PWM driving at low gray scale and PAM driving at high gray scale. The PWM module of the PHM hybrid circuit comprises a PWM driving transistor, the threshold voltage (Vth) value of the PWM driving transistor determines the turn-on time of the PWM driving transistor, so that the light emitting time of the light emitting device is determined, and when the Vth values of a plurality of PWM driving transistors are different, the light emitting time of the light emitting device is greatly influenced, so that the uniformity of a display picture is influenced.

Disclosure of Invention

The application provides a drive circuit and a display panel, which detect the threshold voltage of a PWM drive transistor of the drive circuit to carry out external compensation on the PWM drive transistor and achieve the uniformity of picture display.

In a first aspect, the present application provides a driving circuit comprising:

a first transistor having a gate electrically connected to a first node, one of a source and a drain of the first transistor electrically connected to a first power source terminal, and the other of the source and the drain of the first transistor electrically connected to a second node;

a light emitting device, one end of which is electrically connected to the second node and the other end of which is electrically connected to a second power supply terminal;

a first capacitor, a first end of the first capacitor being electrically connected to the first node, a second end of the first capacitor being electrically connected to the second node;

a pulse width modulation module, connected to a pulse width modulation signal and a data signal, and electrically connected to the second power source terminal and the first node, the pulse width modulation module including a second transistor, the pulse width modulation module being configured to adjust a pulse width of a driving current flowing through the light emitting device under control of the pulse width modulation signal; and

the first external detection module is connected to the pulse width modulation signal and electrically connected to the first node, and is used for detecting and compensating the threshold voltage of the second transistor.

In the driving circuit provided by the present application, the signals connected to the second power supply terminal include a constant voltage high level signal and a constant voltage low level signal.

In the driving circuit provided by the present application, when the first external detection module detects the threshold voltage of the second transistor, the second power terminal is connected to the constant-voltage high-level signal; when the first external detection module does not detect the threshold voltage of the second transistor, the second power supply end is connected to the constant-voltage low-level signal.

In the driving circuit provided by the present application, the first external detection module includes a third transistor;

the grid electrode of the third transistor is connected with the pulse width modulation signal, one of the source electrode and the drain electrode of the third transistor is electrically connected with the first node, and the other of the source electrode and the drain electrode of the third transistor is electrically connected with the first detecting end.

In the driving circuit provided by the application, the pulse width modulation module further comprises a fourth transistor;

the grid electrode of the fourth transistor is connected with the pulse width modulation signal, one of the source electrode and the drain electrode of the fourth transistor is connected with the data signal, and the other of the source electrode and the drain electrode of the fourth transistor is electrically connected with a third node;

a gate of the second transistor is electrically connected to the third node, one of a source and a drain of the second transistor is electrically connected to the second power supply terminal, and the other of the source and the drain of the second transistor is electrically connected to the first node.

In the driving circuit provided by the present application, the pulse width modulation module further includes a second capacitor;

the first end of the second capacitor is connected with a frequency sweeping signal, and the second end of the second capacitor is electrically connected with the third node, so that the frequency sweeping signal adjusts the potential of the third node through the second capacitor.

In the driving circuit provided by the application, the driving circuit further comprises a pulse amplitude modulation module;

the pulse amplitude modulation module is connected with a pulse amplitude modulation signal and the data signal and is electrically connected with the first node, and the pulse amplitude modulation module is used for adjusting the pulse amplitude of the driving current under the control of the pulse amplitude modulation signal.

In the driving circuit provided by the application, the pulse amplitude modulation module comprises a fifth transistor;

the gate of the fifth transistor is connected to the pulse amplitude modulation signal, one of the source and the drain of the fifth transistor is connected to the data signal, and the other of the source and the drain of the fifth transistor is electrically connected to the first node.

In the driving circuit provided by the present application, the driving circuit further includes a second external detection module;

the second external detection module is connected to the pulse amplitude modulation signal and electrically connected to the second node, and the second external detection module is used for detecting and compensating the threshold voltage of the first transistor.

In the driving circuit provided by the present application, the second external detection module includes a sixth transistor;

the grid electrode of the sixth transistor is connected with the pulse amplitude modulation signal, one of the source electrode and the drain electrode of the sixth transistor is electrically connected with the second detection end, and the other of the source electrode and the drain electrode of the sixth transistor is electrically connected with the second node.

In a second aspect, the present application also provides a display panel including the driving circuit as described above.

The application provides a drive circuit and display panel, through setting up first outside detection module electricity and connect in first node, realize listening the threshold voltage of the second transistor in the pulse width modulation module, listen the threshold voltage of PWM driving transistor promptly to carry out external compensation to the threshold voltage of PWM driving transistor, guarantee the homogeneity of picture display, improve display panel's display effect.

Drawings

Fig. 1 is a schematic diagram of a first structure of a driving circuit according to an embodiment of the present disclosure;

FIG. 2 is a timing diagram illustrating threshold voltage detection of a second transistor of the driving circuit shown in FIG. 1;

FIG. 3 is a schematic path diagram of the driving circuit provided in FIG. 1 during a first initialization phase according to the timing sequence shown in FIG. 2;

fig. 4 is a schematic diagram of a second structure of a driving circuit according to an embodiment of the present application;

FIG. 5 is a timing diagram illustrating the threshold voltage detection of the first transistor of the driving circuit shown in FIG. 4;

FIG. 6 is a schematic diagram illustrating a second initialization phase of the driving circuit provided in FIG. 4 according to the timing sequence shown in FIG. 5;

FIG. 7 is a schematic diagram illustrating a second detection phase of the driving circuit shown in FIG. 4 according to the driving timing shown in FIG. 5;

fig. 8 is a schematic diagram of a third structure of a driving circuit according to an embodiment of the present application;

fig. 9 is a timing chart of light emission of the driving circuit shown in fig. 8;

FIG. 10 is a schematic diagram illustrating a third initialization phase of the driving circuit provided in FIG. 8 according to the driving sequence shown in FIG. 9;

FIG. 11 is a schematic diagram of a data write phase of the driving circuit provided in FIG. 8 at the driving timing shown in FIG. 9;

fig. 12 is a schematic diagram of a path of the driving circuit provided in fig. 8 at a light emitting stage under the driving timing shown in fig. 9.

Detailed Description

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. It is to be understood that the described embodiments are merely a few embodiments of the present application and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

Furthermore, the terms "first," "second," and the like in the description and in the claims of the present application are used for distinguishing between different objects and not for describing a particular order. The terms "comprising" and "having," as well as any variations thereof, are intended to cover non-exclusive inclusions. Since the source and the drain of the transistor adopted by the application are symmetrical, the source and the drain can be interchanged. The form of the figure provides that the middle end of the transistor is a grid, the signal input end is a source, and the output end is a drain.

The following disclosure provides many different embodiments or examples for implementing different features of the application. In order to simplify the disclosure of the present application, specific example components and arrangements are described below. Of course, they are merely examples and are not intended to limit the present application. Moreover, the present application may repeat reference numerals and/or letters in the various examples, such repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Referring to fig. 1, fig. 1 is a schematic diagram of a first structure of a driving circuit according to an embodiment of the present disclosure. As shown in fig. 1, a driving circuit 100 provided in the embodiment of the present application includes: the circuit comprises a first transistor T1, a light emitting device D, a first capacitor C1, a pulse width modulation module 10 and a first external detection module 20. It should be noted that the light emitting device D may be a mini light emitting diode, a micro light emitting diode or an organic light emitting diode.

Wherein the gate electrode of the first transistor T1 is electrically connected to the first node Q, one of the source electrode and the drain electrode of the first transistor T1 is electrically connected to the first power terminal V1, and the other of the source electrode and the drain electrode of the first transistor T1 is electrically connected to the second node S.

Wherein one end of the light emitting device D is electrically connected to the second node Q, and the other end of the light emitting device D is electrically connected to the second power terminal V2.

A first end of the first capacitor C1 is electrically connected to the first node Q, and a second end of the first capacitor C1 is electrically connected to the second node S.

The pulse width modulation module 10 is connected to the pulse width modulation signal SPWM and the Data signal Data, and the pulse width modulation module 10 is electrically connected to the second power supply terminal V2 and the first node Q; the pulse width modulation module 10 includes a second transistor T2.

The first external detection module 20 is connected to the pulse width modulation signal SPWM and electrically connected to the first node Q.

Specifically, the pulse width modulation module 10 is configured to output a signal provided by the second power source terminal V2 to the first node Q under the control of the pulse width signal SPWM to adjust a potential of the first node Q, so as to control the first transistor T1 to be turned on or off, thereby adjusting a pulse width of the driving current flowing through the light emitting device D.

Specifically, the first external detection module 20 is electrically connected to the first node Q, so that the potential of the first node Q can be detected and compensated by the first external detection module 20, and since the threshold voltage value of the second transistor T2 can be determined by the potential difference between the gate of the second transistor T2 and the first node Q, the first external detection module 20 can be used to detect and externally compensate the threshold voltage of the second transistor T2.

It should be noted that the second transistor T2 provided in the embodiment of the present application is a transistor having a driving function in the pulse width modulation module 10, in other words, the second transistor T2 is a PWM driving transistor, a threshold voltage value of the second transistor T2 determines an on time of the second transistor T2, and thus a threshold voltage value of the second transistor T2 determines an emitting time of the light emitting device D.

The driving circuit 100 provided in the embodiment of the present application is electrically connected to the first node Q by setting the first external detecting module 20, so as to detect the threshold voltage of the second transistor T2 in the pulse width modulation module 10, that is, detect the threshold voltage of the PWM driving transistor, so as to perform external compensation on the threshold voltage of the PWM driving transistor, thereby achieving uniform light emission of the light emitting device, and facilitating improvement of the display effect of the display panel.

In some embodiments provided herein, please continue to refer to fig. 1. As shown in fig. 1, in the driving circuit 100, the first external detection module 20 includes a third transistor T3; the pulse width modulation module 10 includes a second transistor T2 and a fourth transistor T4.

Wherein the gate of the second transistor T2 is electrically connected to the third node P, one of the source and the drain of the second transistor T2 is electrically connected to the second power source terminal V2, and the other of the source and the drain of the second transistor T2 is electrically connected to the first node Q.

The signals connected to the second power supply terminal V2 include a constant voltage high level signal and a constant voltage low level signal.

The gate of the third transistor T3 is connected to the pulse width modulation signal SPWM, one of the source and the drain of the third transistor T3 is electrically connected to the first node Q, and the other of the source and the drain of the third transistor T3 is electrically connected to the first sensing terminal Sense 1.

The gate of the fourth transistor T4 is connected to the pulse width modulation signal SPWM, one of the source and the drain of the fourth transistor T4 is connected to the Data signal Data, and the other of the source and the drain of the fourth transistor T4 is electrically connected to the third node P.

Specifically, the fourth transistor T4 is used to supply the Data signal Data to the third node P under the control of the pulse width modulation signal SPWM. The second transistor T2 is configured to provide a signal accessed by the second power source terminal V2 to the first node Q according to the potential of the third node P, so that the first transistor T1 can provide the signal accessed by the first power source terminal V1 to the second node S according to the potential of the first node Q, and when the potential of the second node S rises to a preset potential, the light emitting device D emits light based on the preset potential. The third transistor T3 is used for outputting the signal provided by the first sensing terminal Sense1 to the first node Q under the control of the pulse width modulation signal SPWM. Further, when the first sensing terminal Sense1 is connected to a reset signal (not shown), the third transistor T3 outputs the reset signal to the first node Q; when the first sensing terminal Sense1 is electrically connected to the external ADC module, the third transistor T3 outputs the potential of the first node Q to the external ADC module to Sense and compensate the threshold voltage of the second transistor T2.

Referring to fig. 2, fig. 2 is a timing diagram illustrating a threshold voltage detection of a second transistor of the driving circuit shown in fig. 1. It should be noted that, for convenience of illustration, the driving circuits shown in fig. 1 all employ N-type transistors, however, this should not be construed as limiting the embodiments of the present application, and in some embodiments, the driving circuits 100 may all employ P-type transistors, or some N-type transistors and some P-type transistors. As shown in fig. 2, the combination of the pwm signal SPWM, the Data signal Data, the signal accessed by the first power source terminal V1 and the signal accessed by the second power source terminal V2 sequentially corresponds to the first initialization stage t11 and the first detection stage t12.

In some embodiments, in the first initialization period t11, the signal accessed by the first power supply terminal V1, the signal accessed by the second power supply terminal V2 and the pulse width modulation signal SPWM are all high level signals. At this time, the Data signal Data is a low level signal.

In some embodiments, in the first detection phase t12, the signal accessed by the first power source terminal V1, the signal accessed by the second power source terminal V2, the pulse width modulation signal SPWM, and the Data signal Data are all high-level signals.

Specifically, referring to fig. 2 and fig. 3, fig. 3 is a schematic path diagram of the driving circuit provided in fig. 1 in the first initialization stage at the timing shown in fig. 2.

In the first initialization stage T11, the pulse width modulation signal SPWM is a high level signal, and the second transistor T2 is turned on under the control of the pulse width modulation signal SPWM, so that the Data signal Data is output to the third node P, thereby implementing initialization of the third node P.

Meanwhile, the pulse width modulation signal SPWM is a high level signal, and the third transistor T3 is turned on under the control of the pulse width modulation signal SPWM, so that the third transistor T3 outputs the reset signal provided by the first sensing terminal Sense1 to the first node Q, thereby implementing initialization of the first node Q.

Since the Data signal Data at this stage is a low level signal, V _P -V _Q <Vth2, wherein V _P Potential of P point, V _Q Indicating the potential at the point Q, and Vth2 indicating the threshold voltage of the second transistor T2. The fourth transistor T4 is in an off state.

It should be noted that, in this stage, since the first node Q is a low level signal, the first transistor T1 is in an off state, and the light emitting device D does not emit light.

Specifically, please refer to fig. 1 and fig. 2 again. Since the path diagram of the first detection stage in the driving sequence shown in fig. 2 is identical to the circuit diagram shown in fig. 1, the description is made with reference to fig. 2 and fig. 1.

In the first detection period T12, the pwm signal SPWM is a high level signal, and the second transistor T2 is turned on under the control of the pwm signal SPWM, so as to output the Data signal Data to the third node P. Since the Data signal Data at this stage is a high level signal, in this stage, the second transistor T2 is controlled to be turned on, and a high level signal is output to the third node P, so as to charge the third node P. The gate of the second transistor T2 is electrically connected to the third node P, so that the second transistor T2 is turned on based on the potential of the third node P, the second transistor T2 outputs a signal provided from the second power source terminal V2 to the first node Q, and the second power source terminal V2 is a high-level signal, and thus the first node Q can be charged through the second transistor T2 and the second power source terminal V2. When the potential at the point Q rises to V _P -V _Q = Vth2, the second transistor T2 is in an off state, and the potential of the first node Q does not rise any more.

Meanwhile, the pulse width modulation signal SPWM is a high level signal, the third transistor T3 is turned on under the control of the pulse width modulation signal SPWM, so that the first sensing terminal Sense1 is electrically connected to the external ADC module, and the potential of the first node Q can be sensed and obtained, and then the threshold voltage value of the second transistor T2 can be sensed and obtained, so as to implement sensing and external compensation of the threshold voltage of the second transistor T2.

It should be noted that, in the process of detecting the threshold voltage of the second transistor T2, i.e. in the first initialization period T11 and the first detection period T12, both the first power source terminal V1 and the second power source terminal V2 are high level signals, when the first external detection module 20 detects the threshold voltage of the second transistor T2, the second power source terminal V2 can access the constant voltage high level signal, and the first power source terminal V1 can also access the constant voltage high level signal.

It should be noted that when the first external detection module 20 does not detect the threshold voltage of the second transistor T2, the second power source terminal V2 is connected to the constant voltage low level signal.

Referring to fig. 4, fig. 4 is a second structural diagram of a driving circuit according to an embodiment of the present disclosure. As shown in fig. 4, the driving circuit provided in the embodiment of the present application is different from that of fig. 1 in that: in the driving circuit 200 provided in this embodiment, a pulse amplitude modulation module 30 is further included.

The pwm module 30 is connected to the pwm signal SPAM and the Data signal Data, and the pwm module 30 is electrically connected to the first node Q.

Specifically, the pwm module 30 is configured to output the Data signal Data to the first node Q under the control of the pwm signal SPAM, so that the first transistor T1 is turned on based on the potential of the first node Q to charge the second node S. When the potential of the second node S is raised to the preset potential, the light emitting device D emits light based on the preset potential. The pulse amplitude modulation module 30 thus serves to adjust the pulse amplitude of the driving current flowing through the light emitting device D.

Referring to fig. 4, the driving circuit 200 of the present embodiment further includes a second external detection module 40.

The second external detection module 40 is connected to the pulse amplitude modulation signal SPAM and electrically connected to the second node S.

Specifically, the second external detection module 40 is electrically connected to the second node S, so that the potential of the second node S can be detected and compensated by the second external detection module 40. Since the threshold voltage of the first transistor T1 can be determined by the potential difference between the first node Q and the second node S, the second external detection module 40 can be used to detect and externally compensate the threshold voltage of the first transistor T1.

The driving circuit 200 provided in the embodiment of the present application is electrically connected to the second node S by adding the second external detection module 40, so as to detect the threshold voltage of the first transistor T1, perform external compensation on the threshold voltage of the first transistor T1, realize uniform light emission of the light emitting device D, and improve the light emitting effect of the light emitting device D.

In some embodiments provided herein, please continue with FIG. 4. As shown in fig. 4, in the driving circuit 200, the pulse amplitude modulation module 30 includes a fifth transistor T5; the second external detection module 40 includes a sixth transistor T6.

Wherein, the gate of the fifth transistor T5 is connected to the pulse amplitude modulation signal SPAM, one of the source and the drain of the fifth transistor T5 is connected to the Data signal Data, and the other of the source and the drain of the fifth transistor T5 is electrically connected to the first node Q.

Specifically, the fifth transistor T5 is configured to supply the Data signal Data to the first node Q under the control of the pulse amplitude modulation signal SPAM. So that the first transistor T1 is turned on or off based on the potential of the first node Q.

The gate of the sixth transistor T6 is connected to the pulse amplitude modulation signal SPAM, one of the source and the drain of the sixth transistor T6 is electrically connected to the second sensing terminal Sense2, and the other of the source and the drain of the sixth transistor T6 is electrically connected to the second node S.

Specifically, the sixth transistor T6 is configured to output the signal provided by the second Sense terminal Sense2 to the second node S under the control of the pulse amplitude modulation signal SPAM. Further, when the second sensing terminal Sense2 is connected to a reset signal (not shown), the sixth transistor T6 outputs the reset signal to the second node S; when the second sensing terminal Sense2 is electrically connected to an external ADC module (not shown), the sixth transistor T6 outputs the potential of the second node S to the external ADC module to Sense and externally compensate the threshold voltage of the first transistor T1.

Referring to fig. 5, fig. 5 is a timing diagram illustrating the threshold voltage detection of the first transistor of the driving circuit shown in fig. 4. It should be noted that the driving circuits shown in fig. 5 all use N-type transistors, but this should not be construed as limiting the present application. In some embodiments, the driving circuits 200 may also all employ P-type transistors; in some embodiments, the driving circuit 200 may partially employ a P-type transistor and partially employ an N-type transistor.

As shown in fig. 5, the combination of the pwm signal SPWM, the pwm signal SPAM, the Data signal Data, the signal accessed by the first power source terminal V1, and the signal accessed by the second power source terminal V2 sequentially corresponds to the second initialization stage t21 and the second charging and detecting stage t22.

In some embodiments, in the second initialization period t21, the signal switched in by the first power supply terminal V1 and the pulse width modulation signal SPWM are both high level signals. At this time, the signal connected to the second power source terminal V2, the pulse amplitude modulation signal SPAM, and the Data signal Data are all low-level signals.

In some embodiments, in the second charging and detecting phase t22, the signal connected to the first power source terminal V1, the pulse amplitude modulation signal SPAM and the Data signal Data are all high level signals. At this time, the signal accessed by the second power supply terminal V2 and the pulse width modulation signal SPWM are both low level signals.

Specifically, referring to fig. 5 and fig. 6, fig. 6 is a path schematic diagram of the driving circuit provided in fig. 4 in the second initialization stage under the timing sequence shown in fig. 5.

In the second initialization phase T21, the pwm signal SPWM is a high level signal, and the third transistor T3 is turned on under the control of the pwm signal SPWM, so that the third transistor T3 outputs the reset signal provided by the first sensing terminal Sense1 to the first node Q, thereby implementing initialization of the first node Q.

Meanwhile, in the second initialization stage T21, the pulse width modulation signal SPWM is a high level signal, and the second transistor T2 is turned on under the control of the pulse width modulation signal SPWM, so that the Data signal Data is output to the third node P, thereby implementing initialization of the third node P. It should be noted that, in this caseStage, if the Data signal Data is a low level signal, then V _P -V _Q <Vth2, the second transistor T2 is in an off state.

It should be noted that, in this stage, since the first node Q is a low level signal, the first transistor T1 is in an off state, and the light emitting device D does not emit light. In this stage, since the pulse amplitude modulation signal SPAM is a low level signal, both the fifth transistor T5 and the sixth transistor T6 are in the off state.

Specifically, referring to fig. 5 and fig. 7, fig. 7 is a schematic path diagram of the driving circuit provided in fig. 4 in the second detection stage under the driving timing shown in fig. 5.

In the second detection phase T22, the pwm signal SPAM is a high level signal, and the fifth transistor T5 is turned on under the control of the pwm signal SPAM, so that the fifth transistor T5 outputs the Data signal Data to the first node Q, thereby charging the first node Q.

Meanwhile, the pwm signal SPAM is a high level signal, and the sixth transistor T6 is turned on under the control of the pwm signal SPAM, so that the sixth transistor T6 outputs the potential of the second node S to the second sensing terminal Sense2, so that the external ADC module senses and compensates the threshold voltage of the first transistor T1.

Since the pwm signal SPWM at this stage is a low level signal, the third transistor T3, the fourth transistor T4, and the second transistor T2 are in the off state.

In some embodiments provided in the present application, please refer to fig. 8, and fig. 8 is a third structural diagram of a driving circuit provided in the embodiments of the present application. As shown in fig. 8, the present embodiment provides a driving circuit which is different from the aforementioned driving circuit in that: in the driving circuit 300 provided in the present application, the pulse width modulation module 10 further includes a second capacitor C2.

The first end of the second capacitor C2 is connected to the SWEEP signal SWEEP, and the second end of the second capacitor C2 is electrically connected to the third node P.

Specifically, the potential of the third node P is adjusted based on the coupling action of the SWEEP signal SWEEP and the second capacitor C2, so as to control the on-time of the second transistor T2, and further control the light emitting time of the light emitting device D.

The driving circuit 300 provided in the embodiment of the application is electrically connected to the third node P by additionally arranging the second capacitor C2, and the second capacitor C2 is connected to the SWEEP signal SWEEP, so as to control the on-time of the second transistor T2, further control the potential of the first node Q, further control the on-time of the first transistor T1, and then control the light emitting time of the light emitting device D.

Referring to fig. 9, fig. 9 is a timing diagram of light emission of the driving circuit shown in fig. 8. It is to be noted that the driving circuits shown in fig. 9 each employ an N-type transistor. As shown in fig. 9, the combination of the pulse width modulation signal SPWM, the pulse amplitude modulation signal SPAM, the Data signal Data, the signal connected to the first power supply terminal V1, the signal connected to the second power supply terminal V2, and the SWEEP signal SWEEP corresponds to the third initialization phase t31, the Data writing phase t32, and the light emitting phase t33 in sequence.

In some embodiments, in the third initialization period t31, the pulse width modulation signal SPWM, the Data signal Data, and the SWEEP signal SWEEP are all high-level signals, and the signal of the first power source terminal V1, the signal of the second power source terminal V2, and the pulse amplitude modulation signal SPAM are all low-level signals.

In some embodiments, in the Data writing phase t32, the pulse amplitude modulation signal SPAM and the Data signal Data are high level signals, and the signal of the first power source terminal V1, the signal of the second power source terminal V2, the pulse amplitude modulation signal SPAM and the SWEEP signal SWEEP are low level signals.

In some embodiments, during the light emitting period t33, the signal of the first power source terminal V1 is a high level signal, and the pulse amplitude modulation signal SPAM, the pulse width modulation signal SPWM, the Data signal Data, and the signal of the second power source terminal V2 are all low level signals. At this time, the potential of the SWEEP signal SWEEP gradually rises.

Specifically, referring to fig. 9 and fig. 10, fig. 10 is a schematic path diagram of the driving circuit provided in fig. 8 in the third initialization stage under the driving timing shown in fig. 9.

In the third initialization phase T31, the pwm signal SPWM is a high level signal, and the third transistor T3 is turned on under the control of the pwm signal SPWM, so that the third transistor T3 outputs a reset signal (not shown in the figure) provided by the first sensing terminal Sense1 to the first node Q, thereby initializing the first node Q.

Meanwhile, the pulse width modulation signal SPWM is a high level signal, and the fourth transistor T4 is turned on under the control of the pulse width modulation signal SPWM, so that the fourth transistor T4 outputs the Data signal Data to the third node P to implement initialization of the third node P. At this time, the SWEEP signal SWEEP is maintained as a high level signal, and the second capacitor C2 does not affect the potential change of the third node P.

Note that, in this stage, the potential of the third node P has not yet risen to a state that can turn on the second transistor, and therefore, the second transistor T2 is turned off in the third initialization stage T31. The first node Q is at a low voltage level, and the first transistor T1 is turned off.

In this stage, since the pwm signal SPAM is a low level signal, the fifth transistor T5 and the sixth transistor T6 are turned off.

Specifically, referring to fig. 11 and fig. 9, fig. 11 is a schematic path diagram of a data writing stage of the driving circuit provided in fig. 8 at the driving timing shown in fig. 9.

In the Data writing phase T32, the pulse amplitude modulation signal SPAM is a high level signal, and the fifth transistor T5 is turned on under the control of the pulse amplitude modulation signal SPAM, so that the fifth transistor T5 outputs the Data signal Data to the first node Q to charge the first node Q. At this time, even though the first transistor T1 is turned on based on the potential of the first node Q, the light emitting device D does not emit light because the potentials of the first power terminal V1 and the second power terminal V2 are both 0V.

Meanwhile, the pwm signal SPWM is a high level signal, and the sixth transistor T6 is turned on under the control of the pwm signal SPAM, so that the sixth transistor T6 outputs a reset signal (not shown in the figure) to the second node S to initialize the second node S.

It should be noted that, in this stage, in order to avoid raising the potential of the third node P to the level that the second transistor T2 is turned on in the previous stage, the SWEEP signal SWEEP in this stage is a low level signal, that is, under the coupling action of the second capacitor C2, the SWEEP signal SWEEP pulls down the potential of the third node P to ensure that the second transistor T2 is in the off state.

In addition, in this stage, since the pulse width modulation signal SPWM is a low level signal, the fourth transistor T4 and the third transistor T3 are turned off.

Specifically, referring to fig. 12 and fig. 9, fig. 12 is a schematic path diagram of the light-emitting stage of the driving circuit provided in fig. 8 at the driving timing shown in fig. 9.

In the light-emitting period T33, the pwm signal SPAM and the pwm signal SPWM are both low level signals, the third transistor T3, the fourth transistor T4, the fifth transistor T5 and the sixth transistor T6 are all turned off, and the first capacitor C1 is used for maintaining the potential difference between the first node Q and the second node S, so that the first transistor T1 maintains the on state. The signal supplied from the first power source terminal V1 is a high level signal, and as shown in fig. 9, the signal supplied from the first power source terminal V1 is 12V. The first transistor T1 outputs a high level signal of the first power source terminal V1 to the second node S to pull up the potential of the second node S, and when the potential of the second node S rises to a preset potential, the light emitting device D emits light based on the preset potential.

Meanwhile, the potential of the frequency SWEEP signal SWEEP gradually rises, and the potential of the third node P is raised by the frequency SWEEP signal SWEEP through the coupling action of the second capacitor C2, so that the second transistor T2 is turned on, and thus the second transistor T2 outputs the potential of the second power source terminal V2 to the first node Q, as shown in fig. 9, the signal provided by the second power source terminal V2 is 0V. Since the signal provided from the second power terminal V2 is a low level signal, the potential of the first node Q is pulled down, the first transistor T1 is turned off, and the light emitting device D stops emitting light.

Since different Data voltages Data can be output to the third node P based on the turn-on of the fourth transistor T4, the light emitting time of the light emitting device D is controlled by writing different potentials to the third node P in the third initialization phase T31.

In another aspect of the present application, a display panel is provided, which includes the driving circuit in at least one embodiment. It can be understood that, the display panel provided by the application is electrically connected to the first node through the first external detection module, so that the threshold voltage of the PWM driving transistor in the pulse width modulation module is detected, the threshold voltage of the PWM driving transistor is externally compensated, the uniformity of image display is improved, and the display effect of the display panel is improved.

The above embodiments are merely examples, and not intended to limit the scope of the present application, and all modifications, equivalents, and flow charts using the contents of the specification and drawings of the present application, or those directly or indirectly applied to other related arts, are included in the scope of the present application.

Claims

1. A driver circuit, comprising:

and the first external detection module is connected with the pulse width modulation signal and is electrically connected with the first node, and the first external detection module is used for detecting and compensating the threshold voltage of the second transistor.

2. The driving circuit according to claim 1, wherein the signals connected to the second power terminal include a constant voltage high level signal and a constant voltage low level signal.

3. The driving circuit as claimed in claim 2, wherein when the first external detection module detects the threshold voltage of the second transistor, the second power terminal is connected to the constant voltage high level signal; when the first external detection module does not detect the threshold voltage of the second transistor, the second power supply end is connected to the constant-voltage low-level signal.

4. The driving circuit of claim 1, wherein the first external detection module comprises a third transistor;

5. The driving circuit of claim 1, wherein the pulse width modulation module further comprises a fourth transistor;

a grid electrode of the fourth transistor is connected with the pulse width modulation signal, one of a source electrode and a drain electrode of the fourth transistor is connected with the data signal, and the other of the source electrode and the drain electrode of the fourth transistor is electrically connected with a third node;

a gate of the second transistor is electrically connected to the third node, one of a source and a drain of the second transistor is electrically connected to the second power source terminal, and the other of the source and the drain of the second transistor is electrically connected to the first node.

6. The driving circuit of claim 5, wherein the pulse width modulation module further comprises a second capacitor;

7. The driving circuit according to any of claims 1-6, wherein the driving circuit further comprises a pulse amplitude modulation module;

8. The driving circuit of claim 7, wherein the pulse amplitude modulation module comprises a fifth transistor;

9. The driving circuit of claim 7, further comprising a second external detection module;

10. The driving circuit of claim 9, wherein the second external detection module comprises a sixth transistor;

11. A display panel comprising the driver circuit according to any one of claims 1 to 10.