CN115206902B - Chip packaging structure and manufacturing method thereof - Google Patents
Chip packaging structure and manufacturing method thereof Download PDFInfo
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- CN115206902B CN115206902B CN202211133572.8A CN202211133572A CN115206902B CN 115206902 B CN115206902 B CN 115206902B CN 202211133572 A CN202211133572 A CN 202211133572A CN 115206902 B CN115206902 B CN 115206902B
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 28
- 238000004806 packaging method and process Methods 0.000 title claims abstract description 11
- 230000000903 blocking effect Effects 0.000 claims abstract description 126
- 239000000758 substrate Substances 0.000 claims abstract description 118
- 239000003822 epoxy resin Substances 0.000 claims abstract description 52
- 229920000647 polyepoxide Polymers 0.000 claims abstract description 52
- 230000004888 barrier function Effects 0.000 claims abstract description 42
- 238000000034 method Methods 0.000 claims abstract description 24
- 239000004593 Epoxy Substances 0.000 claims description 25
- 238000003466 welding Methods 0.000 claims description 19
- 238000005476 soldering Methods 0.000 claims description 17
- 238000000465 moulding Methods 0.000 claims description 2
- 239000000463 material Substances 0.000 abstract description 18
- 229920005989 resin Polymers 0.000 abstract description 15
- 239000011347 resin Substances 0.000 abstract description 15
- 230000008569 process Effects 0.000 abstract description 14
- 238000010030 laminating Methods 0.000 abstract description 3
- 230000006872 improvement Effects 0.000 description 12
- 239000012528 membrane Substances 0.000 description 8
- 239000002184 metal Substances 0.000 description 5
- 229910052751 metal Inorganic materials 0.000 description 5
- 239000004033 plastic Substances 0.000 description 4
- 229910000679 solder Inorganic materials 0.000 description 4
- 230000006378 damage Effects 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 230000005496 eutectics Effects 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 230000003014 reinforcing effect Effects 0.000 description 2
- 208000027418 Wounds and injury Diseases 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
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- 230000003116 impacting effect Effects 0.000 description 1
- 208000014674 injury Diseases 0.000 description 1
- 238000003754 machining Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 238000007493 shaping process Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/315—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the encapsulation having a cavity
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H3/00—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators
- H03H3/007—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks
- H03H3/02—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks for the manufacture of piezoelectric or electrostrictive resonators or networks
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H3/00—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators
- H03H3/007—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks
- H03H3/08—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks for the manufacture of resonators or networks using surface acoustic waves
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H9/00—Networks comprising electromechanical or electro-acoustic devices; Electromechanical resonators
- H03H9/02—Details
- H03H9/05—Holders; Supports
- H03H9/10—Mounting in enclosures
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H9/00—Networks comprising electromechanical or electro-acoustic devices; Electromechanical resonators
- H03H9/46—Filters
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Acoustics & Sound (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
The invention discloses a chip packaging structure and a manufacturing method thereof, wherein the chip packaging structure comprises a substrate, at least one chip, a plurality of conductive bonding parts and an epoxy resin film, wherein the chip is arranged above the substrate through the conductive bonding parts; the blocking structure is arranged on the part of the upper surface of the substrate, which is outside the conductive combination part, and is configured to block the epoxy resin film from entering the inner side area of the blocking structure; the epoxy resin film coats the upper surface and the side surface of the chip and the outer side surface of the barrier structure, extends to the upper surface of the substrate along the side surface of the chip and the outer side surface of the barrier structure, and forms a cavity among the epoxy resin film, the chip, the substrate and the barrier structure. In the laminating process, the blocking structural member can effectively block resin materials overflowing from the epoxy resin film from entering a cavity area between the chip and the substrate, and prevent the conductive combination part and the cavity area from being polluted.
Description
Technical Field
The invention relates to the technical field of semiconductor packaging, in particular to a chip packaging structure and a manufacturing method thereof.
Background
As shown in fig. 1, in a conventional filter chip package structure, a functional surface of a chip 2 is flip-chip bonded to a substrate 1 through metal ball studs, and an epoxy film 4 covers a whole surface of a portion of an upper surface of the substrate 1 and a non-functional surface of the chip 2, so that a cavity is formed between the chip 2 and the substrate 1 and between the chip 2 and the epoxy film 4.
However, the conventional package structure has the following two problems: firstly, when the epoxy resin film 4 is pressed on the surface of the substrate 1, resin overflowing from the epoxy resin film 4 easily enters the cavity to pollute the effective area of the ball column and the chip, and the performance of the filter product is reduced; secondly, there is a risk that the side epoxy film 4 is washed away during product operation due to the pressure difference between the inside and the outside of the package structure.
Disclosure of Invention
The invention aims to provide a chip packaging structure and a manufacturing method thereof, which are used for preventing resin materials overflowing from an epoxy resin film from entering a cavity area between a chip and a substrate and preventing a conductive combination part and the cavity area from being polluted.
In order to achieve one of the above objects, an embodiment of the present invention provides a chip package structure, including a substrate, at least one chip, a plurality of conductive bonding portions, and an epoxy film, wherein a plurality of soldering regions are disposed on an upper surface of the substrate, the chip is disposed above the substrate through the conductive bonding portions, and the conductive bonding portions are disposed corresponding to the soldering regions, wherein the chip package structure further includes a blocking structure disposed on a portion of the upper surface of the substrate outside the conductive bonding portions, the blocking structure is configured to block the epoxy film from entering an inner region of the blocking structure;
the epoxy resin film covers the upper surface and the side surface of the chip and the outer side surface of the barrier structure and extends to the upper surface of the substrate along the side surface of the chip and the outer side surface of the barrier structure, and a cavity is formed among the epoxy resin film, the chip, the substrate and the barrier structure.
As a further improvement in one embodiment of the present invention, the blocking structure surrounds an upper surface area of the substrate disposed outside the conductive bonding portion.
As a further improvement in an embodiment of the present invention, an inner side of the blocking structure does not exceed the chip edge region.
As a further improvement in an embodiment of the present invention, the blocking structure includes a blocking portion configured to block the epoxy film from entering the cavity, and a drainage portion configured to drain the epoxy film away from the conductive bond.
As a further improvement in one embodiment of the present invention, the blocking structure is an L-shaped structure, the current guiding portion is disposed on the upper surface of the substrate, and the blocking portion protrudes toward the upper side of the substrate along one end of the current guiding portion close to the conductive bonding portion.
As a further improvement in one embodiment of the present invention, a partial region of the upper surface of the substrate is recessed inward to form a groove, and the groove is disposed on a side of the blocking structure far from the conductive bonding portion.
As a further improvement in one embodiment of the present invention, an inner side surface of the groove and a side surface of the blocking structural member away from the conductive bonding portion are disposed on a same vertical line.
As a further improvement in an embodiment of the present invention, the groove surrounds the blocking structure.
As a further improvement in an embodiment of the present invention, the bottom of the groove is provided with a step structure, and the depth of the groove gradually increases toward a direction away from the blocking structure.
An embodiment of the present invention further provides a method for manufacturing a chip package structure, including:
providing a substrate, wherein the upper surface of the substrate is provided with a plurality of welding areas, and a blocking structural member is arranged at part of the upper surface of the substrate outside the welding areas;
providing at least one chip, and arranging the chip above the substrate corresponding to the welding area through a conductive bonding part;
providing an epoxy resin film, extruding the epoxy resin film to coat the upper surface and the side surface of the chip and the outer side surface of the barrier structure member, and extending to the upper surface of the substrate along the side surface of the chip and the outer side surface of the barrier structure member, wherein a cavity is formed among the epoxy resin film, the chip, the substrate and the barrier structure member.
As a further improvement in one embodiment of the present invention, providing a substrate, where a plurality of soldering regions are disposed on an upper surface of the substrate, and a blocking structure is disposed at a partial region of the upper surface of the substrate outside the soldering regions, specifically includes:
a blocking structural part is arranged on the upper surface of the substrate around the outer side of the welding area;
arranging the blocking structure and the welding region closest to the blocking structure at intervals of at least 30 micrometers, wherein the inner side surface of the blocking structure is not beyond the edge region of the chip;
setting the height of the blocking structural part to be not more than 1/2 of the height of the conductive bonding part.
As a further improvement in an embodiment of the present invention, providing a substrate, where a plurality of soldering regions are disposed on an upper surface of the substrate, and a blocking structure is disposed at a partial region of the upper surface of the substrate outside the soldering regions, specifically, the method further includes:
the blocking structure is arranged in an L-shaped structure and comprises a blocking part and a drainage part, wherein the drainage part is arranged on the upper surface of the substrate, and the blocking part is arranged along the edge of the drainage part close to one end of the conductive combination part towards the protruding part above the substrate.
As a further improvement in one embodiment of the present invention, before the providing at least one chip, the method further includes:
and on one side of the blocking structural member, which is far away from the conductive combination part, the partial area of the upper surface of the substrate is inwards sunken to form a groove.
As a further improvement in one embodiment of the present invention, on a side of the blocking structure far away from the conductive bonding portion, a groove is formed by recessing a partial region of the upper surface of the substrate, which specifically includes:
arranging the groove around the blocking structural part, and arranging the inner side surface of the groove and one side surface of the blocking structural part far away from the conductive combination part on the same vertical line;
and forming the bottom of the groove into a step structure, wherein the depth of the groove is gradually increased towards the direction far away from the blocking structural part.
The invention has the beneficial effects that: the blocking structural part is arranged on the partial area of the upper surface of the substrate on the outer side of the conductive joint part, and the blocking structural part does not exceed the edge area of the chip.
Drawings
Fig. 1 is a schematic diagram of a chip package structure in the conventional technology.
Fig. 2 is a schematic flow chart illustrating a manufacturing method of a chip package structure according to an embodiment of the invention.
Fig. 3 to 7 are process steps of a method for manufacturing a corresponding chip package structure according to an embodiment of the invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the technical solutions of the present invention will be clearly and completely described below with reference to the specific embodiments of the present invention and the accompanying drawings. It is to be understood that the described embodiments are merely exemplary of the invention, and not restrictive of the full scope of the invention. All other embodiments, which can be obtained by a person skilled in the art without any inventive step based on the embodiments of the present invention, are within the scope of the present invention.
Reference will now be made in detail to embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to the same or similar elements or elements having the same or similar function throughout. The embodiments described below with reference to the accompanying drawings are illustrative only for the purpose of explaining the present invention, and are not to be construed as limiting the present invention.
For convenience in explanation, the description herein uses terms indicating relative spatial positions, such as "upper," "lower," "rear," "front," and the like, to describe one element or feature's relationship to another element or feature as illustrated in the figures. The term spatially relative position may encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as "below" or "above" other elements or features would then be oriented "below" or "above" the other elements or features. Thus, the exemplary term "below" can encompass both a spatial orientation of below and above.
As shown in fig. 7, a chip package structure according to an embodiment of the present invention includes a substrate 1, at least one chip 2, a plurality of conductive bonding portions 3, and an epoxy film 4.
The substrate 1 has an upper surface and a lower surface opposite to the upper surface, and the upper surface of the substrate 1 is provided with a plurality of soldering regions 11.
Illustratively, in the present embodiment, a chip 2 is provided, the chip 2 is disposed on the upper surface of the substrate 1 and electrically connected to the substrate 1, and specifically, the chip 2 has a functional surface provided with pads and a non-functional surface opposite to the functional surface, and the functional surface of the chip 2 is disposed toward the substrate 1 and electrically connected to the substrate 1 through the pads. In other embodiments of the present invention, two or more chips may be disposed on the upper surface of the substrate 1 to meet different requirements of products.
More specifically, the chip 2 is disposed above the substrate 1 through the conductive bonding portion 3, and the conductive bonding portion 3 is disposed corresponding to the bonding area 11 on the upper surface of the substrate 1 and the bonding pad on the functional surface of the chip 2. In the present embodiment, the conductive bonding portion 3 is a metal ball stud, which may be a solder ball, a gold ball eutectic solder, or the like. The specific setting height of the metal ball column is not limited, and can be adjusted according to different requirements of products or the subsequent requirement on the height of a cavity formed by manufacturing.
Further, the chip package structure further includes a blocking structure 5, the blocking structure 5 is disposed in a partial region of the upper surface of the substrate 1 outside the conductive bonding portion 3, the blocking structure 5 is configured to block the epoxy resin film 4 from entering into an inner region of the blocking structure 5, i.e., the blocking structure 5 is close to the conductive bonding portion 3 by blocking the epoxy resin film 4 from entering into the blocking structure.
The epoxy resin film 4 covers the upper surface and the side surface of the chip 2 and the outer side surface of the barrier structure 5, and extends to the upper surface of the substrate 1 along the side surface of the chip 2 and the outer side surface of the barrier structure 5, and a cavity 6 is formed among the epoxy resin film 4, the chip 2, the substrate 1 and the barrier structure 5. The epoxy resin film 4 is in a hardened state after being baked at a high temperature, the chip 2 and the substrate 1 are firmly bonded together to form the cavity 6, and a certain protection effect is achieved on the functional surface of the chip 2, but in the process of laminating the epoxy resin film 4, the chip 2 and the substrate 1, the conductive bonding part 3 and the cavity 6 are easily polluted by resin materials overflowing from the epoxy resin film 4, so that the blocking structural member 5 provided by the invention can well block the resin materials overflowing from the epoxy resin film 4, and prevent the conductive bonding part 3 and the cavity 6 from being polluted by the resin materials.
Of course, in other embodiments of the present invention, a DAF (Die Attachment Film) Film may be used instead of the epoxy Film 4, and the substrate 1 and the chip 2 can be fixed and combined to form the cavity 6, and the cavity is cured after being baked at a high temperature, so that the package structure can be fixed and protected.
Specifically, the blocking structure 5 surrounds the upper surface area of the substrate 1 outside the conductive bonding portion 3, that is, the blocking structure 5 surrounds the conductive bonding portion 3 to form a square or annular structure, or surrounds the conductive bonding portion 3 to form a structure with other shapes.
More specifically, the inner side of the barrier structure 5, i.e. the side of the barrier structure 5 facing the conductive bond 3, is not arranged beyond the edge area of the chip 2, further reducing the possibility of the epoxy film 4 entering the cavity 6. Meanwhile, in consideration of the precision of the machine for actually mounting the chip 2, the spacing between the blocking structural member 5 and the nearest conductive bonding part 3 is at least 30 micrometers, so that the blocking structural member 5 is prevented from being impacted by the machine in the manufacturing process of the packaging structure when the chip 2 is mounted, and the chip 2 is prevented from being damaged.
In the preferred embodiment of the present invention, the upper surface of the blocking structure 5 is in contact with the lower surface of the chip 2, so that the resin material overflowing from the epoxy resin film 4 in the subsequent process can be completely blocked from entering the cavity region between the chip 2 and the substrate 1. However, considering that the conductive bonding portion 3 may be in a molten state during an actual manufacturing process, such as reflow soldering, it is difficult to ensure that the height difference between the lower surface of the chip 2 and the upper surface of the substrate 1 in the final manufactured product is stable, i.e., it is difficult to determine the specific height of the blocking structure 5 during the actual manufacturing process. If the height of the blocking structure 5 is set too high, the blocking structure 5 may easily damage the functional surface of the chip 2 when the conductive bonding portion 3 is melted during the reflow process to lower the height of the chip 2, so in the embodiment of the present invention, the height of the blocking structure 5 is set to be not more than 1/2 of the height of the conductive bonding portion 3 before the reflow process. Meanwhile, the height of the blocking structure 5 cannot be set too low, and if the height of the blocking structure 5 is set too low, it is difficult to ensure whether the blocking structure 5 can effectively block the resin material overflowing from the epoxy resin film 4 from entering the cavity region between the chip 2 and the substrate 1. The invention does not limit the specific setting value of the height of the blocking structural member 5, and can play a role in effectively blocking resin materials overflowing from the epoxy resin film 4 while ensuring that the functional surface of the chip 2 cannot be damaged by the upper surface of the blocking structural member 5 in the subsequent process.
Specifically, the blocking structure 5 includes a blocking portion 51 and a drainage portion 52, the blocking portion 51 is configured to block the epoxy resin film 4 from entering the cavity 6, and the drainage portion 52 is configured to drain the epoxy resin film 4 in a direction away from the conductive bonding portion 3.
The blocking structure 5 is specifically an L-shaped structure, the drainage portion 52 is disposed on the upper surface of the substrate 1, the blocking portion 51 protrudes toward the upper side of the substrate 1 along one end of the drainage portion 52 close to the conductive bonding portion 3, and the blocking portion 51 is disposed at a side surface close to the conductive bonding portion 3 and does not exceed the edge region of the chip 2. Specifically, one side of the drainage portion 52 away from the conductive bonding portion 3 is aligned with the side surface of the chip 2, the protruding height of the blocking portion 51 meets the specific height setting requirement for the blocking structure 5, and the blocking portion 51 and the drainage portion 52 are set in other sizes. Of course, in the present embodiment, the epoxy resin film 4 covers one side surface of the barrier section 51 away from the conductive bonding section 3, and extends along the side surface to the upper surface of the drain section 52 and the upper surface of the substrate 1.
Preferably, the barrier structure 5 is made of ink, so that the manufacturing cost is low. Of course, in other embodiments of the present invention, the material of the barrier structure 5 may also be copper or other high temperature resistant materials.
Further, partial region of the upper surface of the substrate 1 is inwards sunken to form a groove 12, the groove 12 is arranged on one side, away from the conductive joint part 3, of the blocking structure 5, specifically, the groove 12 is arranged in the substrate, away from one side of the conductive joint part 3, of the drainage part 52, the epoxy resin film 4 can be extended and filled into the groove 12 through drainage of the drainage part 52, the binding force between the epoxy resin film 4 and the substrate 1 is enhanced, and the product performance is improved. The specific shape and size of the groove 12 is not limited in this respect and can be designed according to practical requirements.
In the specific embodiment of the present invention, the inner side surface of the groove 12 and the side surface of the blocking structure 5 far from the conductive bonding portion 3 are disposed on the same vertical line, that is, the inner side surface of the groove 12 and the side surface of the drainage portion 52 far from the conductive bonding portion 3 are disposed on the same vertical line, specifically, the inner side surface of the groove 12 and the side surface of the drainage portion 52 far from the conductive bonding portion 3 are aligned with the side surface of the chip 2, and the epoxy film 4 directly extends and fills the groove 12 through the upper surface of the drainage portion 52.
More specifically, the grooves 12 form a square or ring structure around the barrier structure 5, further enhancing the bonding force between the epoxy molding film 4 and the substrate 1. The invention does not limit the specific shape structure and size formed by enclosing the groove 12, and only needs to ensure that the area enclosed by the barrier structural member 5 completely falls into the area enclosed by the groove 12.
For further reinforcing the cohesion between epoxy resin membrane 4 and the base plate 1, recess 12 bottom sets up to a stair structure, and towards keeping away from 5 directions of blockking the structure, the degree of depth of recess 12 increases gradually, certainly, does not do specific requirements to stair structure's step number in this embodiment, and the step number is more, and the frictional force of epoxy resin membrane 4 and recess 12 internal surface is bigger, and then the cohesion of epoxy resin membrane 4 and base plate 1 is bigger, so the step number of stair structure can design the adjustment according to actual need. Of course, in other embodiments of the invention, the bottom of the groove 12 may have a wavy or other shape, or the depth of the groove 12 may gradually decrease in a direction away from the barrier structure 5. Any variations in the configuration and dimensions of the recess 12 based on this configuration are within the scope of the present invention.
As shown in fig. 2, an embodiment of the present invention further provides a method for manufacturing a chip package structure, including the steps of:
s1: providing a substrate, wherein the upper surface of the substrate is provided with a plurality of welding areas, and the partial area of the upper surface of the substrate outside the welding areas is provided with a blocking structural member.
S2: and providing at least one chip, and arranging the chip above the substrate corresponding to the welding area through the conductive bonding part.
S3: and providing an epoxy resin film, extruding the epoxy resin film to coat the upper surface and the side surface of the chip and the outer side surface of the barrier structure member, extending to the upper surface of the substrate along the side surface of the chip and the outer side surface of the barrier structure member, and forming a cavity among the epoxy resin film, the chip, the substrate and the barrier structure member.
As shown in fig. 3, corresponding to step S1, a substrate 1 is provided, a plurality of soldering regions 11 are disposed on the upper surface of the substrate 1, and a blocking structure 5 is disposed on a partial region of the upper surface of the substrate 1 outside the soldering regions 11, which specifically includes:
the specific setting requirements of the barrier structure 5 are related to the different chips to be mounted subsequently and the different manufacturing processes of the products. The specific position of the blocking structure 5 on the upper surface of the substrate 1 is set according to the specific size of the chip 2 required by a subsequent product, specifically, the blocking structure 5 is arranged on the partial region of the upper surface of the substrate 1 outside the welding region 11, and the inner side surface of the blocking structure 5 does not exceed the edge region of the subsequent chip 2 required to be mounted.
Specifically, the blocking structure 5 is arranged around the upper surface area of the substrate 1 outside the welding area 11, that is, the blocking structure 5 surrounds the welding area 11 to form a square or annular structure, or surrounds the blocking structure to form a structure with other shapes.
More specifically, in consideration of the precision of the machine actually used for mounting the chip 2 in the subsequent manufacturing process, the spacing between the barrier structure 5 and the nearest welding region 11 is at least 30 μm, so that the machine in the packaging structure manufacturing process is prevented from impacting the barrier structure 5 when mounting the chip 2, and the chip 2 is prevented from being damaged.
In the preferred embodiment of the present invention, the blocking structure 5 is disposed such that the upper surface thereof is in contact with the lower surface of the chip 2, thereby completely blocking the resin material overflowing from the epoxy resin film 4 in the subsequent process from entering the cavity region between the chip 2 and the substrate 1. However, considering that the conductive bonding portion 3 provided in step S2 may be in a molten state during a reflow process or the like in an actual manufacturing process, it is difficult to ensure that the height difference between the lower surface of the chip 2 and the upper surface of the substrate 1 in the final manufactured product is stable, i.e., it is difficult to determine the specific height of the barrier structure 5 in the actual manufacturing process. If the height of the blocking structure 5 is set too high, the blocking structure 5 may easily damage the functional surface of the chip 2 when the conductive bonding portion 3 is melted during the reflow process to lower the height of the chip 2, so in the embodiment of the present invention, the height of the blocking structure 5 is set to be not more than 1/2 of the height of the conductive bonding portion 3 before the reflow process. Meanwhile, the height of the blocking structure 5 cannot be too low, and if the height of the blocking structure 5 is too low, it is difficult to ensure that whether the blocking structure 5 can effectively block the resin material overflowing from the epoxy resin film 4 from entering the cavity area between the chip 2 and the substrate 1. The invention does not limit the specific setting value of the height of the blocking structural member 5, and can play a role in effectively blocking resin materials overflowing from the epoxy resin film 4 while ensuring that the functional surface of the chip 2 cannot be damaged by the upper surface of the blocking structural member 5 in the subsequent process.
Specifically, with continued reference to fig. 3, the blocking structure 5 is provided to include a blocking portion 51 and a draining portion 52, the blocking portion 51 is configured to block the epoxy film 4 in the step S3 from entering the cavity 6, and the draining portion 52 is configured to drain the epoxy film 4 in the step S3 in a direction away from the conductive bonding portion 3.
The blocking structure 5 is specifically of an L-shaped structure, the drainage part 52 is arranged on the upper surface of the substrate 1, the blocking part 51 protrudes towards the upper side of the substrate 1 along one end, close to the conductive joint part 3, of the drainage part 52, specifically, one side face, far away from the conductive joint part 3, of the drainage part 52 is aligned with the side face of the chip 2 to be pasted, the protruding height of the blocking part 51 meets the specific height setting requirement of the blocking structure 5, and other size settings of the blocking part 51 and the drainage part 52 are achieved. Of course, in this embodiment, in step S3, the epoxy resin film 4 covers one side surface of the barrier portion 51 away from the conductive bonding portion 3 and extends along the side surface to the upper surface of the drain portion 52 and the upper surface of the substrate 1.
Preferably, the blocking structure 5 is made of ink, so that the manufacturing cost is low. Of course, in other embodiments of the present invention, the material for forming the barrier structure 5 may also be copper or other high temperature resistant materials.
Further, before step S2, the method further includes the steps of: on the side of the barrier structure 5 away from the conductive bonding portion 3, a groove 12 is formed at a portion of the upper surface of the substrate 1.
As shown in fig. 4, specifically, the grooves 12 are formed in the partial region of the upper surface of the substrate on the side of the drainage portion 52 away from the conductive bonding portion 3 by using a laser or a mask, and in step S3, the epoxy resin film 4 is drained by the drainage portion 52 and can extend and fill the grooves 12, so that the bonding force between the epoxy resin film 4 and the substrate 1 is enhanced, and the product performance is improved. The shape and size of the groove 12 are specifically formed, but the invention is not limited thereto, and can be designed according to actual requirements.
Form a square or ring structure with recess 12 around blockking structure 5 to keep away from the medial surface of recess 12 with blockking structure 5 a side setting of electrically conductive joint 3 is in same vertical line, and the medial surface of recess 12 is in same vertical line with a side that electrically conductive joint 3 was kept away from to drainage portion 52 promptly, and is specific, with the medial surface of recess 12 and the side that electrically conductive joint 3 was kept away from to drainage portion 52 and treat that the side surface of pasting chip 2 aligns the setting, and epoxy membrane 4 directly extends to fill to inside the recess 12 through drainage portion 52 upper surface in step S3. The invention does not limit the specific shape structure and size formed by enclosing the groove 12, and only needs to ensure that the area enclosed by the blocking structural member 5 completely falls into the area enclosed by the groove 12.
In order to further enhance the bonding force between the epoxy resin film 4 and the substrate 1, the bottom of the groove 12 is made into a step structure, and the depth of the groove 12 is gradually increased towards the direction away from the blocking structure 5, however, in the present embodiment, no specific requirement is made on the number of steps of the formed step structure, and the larger the number of steps is, the larger the friction force between the epoxy resin film 4 and the inner surface of the groove 12 is, the larger the bonding force between the epoxy resin film 4 and the substrate 1 is, so that the number of steps of the step structure can be designed and adjusted according to actual requirements and processing precision. Of course, in other embodiments of the present invention, the bottom of the groove 12 may also be wavy or have other shapes, or the depth of the groove 12 gradually decreases in the direction away from the blocking structure 5, which may be specifically adjusted according to the actual manufacturing process and machining precision.
As shown in fig. 5, in order to correspond to the manufacturing process step in step S2, the functional surface of the chip 2 is provided with a corresponding conductive bonding portion 3, in this embodiment, the conductive bonding portion 3 is provided as a metal ball stud, which may be a solder ball, a gold ball eutectic solder, or the like. The specific setting height of the metal ball column is not limited, and can be adjusted according to different requirements of products or the subsequent requirement on the height of a cavity formed by manufacturing.
Furthermore, the functional surface of the chip 2 faces the upper surface of the substrate 1, and the conductive bonding portion 3 on the functional surface of the chip 2 is correspondingly soldered to the soldering area 11 on the upper surface of the substrate 1, so as to form an electrical connection with the substrate 1.
Further, after the chip 2 is mounted on the upper surface of the substrate 1, a reflow process is performed, and since the conductive bonding portion 3 is in a melting state in the reflow process, the height of the originally formed cavity 6 is reduced, and the distance between the upper surface of the barrier structure 5 and the lower surface of the chip 2 is reduced, as shown in fig. 6. In this embodiment, the height that will block structure 5 is no longer than 3 reflow soldering shaping preceding 1/2 settings of height of electrically conductive joint portion, so behind the reflow soldering technology, still there is certain space between the lower surface that blocks the upper surface of structure 5 and chip 2, when guaranteeing to block structure 5 and can not cause the injury to the functional surface of chip 2, can play the resin material that effectively blocks epoxy membrane 4 and spill over in the follow-up plastic envelope technology again and get into the medial surface that blocks structure 5 can.
As shown in fig. 7, corresponding to the manufacturing process step in step S4, the epoxy film 4 is pressed to cover the upper surface and the side surface of the chip 2 and the outer side surface of the barrier structure 5 and extends to the upper surface of the substrate 1 along the side surface of the chip 2 and the outer side surface of the barrier structure 5, and a cavity 6 is formed among the epoxy film 4, the chip 2, the substrate 1 and the barrier structure 5. Specifically, the epoxy resin film 4 is pressed to cover a side of the blocking portion 51 away from the conductive bonding portion 3, and extends to the upper surface of the drainage portion 52, the inside of the groove 12 and the upper surface of the substrate 1 along the side.
In other embodiments of the present invention, a DAF (Die Attachment Film) Film may be used instead of the epoxy Film 4, and the substrate 1 and the chip 2 can be fixed and combined to form the cavity 6, and the cavity is hardened after being baked at a high temperature, so that the package structure can be fixed and protected, and the structure of the final package product can effectively prevent resin materials overflowing from the epoxy Film 4 from entering the cavity area between the chip 2 and the substrate 1, and prevent the conductive bonding portion 3 and the functional surface area of the chip 2 from being contaminated.
In summary, according to the invention, the blocking structure is disposed on the partial area of the upper surface of the substrate outside the conductive bonding portion, and the blocking structure does not exceed the edge area of the chip, so that in the laminating process, the blocking structure can effectively prevent resin material overflowing from the epoxy resin film from entering the cavity area between the chip and the substrate, and prevent the conductive bonding portion and the cavity area from being contaminated. In addition, set up the recess inwards on base plate upper surface side for in epoxy plastic envelope membrane can extend and fill to the recess, reinforcing epoxy plastic envelope membrane and the cohesion between the base plate, reduce the risk that epoxy plastic envelope membrane drops, promote product property ability.
It should be understood that although the present description refers to embodiments, not every embodiment contains only a single technical solution, and such description is for clarity only, and those skilled in the art should make the description as a whole, and the technical solutions in the embodiments can also be combined appropriately to form other embodiments understood by those skilled in the art.
The above-listed detailed description is only a specific description of a possible embodiment of the present invention, and they are not intended to limit the scope of the present invention, and equivalent embodiments or modifications made without departing from the technical spirit of the present invention should be included in the scope of the present invention.
Claims (13)
1. A chip packaging structure comprises a substrate, at least one chip, a plurality of conductive bonding parts and an epoxy resin film, wherein a plurality of welding areas are arranged on the upper surface of the substrate, the chip is arranged above the substrate through the conductive bonding parts, and the conductive bonding parts are arranged corresponding to the welding areas;
the barrier structural part and the nearest conductive bonding part are arranged at intervals of at least 30 micrometers, and the height of the barrier structural part is not more than 1/2 of the height of the conductive bonding part before reflow soldering forming;
the epoxy resin film covers the upper surface and the side surface of the chip and the outer side surface of the barrier structure and extends to the upper surface of the substrate along the side surface of the chip and the outer side surface of the barrier structure, and a cavity is formed among the epoxy resin film, the chip, the substrate and the barrier structure.
2. The chip package structure according to claim 1, wherein the blocking structure surrounds an upper surface area of the substrate disposed outside the conductive bonding portion.
3. The chip package structure according to claim 2, wherein an inner side of the blocking structure does not exceed the chip edge region.
4. The chip package structure according to claim 1, wherein the blocking structure comprises a blocking portion and a draining portion, the blocking portion is configured to block the epoxy film from entering the cavity, and the draining portion is configured to drain the epoxy film away from the conductive bonding portion.
5. The chip package structure according to claim 4, wherein the blocking structure is an L-shaped structure, the current guiding portion is disposed on the upper surface of the substrate, and the blocking portion protrudes above the substrate along an end of the current guiding portion close to the conductive bonding portion.
6. The chip package structure according to claim 1, wherein a portion of the upper surface of the substrate is recessed to form a groove, and the groove is disposed on a side of the blocking structure away from the conductive bonding portion.
7. The chip package structure according to claim 6, wherein an inner side surface of the groove is disposed on a same vertical line with a side surface of the blocking structure far from the conductive bonding portion.
8. The chip package structure according to claim 7, wherein the recess surrounds the blocking structure.
9. The chip package structure according to claim 8, wherein the bottom of the recess is configured as a step structure, and the depth of the recess gradually increases in a direction away from the blocking structure.
10. A manufacturing method of a chip packaging structure is characterized by comprising the following steps:
providing a base plate, the base plate upper surface is provided with a plurality of welding zone, in the partial region department of base plate upper surface outside the welding zone is provided with and blocks the structure, specifically includes:
a blocking structure is arranged on the upper surface of the substrate around the outer side of the welding area;
arranging the blocking structure and the welding region closest to the blocking structure at intervals of at least 30 micrometers, wherein the inner side surface of the blocking structure is not beyond the edge region of the chip;
providing at least one chip, arranging the chip above the substrate corresponding to the welding area through a conductive bonding part, and arranging the height of the blocking structural part not more than 1/2 of the height of the conductive bonding part before reflow soldering molding;
providing an epoxy resin film, extruding the epoxy resin film to cover the upper surface and the side surface of the chip and the outer side surface of the barrier structure, and extending to the upper surface of the substrate along the side surface of the chip and the outer side surface of the barrier structure, wherein a cavity is formed among the epoxy resin film, the chip, the substrate and the barrier structure.
11. The method for manufacturing a chip package structure according to claim 10, wherein the providing a substrate, the substrate having a plurality of soldering regions on an upper surface thereof, and the blocking structure being disposed at a portion of the substrate on the upper surface outside the soldering regions, further comprises:
stop the structure and set up for L type structure, including stop part and drainage portion, will drainage portion set up in the base plate upper surface, will stop the part and follow drainage portion leans on the one end court of electrically conductive joint portion the protruding setting in base plate top.
12. The method for manufacturing a chip package according to claim 10, further comprising, before the providing at least one chip, the steps of:
and on one side of the blocking structural member far away from the conductive combination part, a groove is formed in the partial area of the upper surface of the substrate in an inward concave manner.
13. The method for manufacturing a chip package structure according to claim 12, wherein the blocking structure is recessed inward at a portion of the upper surface of the substrate on a side of the blocking structure away from the conductive bonding portion to form a groove, and specifically comprises:
arranging the groove around the blocking structural member, and arranging the inner side surface of the groove and one side surface of the blocking structural member far away from the conductive combination part on the same vertical line;
and forming the bottom of the groove into a step structure, wherein the depth of the groove is gradually increased towards the direction far away from the blocking structural part.
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| CN105977225B (en) * | 2016-07-04 | 2019-09-17 | 苏州晶方半导体科技股份有限公司 | Encapsulating structure and packaging method |
| US11211302B2 (en) * | 2019-10-17 | 2021-12-28 | Advanced Semiconductor Engineering, Inc. | Semiconductor device package |
| CN114824040B (en) * | 2022-07-01 | 2022-11-08 | 广东中科半导体微纳制造技术研究院 | Semiconductor package device |
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