CN115206808A - Tin plating method, semiconductor device packaging process and semiconductor device - Google Patents

Tin plating method, semiconductor device packaging process and semiconductor device Download PDF

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Publication number
CN115206808A
CN115206808A CN202210653330.5A CN202210653330A CN115206808A CN 115206808 A CN115206808 A CN 115206808A CN 202210653330 A CN202210653330 A CN 202210653330A CN 115206808 A CN115206808 A CN 115206808A
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plating
tin
layer
pin
chip
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赵丹
廖添政
濮虎
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JCET Group Co Ltd
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Jiangsu Changjiang Electronics Technology Co Ltd
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    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D3/00—Electroplating: Baths therefor
    • C25D3/02—Electroplating: Baths therefor from solutions
    • C25D3/30—Electroplating: Baths therefor from solutions of tin
    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D5/00—Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
    • C25D5/10—Electroplating with more than one layer of the same or of different metals
    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D5/00—Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
    • C25D5/34—Pretreatment of metallic surfaces to be electroplated
    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D7/00—Electroplating characterised by the article coated
    • C25D7/12—Semiconductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4871—Bases, plates or heatsinks
    • H01L21/4882—Assembly of heatsink parts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H01L23/3672—Foil-like cooling fins or heat sinks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H01L23/49548—Cross section geometry
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49568—Lead-frames or other flat leads specifically adapted to facilitate heat dissipation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Materials Engineering (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Electrochemistry (AREA)
  • Metallurgy (AREA)
  • Organic Chemistry (AREA)
  • Manufacturing & Machinery (AREA)
  • Geometry (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

The invention discloses a tinning method, a packaging process of a semiconductor device and the semiconductor device, wherein the tinning method comprises the following steps of: immersing a piece to be electroplated into an activating solution for activation, wherein a counter electrode is immersed in the activating solution, and the current applied to the counter electrode in the activation process is not less than 50A; and immersing the activated piece to be electroplated into the electroplating solution for electroplating to form a tin layer on the outer surface of the piece to be electroplated. In order to solve the peeling problem on the steel belt and the piece to be electroplated, the current on the counter electrode in the activating solution is increased to be not less than 50A in the activating process, so that the pre-electroplated lead frame can be fully activated in the activating solution, and the peeling of the steel belt and the electroplated product is avoided.

Description

Tin plating method, semiconductor device packaging process and semiconductor device
Technical Field
The invention relates to the technical field of semiconductor packaging, in particular to a tinning method for chip packaging, a packaging process of a semiconductor device and the semiconductor device.
Background
The PPF lead frame is also called a pre-plated lead frame, and an electroplated layer is formed outside the incoming lead frame in advance, so that the PPF lead frame can be used for various packaging type products, such as QFN/SOIC/QFP/SOT and the like. Since the incoming lead frame has been plated with a plating layer such as a Ni-Pd-Au plating layer, which provides the lead frame with solderability, the operation of plating the lead frame with tin is saved during the packaging process.
In order to realize the function diversification of products in the actual packaging process, such as the improvement of heat dissipation wattage, the convenience of wire bonding and the like, a riveting lead frame is generally adopted, the riveting lead frame fixes a heat dissipation sheet for fixing a chip on the lead frame in a riveting mode, the back surface of the heat dissipation sheet is exposed outwards for heat dissipation after plastic packaging, the heat dissipation sheet is used as a fixed supporting part of the chip and also used as the heat dissipation sheet of the chip to release the heat of the chip outwards, such as the structure of riveting the heat dissipation sheet on a PPF lead frame, and due to the technical bottleneck, the heat dissipation sheet is generally made of a copper material in the prior art.
Because the fin is the copper product and is not convenient for combine with the external world, in order to more convenient realization and external combination, generally can be at the back of fin tin-plating. If the back surface of the heat sink is plated with tin and then riveted with the PPF (Ni-Pd-Au) lead frame, the tin plated layer on the back surface of the heat sink is scratched in the riveting process due to mechanical combination of riveting, thereby affecting the reliability of the product. Therefore, it is generally selected to perform the soldering function of the heat sink by plating tin on the back surface of the heat sink after the plastic package is completed.
Because the heat radiating fin and the PPF (Ni-Pd-Au) lead frame are combined through riveting, a tin layer is plated on the exposed area of the PPF (Ni-Pd-Au) lead frame when the back surface of the heat radiating fin is tinned, and because the frame is the PPF (Ni-Pd-Au) lead frame, the resistivity is higher than that of a copper material, peeling can be generated to different degrees on the lead frame and a steel belt used for bearing the lead frame in the tinning process, the product quality is influenced, and meanwhile, the damage of the steel belt is also aggravated.
Disclosure of Invention
The invention aims to provide a tin plating method to solve the defects in the prior art, and the pre-plating lead frame can be fully activated in an activating solution by increasing the current on a counter electrode in the activating solution to be not less than 50A in the activating process, so that the peeling of a steel strip and a plated product is avoided.
The tin plating method provided by the embodiment of the invention comprises the following steps: immersing a piece to be electroplated into an activating solution for activation, wherein a counter electrode is immersed in the activating solution, and the current applied to the counter electrode in the activation process is not less than 50A;
and immersing the activated piece to be electroplated into the electroplating solution for electroplating to form a tin layer on the outer surface of the piece to be electroplated.
Furthermore, the outer surface of the piece to be electroplated is provided with a plating layer, and the tin layer is formed on the outer surface of the plating layer in an electroplating way.
Further, the plating layer is a Ni-Pd-Au plating layer.
Further, the current applied to the counter electrode during the activation process is not more than 60A.
Further, the method also comprises the step of pretreating the piece to be electroplated before activating the piece to be electroplated, wherein the pretreatment comprises a deoxidation process.
Furthermore, the method also comprises a neutralization process and a drying process after the tin coating is electroplated outside the coating of the piece to be electroplated.
The invention also discloses a packaging process of the semiconductor device, which comprises the following steps:
providing a lead frame, wherein the lead frame is a pre-plated lead frame with a plated layer on the outer surface, and the lead frame comprises a frame body and a plurality of pins arranged on the frame body;
providing a radiating fin and fixing the radiating fin on the frame body;
attaching a chip to the front surface of the radiating fin;
connecting the chip and the pins through leads;
forming a plastic package on the front surface and the side surface of the radiating fin, wherein the plastic package encapsulates the chip, the lead and the pin, and the pin is provided with an exposed section exposed outside the plastic package;
and electroplating the outer surface of the exposed section and the back surface of the heat sink to form a tin layer by adopting the tin plating method.
Further, the method further comprises the following steps of forming a tin layer on the outer surface of the exposed section and the back surface of the radiating fin through electroplating:
bending and molding the pin and cutting;
and baking the bent and cut pin and the tin layer on the radiating fin.
Further, the time point of baking the tin layer is not more than 72 hours apart from the time point of electroplating the formed tin layer.
Another embodiment of the present invention also discloses a semiconductor device, including: the heat radiating fin comprises a heat radiating fin, a chip attached to the front surface of the heat radiating fin, pins, a lead for connecting the pins and the chip and a plastic package;
the plastic package parts are arranged on the front surface and the side surface of the radiating fin and are used for packaging the chip and the lead;
the pin is provided with a packaging section packaged in the plastic packaging part and an exposed section exposed outside the plastic packaging part, and the lead is connected between the packaging section and the chip;
and tin layers are arranged on the outer surface of the exposed section and the back surface of the radiating fin, and are formed by electroplating by adopting the tin plating method.
Furthermore, the pin comprises a pin body and a plating layer formed on the outer surface of the pin body, and the tin layer is formed on the outer surface of the plating layer of the exposed section of the pin in an electroplating mode.
Further, the plating layer is a Ni-Pd-Au plating layer.
Compared with the prior art, in order to solve the peeling problem on the steel belt and the piece to be electroplated, the current on the counter electrode in the activating solution is increased to be not less than 50A in the activating process, so that the pre-electroplated lead frame can be fully activated in the activating solution, and the peeling of the steel belt and the electroplated product is avoided.
Drawings
FIG. 1 is a schematic flow diagram of a tin plating process disclosed in an embodiment of the invention;
fig. 2 is a schematic flow chart of a packaging process of a semiconductor device according to an embodiment of the present invention;
fig. 3 is a schematic structural diagram of a semiconductor device according to an embodiment of the present invention;
FIG. 4 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present invention after electroplating tin on the leads;
fig. 5 is a diagram illustrating a trend of metal potential movement in a packaging process of a semiconductor device according to an embodiment of the present invention;
fig. 6 is a schematic structural diagram of an IMC layer formed on a metal bonding surface in a packaging process of a semiconductor device according to an embodiment of the present invention;
description of the reference numerals: 1-radiating fin, 2-chip, 3-pin, 31-pin body, 32-plating layer, 4-lead, 5-plastic package and 6-tin layer.
Detailed Description
The embodiments described below with reference to the drawings are illustrative only and should not be construed as limiting the invention.
The embodiment of the invention comprises the following steps: discloses a tin plating method which is mainly used in the field of chip packaging. The riveting lead frame generally comprises a frame body and a radiating fin riveted on the frame body, the radiating fin is used for fixedly supporting a chip, a pin is arranged on the frame body, the radiating fin is riveted on the frame body, the chip is attached to the radiating fin, the pin and the chip are connected through lead bonding after the chip is attached, and finally the chip and the pin are packaged through a plastic package piece. The back of the radiating fin is exposed outwards during plastic packaging, and the chip can be radiated.
In the specific packaging process, the lead frame is generally a PPF lead frame, that is, a pre-plated lead frame, the pre-plated lead frame is formed by a plating layer outside the frame body in advance, so that the lead frame does not need to be plated in the packaging process, and products using the PPF lead frame are definitely defined by packaging factories to prohibit plating, and in the embodiment, the plating layer of the pre-plated lead frame is an Ni-Pd-Au plating layer.
Due to the technical bottleneck, the material of the radiating fin before riveting can only be copper material, and in order to realize the function diversification of the product in the packaging process, if the radiating fin is required to be welded with other parts, such as the improvement of radiating wattage, the convenience of welding wires and the like, the welding function of the radiating fin is generally realized by plating tin on the back surface of the radiating fin after plastic packaging is finished due to the poor solderability of the copper material. In the actual use process, the PPF lead frame and the steel strip used for positioning the PPF lead frame are skinned to different degrees, so that the product quality is influenced, and the service life of the steel strip is shortened.
In order to solve the above problems, the present embodiment discloses a tin plating method, as shown in fig. 1, including the following steps:
immersing a piece to be electroplated into an activating solution for activation, wherein a counter electrode is immersed in the activating solution, and the current applied to the counter electrode in the activation process is not less than 50A;
it can be understood that the activating solution is placed in the activating groove, and the piece to be electroplated is brought to the position of the activating groove by the steel strip and is immersed into the activating solution for activation; the specific type of the activating solution can adopt the existing conventional activating solution, such as electronic-grade methanesulfonic acid SYT810; the counter electrode in the activation tank comprises a positive electrode and a negative electrode which are oppositely arranged, and is immersed in the activation solution in advance and then current is applied to the counter electrode to carry out electrolytic activation;
immersing the activated to-be-electroplated member into electroplating solution for electroplating to form a tin layer on the outer surface of the to-be-electroplated member;
after activation in the activation tank, moving the to-be-plated part to a plating tank along with the steel strip and immersing the to-be-plated part into a plating solution for plating, wherein the plating solution is a solution containing tin, and the specific type can adopt the existing solution, such as a solution containing electronic grade methanesulfonic acid SYT810, electronic grade methanesulfonic acid tin SYT820 and an additive;
the electroplating bath is also internally provided with a counter electrode for electroplating, current is applied to the counter electrode, the process steps and parameters used in the electroplating process are all the conventional technology, and the part is not improved in the application, so that the details are not repeated.
In the embodiment, the electroplating is carried out on the back surface of the heat sink, but because partial pins are required to be exposed after the chip is packaged, the exposed pins are also electroplated together, and the outer surfaces of the exposed pins are also provided with the plating layer because the exposed pins are part of the pre-electroplated lead frame, so that the parts to be electroplated comprise the copper heat sink and the pins containing the Ni-Pd-Au plating layer when the back surface of the heat sink is electroplated.
In the prior art, a part to be electroplated is generally made of copper, and as shown in the following table 1, the resistivity of copper is relatively low; however, in the embodiment, the part to be electroplated includes a pin with a plating layer on the outer surface, and the tin layer is electroplated on the outer surface of the plating layer, wherein the plating layer is a Ni-Pd-Au plating layer. Due to the pins including the Ni-Pd-Au plating layer, as shown in table 1 below, the resistivity of Ni and Pd was higher compared to that of copper. The total energy = heat energy + reduction energy used in the electroplating process, if the total energy and the current are not changed, the heat energy = I 2 When the resistivity becomes high, the thermal energy increases accordingly, and the reduction energy decreases accordingly.
When the piece to be electroplated is pre-soaked and activated in the activation solution, the steel belt and the piece to be electroplated are in a series connection mode, the piece to be electroplated is changed from copper material to copper plus nickel-palladium-gold, so that the energy consumption in the electroplating process is increased, the chemical energy is reduced, the amount of reduced hydrogen is less, the full and complete activation on the piece to be electroplated can not be realized, and the problem of peeling on the steel belt and the electroplated product is easy to occur after electroplating.
In order to solve the peeling problem on the steel strip and the to-be-electroplated member, the current on the counter electrode in the activation solution is increased to be not less than 50A, so that the pre-electroplated lead frame can be fully activated in the activation solution, and the peeling of the steel strip and the electroplated product is avoided. The pre-plated lead frame can effectively enhance the bonding force with the lead and improve the reliability of the product.
In addition, this embodiment makes the cladding material fully activate through control activation current, can be at the outer tin coating of cladding material after the activation, broken the common knowledge that the use is electroplated lead frame product in advance can not tin-plating, when tin-plating to the fin back of the product after the encapsulation, reduced the influence of the tin coating of electroplating formation outside the pin to the pin, make the fin of copper have easy weldability, satisfied the demand of customer to high-power base station construction product under the prerequisite of guaranteeing the product quality.
Table 1: resistivity meter for metal
Figure BDA0003686746460000061
Preferably, the current applied to the counter electrode during activation is no greater than 60A. Higher current can be used, but the current exceeding 60A has corresponding influence on other steps of the process, and corresponding adjustment is needed in other steps, and the embodiment controls the current of the activation stage to be 50-60A, so that the problem of peeling on the steel strip and the product can be solved under the condition of having minimal influence on the process steps.
It is understood that before the item to be plated is immersed in the activation solution for activation, S100 is also included: pretreating a piece to be electroplated;
the specific pretreatment comprises an oil removing process and a deoxidation process, wherein the oil removing process adopts an electrolytic oil removing mode, and oil stains on the surface of the piece to be electroplated are removed under the action of electrolytic deoiling liquid in an electrolytic deoiling tank. The deoxidation process is performed under the action of the chemical deoxidation powder in the deoxidation tank, it should be noted that the pretreatment steps are all prior art, and this part is not improved in the present application, and therefore, no further description is given here.
Also, it is understood that the neutralization process and the baking process are included after the tin plating of the plated article.
The neutralization process is to neutralize the solution used in the previous processes, because the activating solution and the plating solution have certain acidity, and therefore, the neutralization process in this embodiment can be performed by using an alkaline solution.
The drying process is to dry the solution on the surface of the product after the neutralization process.
In the prior art, after a tin layer is formed by electroplating, the tin layer needs to be baked, and after baking, the pin is bent, formed and cut; the pins are cut from the frame body to form individual semiconductor devices. The pin is easy to crack and the weldability of the pin is seriously influenced when the existing scheme is adopted in the process of bending, forming and cutting.
As shown in fig. 2, to solve the problem of pin cracking, another embodiment of the present invention further discloses a packaging process of a semiconductor device, which includes the following steps:
s100 incoming material assembly: providing a lead frame, wherein the lead frame is a pre-plated lead frame with a plated layer on the outer surface, and the lead frame comprises a frame body and a plurality of pins arranged on the frame body; providing a radiating fin and fixing the radiating fin on the frame body;
in the embodiment, the lead frame is a pre-plated lead frame, and a Ni-Pd-Au plating layer is formed outside the whole lead frame in advance, wherein the thickness of Au is 0.003-0.015 mu m; the thickness of Pd is 0.02-0.15 μm; the thickness of Ni is 0.508-2.032 μm;
the radiating fin is fixed on the frame body in a riveting mode, wherein the frame body is provided with a riveting hole, the radiating fin is provided with a riveting column matched with the riveting hole, the riveting column and the riveting hole are connected together in a riveting and pressing mode, and a nut shape is formed above the riveting column under the action of pressure to enable the frame body and the radiating fin to be tightly riveted;
s200, pasting a piece: attaching a chip to the front surface of the radiating fin; specifically, the chip cut by grinding is fixed on the radiating fin through a chip mounting machine table and an oven, so that the chip and the radiating fin are firmly and physically connected; mounting glue is arranged between the chip and the radiating fin, and the chip and the radiating fin are connected together through the glue with a certain thickness;
s300, wire bonding: connecting the chip and the pins through leads; the lead wire can be an aluminum wire, one end of the aluminum wire is welded on the pin, and the other end of the aluminum wire is welded on the pin of the chip; the aluminum wire can be better combined with the pre-plated lead frame, so that the reliability of the product is improved;
s400, plastic packaging: forming a plastic package part on the front surface and the side surface of the radiating fin, wherein the plastic package part encapsulates the chip, the lead and the pin, and the pin is provided with an exposed section exposed outside the plastic package part;
s500, electroplating: electroplating the outer surface of the exposed section and the back surface of the radiating fin by adopting the tin plating method to form a tin layer; the tinned radiating fin has weldability, meets the requirement of an upper plate of a product, and meets the requirement of the thickness of a tinned layer: 5-20 μm; because the lead frame is a pre-electroplated lead frame, the pin generally comprises a pin body and a plating layer arranged outside the pin body, the plating layer is a Ni-Pd-Au metal layer, and a tin layer is formed outside the plating layer in an electroplating way;
s600, forming: bending and molding the pin and cutting; bending the pin into a certain angle, and cutting the pin from the lead frame to complete the forming;
s700, baking: and baking the bent and cut pin and the tin layer on the radiating fin to release the stress of the tin layer.
Compare in prior art and toast earlier the shaping again after electroplating, the shaping is toasted again earlier in this embodiment, accomplishes the shaping flow earlier after electroplating, toasts again after releasing mechanical stress, can effectual reduction pin receives stress to influence the risk that the fracture appears.
In the embodiment, since tin is plated on the pre-lead frame, the plated pin includes a Ni-Pd-Au plating layer and a tin layer as shown in fig. 4, if a process of baking first and then forming is adopted in the prior art, the migration of Sn will occur after baking (annealing) to make the IMC layer brittle, and the Ni-Pd-Au-Sn plating layer on the pin is likely to crack and peel due to the influence of stress in the forming process of the post-process, thereby affecting the solderability.
It was found that baking accelerated tin migration to the Ni-Pd-Au layer, exacerbating IMC layer embrittlement. Since the potential of Pd is positive and has a specific value of 0.83V, the potentials of Sn and Ni are both negative, wherein the potential of Ni is-0.25V and the potential of Sn is-0.136V, and as shown in FIG. 5, pd is located between Sn and Ni, sn and Ni will move and diffuse to Pd.
The purpose of baking after electroplating is to release the stress of the tin layer, but because the plating layer of the lead frame is a plurality of metal layers of Ni-Pd-Au-Sn, the movement and diffusion of Sn and Ni to Pd are aggravated by the heating of the electroplating baking, a thicker IMC layer can be formed after atoms move as shown in figure 6, and the IMC has poor mechanical property, and is easy to crack due to the deformation of external force in the punching forming process.
The shaping is earlier baked again in this embodiment, accomplishes the shaping flow earlier after electroplating, toasts again after releasing mechanical stress, has avoided the bodiness on IMC layer that Sn, ni that cause among the baking process caused to Pd's removal diffusion, makes the mechanicalness of pin better, has reduced the risk that the fracture appears in the pin receiving stress influence in the forming process.
Further, the time point of baking the tin layer is not more than 72 hours apart from the time point of plating the tin layer. In order to avoid the occurrence of tin whisker problems after the electroplating molding, the baking needs to be completed within a certain time, and if the predetermined time is exceeded, the tin whisker problems occur, so that the quality is influenced.
As shown in fig. 3, another embodiment of the present invention further discloses a semiconductor device, including: the heat sink comprises a heat sink 1, a chip 2 attached to the front surface of the heat sink 1, pins 3, leads 4 for connecting the pins 3 and the chip 2, and a plastic package 5;
the plastic package 5 is arranged on the front surface and the side surface of the heat sink 1 and encapsulates the chip 2 and the lead 4;
the pin 3 is provided with a packaging section packaged in the plastic packaging part 5 and an exposed section exposed outside the plastic packaging part, and the lead 4 is connected between the packaging section and the chip 2; the pin 3 comprises a pin body 31 and a plating layer 32 formed on the outer surface of the pin body 31, wherein the plating layer 32 is a Ni-Pd-Au metal layer;
the semiconductor device also has a tin layer 6 arranged on the outer surface of the exposed section and the back surface of the heat sink 1, and the tin layer 6 is formed on the outer surface of the plating layer 32 by electroplating using the tin plating method.
The construction, features and functions of the present invention are described in detail in the embodiments illustrated in the drawings, which are only preferred embodiments of the present invention, but the present invention is not limited by the drawings, and all equivalent embodiments modified or changed according to the idea of the present invention should fall within the protection scope of the present invention without departing from the spirit of the present invention covered by the description and the drawings.

Claims (12)

1. A tin plating method is characterized by comprising the following steps:
immersing a piece to be electroplated into an activating solution for activation, wherein a counter electrode is immersed in the activating solution, and the current applied to the counter electrode in the activation process is not less than 50A;
and immersing the activated piece to be electroplated into the electroplating solution for electroplating to form a tin layer on the outer surface of the piece to be electroplated.
2. The method of plating tin according to claim 1, wherein the member to be plated has a plating layer on an outer surface thereof, and the tin layer is formed by plating on the outer surface of the plating layer.
3. The method of plating tin according to claim 2, wherein the plating layer is a Ni-Pd-Au plating layer.
4. The method of tin plating according to claim 1, characterized in that the current applied to the counter electrode during activation is not more than 60A.
5. The method of plating tin according to claim 1, further comprising a pretreatment of the article to be plated before activating the article to be plated, the pretreatment including a deoxidation process.
6. The method of plating tin according to claim 1, further comprising a neutralization process and a baking process after plating the tin layer outside the plating layer of the article to be plated.
7. A packaging process of a semiconductor device is characterized by comprising the following steps:
providing a lead frame, wherein the lead frame is a pre-plated lead frame with a plated layer on the outer surface, and the lead frame comprises a frame body and a plurality of pins arranged on the frame body;
providing a radiating fin and fixing the radiating fin on the frame body;
attaching a chip to the front surface of the radiating fin;
connecting the chip and the pins through leads;
forming a plastic package part on the front surface and the side surface of the radiating fin, wherein the plastic package part encapsulates the chip, the lead and the pin, and the pin is provided with an exposed section exposed outside the plastic package part;
electroplating the outer surface of the exposed section and the back surface of the heat sink with the tin plating method according to any one of claims 1 to 6 to form a tin layer.
8. The process of packaging a semiconductor device according to claim 7, further comprising, after the step of electroplating a tin layer on the outer surface of the exposed section and the back surface of the heat sink:
bending and molding the pin and cutting;
and baking the bent and cut pin and the tin layer on the radiating fin.
9. The process of claim 8, wherein the time point at which the tin layer is baked is spaced from the time point at which the tin layer is electroformed by no more than 72 hours.
10. A semiconductor device, comprising: a heat sink, a chip attached to the front surface of the heat sink, pins, leads for connecting the pins and the chip, and a plastic package,
the plastic package parts are arranged on the front surface and the side surface of the radiating fin and are used for packaging the chip and the lead;
the pin is provided with a packaging section packaged in the plastic packaging part and an exposed section exposed outside the plastic packaging part, and the lead is connected between the packaging section and the chip;
the outer surface of the exposed section and the back surface of the heat sink are provided with tin layers which are formed by electroplating using the tin plating method according to any one of claims 1 to 6.
11. The semiconductor device of claim 10, wherein said pin includes a pin body and a plating formed on an outer surface of said pin body, said tin layer being formed by electroplating on an outer surface of said plating of said exposed portion of said pin.
12. A semiconductor device according to claim 11, wherein the plating layer is a Ni-Pd-Au plating layer.
CN202210653330.5A 2022-06-09 2022-06-09 Tin plating method, semiconductor device packaging process and semiconductor device Pending CN115206808A (en)

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CN202210653330.5A CN115206808A (en) 2022-06-09 2022-06-09 Tin plating method, semiconductor device packaging process and semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202210653330.5A CN115206808A (en) 2022-06-09 2022-06-09 Tin plating method, semiconductor device packaging process and semiconductor device

Publications (1)

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