CN115190258A - Serial image data training method for time sequence reset of each row with low resource occupancy rate - Google Patents

Abstract

The invention discloses a serial image data training method for time sequence reset of each line with low resource occupancy rate, which relates to a training method of a CMOS image sensor and solves the problems that the existing image data training method carries out data training in a power-on stage, and the training operation is allowed to be completed in a long time, the requirement of carrying out word correction in a short time in an image blanking stage of each line is not met, the output parallel data combination sequence is fixed and unchanged, and the like. Compared with the traditional training method, the training time can be greatly reduced, and the requirement of short blanking period and high line frequency application is met. The training method is suitable for application in severe space environments. The invention ensures that the image data received after each row of time sequence reset is well trained.

Description

Serial image data training method for time sequence reset of each row with low resource occupancy rate

Technical Field

The invention relates to a training method of a CMOS image sensor, in particular to a serial image data training method applied to a severe space environment and in a low-resource-occupancy rate and in a time sequence reset state of each row.

Background

When the CMOS detector is applied to an in-orbit application, particularly to the application of a severe space environment, high-energy particles are easy to overturn the internal logic of the detector, so that time sequence errors occur easily. The timing reset is performed every line, and since the phase of the timing reset signal may be different with the temperature change from that at the beginning of training, the transmission start position of the output serial image data may be changed, and thus word correction and channel processing are required for each line of serial data output by the detector.

The prior granted patent, patent number 202110427323.9, patent name: a training method of high-frequency and low-frequency serial image data is disclosed in patent No. 202010447392.1, with the patent names: a method for improving and training CMOS image data based on alternating conversion pulse is characterized in that multiple groups of parallel image data are combined to generate correct parallel data, but the method is in a power-on stage, and training is not performed after a photosensitive image is output after the power-on stage is started. The data valid signals are generated according to the delay of the timing driving signals; furthermore, the training operation is allowed to be completed in a longer time, and does not satisfy the requirement of performing word correction in a short time during the image blanking period of each line.

There are issued patents, patent number 202110427711.7, with the patent names: in the patent, a training system comprises five stages, namely an idle stage, a bit correction stage based on an accompanying clock, a word correction stage based on the accompanying clock, a channel correction stage based on a sync word sync _ code and a writing stage of a training result. Also for the power-on phase, training based on the sync _ code allows the training operation to be completed in a longer time and does not meet the need for word correction and dynamic correction in a very short time (no more than 3 pixel clock lengths) during the image blanking phase of each line. In addition, the combination order of outputting the parallel data is constant and thus does not change with the detection of each line.

Disclosure of Invention

The invention provides a serial image data training method with low resource occupancy rate for resetting a time sequence of each line, aiming at solving the problems that the existing image data training method carries out data training in a power-on stage, training operation is allowed to be completed in a long time, the requirement of carrying out word correction in a short time in an image blanking stage of each line is not met, the output parallel data combination sequence is fixed and the like.

The serial image data training method of time sequence reset of each row with low resource occupancy rate is realized by the following processes: a timing reset signal clk _ rst _ n output by the imaging controller generates a low-level reset pulse in a power-on reset stage; in the training phase, the constant high level is set; in the image pickup stage of the output time sequence, a low-level reset pulse repeatedly appears once in each b spectrum time sequence, and the low-level reset pulse is generated before the positive pulse of the line synchronization signal sync _ b of each b spectrum;

a word correction is needed in each line period of the b spectrum; each word correction is started by using a line synchronization signal sync _ b signal of a b spectrum; the p-spectrum data effective signal and the b-spectrum data effective signal are generated after four synchronous words are detected;

the training of the detector comprises two stages, namely a training stage after power-on reset and a training stage corresponding to a shooting stage of an output time sequence;

the training phase after power-on reset comprises a bit correction phase, wherein the bit correction needs a plurality of pixel clock cycles;

outputting a training stage corresponding to a shooting stage of a time sequence, wherein the duration time is less than or equal to three pixel clock cycles, and the training stage is realized by the combination selection of parallel data with different delays;

the combination mode of outputting the parallel data is as follows: according to the parallel data combination output by the low bit LSB or the high bit MSB;

for the data with the low bit LSB in front, the currently received data is at the highest bit of a single word p bit, the lowest bit data of the original parallel data is shifted out from the parallel data, and the rest bits in the original parallel data move to the right; the update period is 1 pixel clock period;

for the most significant bit MSB before, the currently received data is at the least significant bit of a single word p bit, and the most significant bit of the original parallel data is shifted out of the parallel data; the rest bits in the original parallel data are moved to the left; the update period is 1 pixel clock period;

when LSB is in front, the detected four-word parallel data r-1:r-4p is sync _ code1& sync _ code2& sync _ code3& sync _ code4, then the output parallel data is r + p-1: r; the r is the digit of the parallel data, and the value is less than or equal to 6p; sync _ code1, sync _ code2, sync _ code3 and sync _ code4 are four sync words, and the & symbol is parallel;

when the upper MSB is ahead, detected four-word parallel data r-4p is sync _ code4& sync _ code3& sync _ code2& sync _ code1, then the output parallel data is r-5p: r-4p-1.

The invention has the beneficial effects that:

1. after the time sequence of each row is reset, the channel correction position change caused by factors such as temperature drift is within the range of 1 pixel position, so that the combined judgment of the synchronous words is only needed to be carried out at three positions including the original correct channel correction position and the front and rear positions, the judgment of all time periods is not needed, and the condition that the initial position of the effective data of the row is wrong due to the fact that the gray value of the adjacent pixel in the photosensitive image is exactly the same as the combination of the synchronous words and the wrong effective data signal indication occurs can be avoided.

2. In the image pickup stage, the effect of comparing a plurality of counting positions can be achieved by only parallelly judging the combination of a plurality of types of synchronous words at three counting positions and using parallel comparison of a plurality of types of delay data. Compared with the traditional training method, the training time can be greatly reduced, and the requirement of short blanking period and high line frequency application is met.

3. In the power-on training stage, only bit correction is carried out, and word correction and control correction are not carried out, so that control resources required by the traditional word correction and channel can be greatly reduced, and the resource occupancy rate is reduced.

Drawings

FIG. 1 is a schematic block diagram of a low resource occupancy serial image data per row time sequence reset training system according to the present invention;

FIG. 2 is a schematic diagram of a topology of a conventional training method;

FIG. 3 is a schematic diagram of the topology of the new training method;

FIG. 4 is a diagram of a combination of output parallel data when one word is 12;

fig. 5 is a diagram of a parallel data arrangement with the LSB (least significant bit) preceding;

fig. 6 is a diagram of parallel data arrangement with MSB (most significant bit) preceding.

Detailed Description

Fig. 3 to fig. 6 illustrate the serial image data training method for time sequence reset per line with low resource occupancy of the present embodiment, which is implemented by the time sequence per line imaging system shown in fig. 1, and includes an imaging detector, a driving and controlling circuit, an imaging controller, a memory and a data transmission interface circuit; the driving and control signals generated by the imaging controller are sent to the imaging detector after passing through the driving and control circuit; the generated time sequence reset signal carries out time sequence reset on the detector in each row. The digital image data output by the imaging detector is processed by the imaging controller and then output by the data transmission interface circuit. Under the shooting state, each line of the imaging detector firstly outputs four synchronous words sync _ code and then outputs photosensitive image data; the four synchronous words are different, the highest of the first synchronous word is 1, and the rest are 0; in the second synchronous word, the lowest bit is 0, and the rest are 1; the third sync word is the inverse of the training word (e.g., 98EH for 12bit application selection) and the fourth sync word is the inverse of the lowest of the training words.

In the present embodiment, the low-level pulse of the timing reset signal clk _ rst _ n precedes the positive pulse of the line synchronization signal sync _ b in the b spectrum (multispectral spectral band).

As shown in table 1, the timing reset signal clk _ rst _ n, in the power-on reset phase, appears only once as a low-level reset pulse; in the training phase, the constant high level is set; in the image pickup phase of the output timing, a low-level reset pulse that precedes the positive pulse of sync _ b of each b spectrum repeatedly appears once per b spectrum timing.

Therefore, one word correction is needed in each line period of the b spectrum; each word correction is initiated using the sync _ b signal of the b spectrum; the p-spectrum (panchromatic spectral band) and b-spectrum data valid signals are generated not according to the line synchronization signals sync _ p and sync _ b of the p-spectrum and b-spectrum, but after four synchronization words sync _ code are detected (the four synchronization words are different, the highest in the first synchronization word is 1, the rest are 0, the lowest in the second synchronization word is 0, the rest are 1, the third synchronization word is the negation of the training word, and the fourth synchronization word is the negation of the lowest in the training word).

TABLE 1 states of timing reset signals at different stages

In this embodiment, the training of the detector includes two stages, a training stage after power-on reset and a training stage corresponding to a camera stage of an output timing sequence; the operation of the training stage after power-on reset is different from that of the traditional training method, and only comprises a bit correction stage, wherein the bit correction is realized by a plurality of clock cycles; and the training stage corresponding to the shooting stage of the output time sequence has the duration not exceeding three pixel clock cycles and is realized by the combination selection of the parallel data with different delays.

The combination mode of outputting the parallel data is as follows: parallel data combination which is output according to the fact that the LSB or the MSB is in the front;

for the data with the LSB being in front and the low bit being in front, the currently received data is at the highest bit of a single word p bit; moving the parallel data to the right; the update period should be 1 pixel clock period (1 word for the number of high speed serial clocks);

when LSB is prior, the detected four-word parallel data (r-1:r-4 p) is sync _ code1& sync _ code2& sync _ code3& sync _ code4, and the output parallel data is (r + p-1:r); in the formula, r is the digit of the parallel data, and the value is less than or equal to 6p.

For MSB first, high order first, currently received data is at the lowest order of 12 bits of a single word; moving the parallel data to the left; the update period should be 1 pixel clock period (1 word for the number of high speed serial clocks);

when the MSB is ahead, the detected four-word parallel data (r-4 p.

As shown in fig. 2, in order to realize word correction and channel correction of serial image data with low resource occupancy, 6-stage delays D1 to D6 for outputting parallel data and a check MUX1 are added on the basis of using a conventional delayer IODELY, a double edge sampler IDDR, a check MUX, a shift register shifer, and a cross clock domain RAM, and finally parallel data Train parallel data is output. The bit correction adopts a traditional training method, and IODELY and a check device MUX are required to be controlled; in the word correction and channel correction stages, variable parameter control is not performed on shifer and the clock domain crossing RAM, and only the check device MUX1 is controlled. The detection of the parallel data is performed only within three pixel clocks, the positions of which are generated by the delay of sync _ b. The control signals of the IODELY comprise a reset signal rst, a delay enable signal ce and a delay increase and decrease indication signal inc; under the control of a selection signal Iddr control, the MUX selects and outputs a signal sampled from a rising edge or a falling edge; shifer is controlled by a word correction control signal bitslip, and the combination sequence of the output parallel image data is changed; the RAM is controlled by a channel correction control signal chan _ shift _ inc, which changes the relative delay relationship of input and output parallel data.

As shown in fig. 3, the training phase corresponding to the image capturing phase of the output timing sequence performs correction of the word and channel as a whole, and is completed in one pixel clock; the final output is a combination of three parallel data of E, F and G by finding a combination of four words (four sync word combinations M1M2M3M4 in the figure, four sync words of 48 bits in the figure, and four sync words of 4pbit in the figure) in six words (A, B, C, D, E and F in the figure, corresponding to 72 bits in the figure, and 6pbit in the figure, when each word is p in width).

The combination form changes in real time according to the detection result in the training stage after power-on reset and the training stage corresponding to the shooting stage of the output time sequence. The starting position of the output valid data also changes according to the detection result of each training. If 70down 23 is detected as a combination of four sync words M1M2M3M4, the output parallel data Dataout is 22down 11.DOWNto means from high to low.

In this embodiment, the imaging detector uses a TDICMOS detector from long optical core corporation; the data transmission interface circuit adopts a TLK2711 chip; the driving and control circuit is mainly based on a level conversion chip 164245; the imaging controller mainly adopts an FPGA and a refreshing chip of Shanghai double-denier microelectronics corporation.

Claims (6)

1. The serial image data training method for time sequence reset of each row with low resource occupancy rate is characterized by comprising the following steps: a timing reset signal clk _ rst _ n output by the imaging controller generates a low-level reset pulse in a power-on reset stage; in the training phase, the constant high level is set; in the image pickup stage of the output time sequence, a low-level reset pulse repeatedly appears once in each b spectrum time sequence, and the low-level reset pulse is generated before the positive pulse of the line synchronization signal sync _ b of each b spectrum;

a word correction is needed to be carried out in the line period of each b spectrum; each word correction is started by using a line synchronization signal sync _ b signal of a b spectrum; the p-spectrum data effective signal and the b-spectrum data effective signal are generated after four synchronous words are detected;

the training of the detector comprises two stages, namely a training stage after power-on reset and a training stage corresponding to a shooting stage of an output time sequence;

the training phase after power-on reset comprises a bit correction phase which is realized by a plurality of pixel clock cycles;

and outputting a training stage corresponding to the shooting stage of the time sequence, wherein the duration time is less than or equal to three pixel clock cycles, and the training stage is realized by the combination selection of parallel data with different delays.

2. The serial image data training method for time sequence reset of each row with low resource occupancy rate as claimed in claim 1, characterized in that: the combination mode of outputting the parallel data is as follows: parallel data combination which is output in advance according to the low-order LSB or the high-order MSB;

for the most significant bit of a single word p bit of currently received data with the low bit LSB being in front, the updating period is 1 pixel clock period; the detected four-word parallel data r-1:r-4p is sync _ code1& sync _ code2& sync _ code3& sync _ code4, and the output parallel data is r + p-1: r; the r is the digit of the parallel data, and the value is less than or equal to 6p; sync _ code1, sync _ code2, sync _ code3 and sync _ code4 are four sync words, and the & symbol is parallel;

for the most significant bit MSB, the updating period is 1 pixel clock period when the currently received data is at the least significant bit of a single word p bit; if the detected four-word parallel data r-4p is sync _ code4& sync _ code3& sync _ code2& sync _ code1, the output parallel data is r-5p: r-4p-1.

3. The serial image data training method for time sequence reset of each row with low resource occupancy rate as claimed in claim 1, characterized in that: the four synchronous words are different, the highest of the first synchronous word is 1, and the rest are 0; the lowest bit of the second sync word is 0, and the rest are 1; the third synchronous character is the negation of the training character, and the fourth synchronous character is the negation of the lowest position of the training character.

4. The serial image data training method for time sequence reset of each row with low resource occupancy rate as claimed in claim 1, characterized in that: the combination form of the parallel data is set to be a constant central position in a training stage after power-on reset, and the combination form of the data changes in real time according to a detection result in a training stage corresponding to a shooting stage of an output time sequence.

5. The serial image data training method for time sequence reset of each row with low resource occupancy rate as claimed in claim 1, characterized in that: the method is realized by an imaging system, wherein the imaging system comprises an imaging detector, a driving and control circuit, an imaging controller, a memory and a data transmission interface circuit; the driving and control signals generated by the imaging controller are sent to the imaging detector after passing through the driving and control circuit; the generated time sequence reset signal carries out time sequence reset on the detector in each row; and digital image data output by the imaging detector is processed by the imaging controller and then output by the data transmission interface circuit.

6. The serial image data training method for time sequence reset of each row with low resource occupancy rate as claimed in claim 1, characterized in that: the imaging controller further includes D flip-flops D1-D6 outputting 6-stage delays of parallel data and a check MUX1; during the word correction and channel correction phases, the check device MUX1 is controlled.

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