CN115189219A - Method for obtaining optimal aging condition of edge-emitting laser chip and method for screening chip by adopting condition - Google Patents
Method for obtaining optimal aging condition of edge-emitting laser chip and method for screening chip by adopting condition Download PDFInfo
- Publication number
- CN115189219A CN115189219A CN202210908119.3A CN202210908119A CN115189219A CN 115189219 A CN115189219 A CN 115189219A CN 202210908119 A CN202210908119 A CN 202210908119A CN 115189219 A CN115189219 A CN 115189219A
- Authority
- CN
- China
- Prior art keywords
- aging
- driving current
- chip
- condition
- optimal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
- H01S5/00—Semiconductor lasers
- H01S5/0014—Measuring characteristics or properties thereof
- H01S5/0021—Degradation or life time measurements
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Electromagnetism (AREA)
- Optics & Photonics (AREA)
- Testing Of Individual Semiconductor Devices (AREA)
- Semiconductor Lasers (AREA)
Abstract
The invention provides a method for obtaining an optimal aging condition of a side-emitting laser chip and a method for screening the chip by adopting the condition, which are used for solving the problem that the driving current under the maximum power obtained by a method for testing a PI curve through points is different from the driving current under the actual aging maximum power. The method comprises the following steps: testing the corresponding saturation current Io at different aging temperatures I by using the chip set I; combining the driving current I, the aging temperature II and the aging time into an aging condition matrix, and counting the aging failure rate of each group of chips; performing an Htol test on the aged chip set II, and counting Htol failure rate after the test is finished; and comparing the aging failure rate of the chip set II with the Htol failure rate of 0, wherein the aging condition corresponding to the chip set II with the highest aging failure rate is the optimal aging condition of the chip. According to the scheme, the selection of the saturation current Io is more accurate, the verification in the current range is more comprehensive, and the finally obtained aging condition is more applicable.
Description
Technical Field
The invention belongs to the technical field of aging screening of lasers, and particularly relates to a method for obtaining an optimal aging condition of an edge-emitting laser chip and a method for screening the chip by adopting the condition.
Background
Laser chips need 100% burn-in screening after packaging into devices (TO or COC) in order TO reject early failure samples. The selection of the aging condition is crucial, the early failure sample cannot be effectively removed under the weaker aging condition, the overstress can be caused by the excessively strong aging condition, the laser chip is additionally damaged, the laser chip rapidly fails, and the service life is greatly shortened. The optimal aging condition can effectively remove early failure samples, does not cause additional damage to chips, and can be found only by designing a rigorous and reasonable test scheme.
The aging conditions had 3 parameters: duration h, drive current mA and temperature. The time length is usually controlled to be 24-48h, the temperature is usually 85-120 ℃, and when the driving current is selected, the traditional method is to find the corresponding driving current Io under the maximum power by a point test front light PI curve, and select 0.8-1.0 time of Io as the driving current to carry out matrix tests with different temperatures. However, the driving current under the maximum power obtained by the method of point testing the PI curve is different from the driving current under the actual aged maximum power. Because the point test is an instantaneous test and has a short duration, the actual aging process usually lasts for several or even tens of hours, and the junction temperatures of the two operation processes are different. Therefore, the driving current at the maximum power found by the point test is different from the driving current at the maximum power in the actual aging, so that the finally selected aging condition is not accurate.
Disclosure of Invention
Aiming at the technical problem of inaccurate aging conditions, the invention provides a method for obtaining the optimal aging conditions of the edge-emitting laser chip and a method for screening the chip by adopting the conditions.
In order to achieve the purpose, the technical scheme of the invention is realized as follows:
a method of obtaining optimal burn-in conditions for an edge-emitting laser chip, comprising the steps of:
(1) Respectively packaging a plurality of chips as a chip set I and a chip set II, and respectively carrying out aging tests on the chip set I at different aging temperatures I;
(2) Setting initial driving current, final driving current and driving current stepping in an aging test, testing at each driving current point, continuously recording backlight power values in the testing process, taking the backlight power value I recorded at the last time of each driving current point after the testing is finished, averaging the backlight power values I of all chips in a chip set I at the same driving current point, and recording as the backlight power value II under the driving current point;
(3) Comparing a backlight power value II under the point of the tested driving current from the initial driving current to the end driving current, recording the driving current corresponding to the maximum backlight power value II as a saturation current Io of the chip set I at the corresponding aging temperature I, and respectively testing the saturation currents Io corresponding to different aging temperatures I;
(4) Combining the driving current I, the aging temperature II and the aging time into an aging condition matrix, and selecting the aging temperature II to the aging temperature I tested in the step (1); each aging condition corresponds to one chip set II to carry out aging test, and after the aging test is finished, the aging failure rate of each group of chips is counted;
(5) Performing an Htol test on the aged chip set II, and counting the failure rate of the Htol after the test is finished; and comparing the aging failure rate of the Htol failure rate to 0 chip set II, wherein the aging condition corresponding to the chip set II with the highest aging failure rate is the optimal aging condition of the chip.
Conventionally packaging the chip in the step (1); preferably, packaged as TO or COC components; all chips in the chip set I are of the same type and come from the same wafer, and the chip set I comprises at least 64 chips;
in the step (1), the aging temperature I is 80-130 ℃, the temperature interval between two adjacent groups of aging temperatures I is 1-10 ℃, and usually integral temperature is selected.
In the step (2), the initial driving current is 40-60mA, the final driving current is 120-130mA, and the driving current is stepped to 1-10mA; the running time of each driving current point is an integer part of 10-15min, and the time interval when the backlight power value is continuously recorded is 1min.
And (5) the driving current I in the step (4) is 0.8-1.2 times of the saturation current Io at the corresponding aging temperature II in the aging condition matrix.
The driving current i in the aging condition matrix of the step (4) is composed of 2 or 4 of any two of the saturation currents Io of 0.8, 0.9, 1.1 and 1.2 times, and the saturation currents Io.
The chips in the chip group II are from at least 3 wafers of the same type, and each wafer is at least provided with 64 chips, so that the errors caused by the defects of the wafers are effectively reduced.
And the aging time in the aging test of the step (4) is 24-48h.
The Htol test conditions in the step (5) are as follows: the temperature is 80-90 ℃, the current is 70-80mA, and the time is 2000-3000h.
The chip aging screening method includes the steps of screening the chip under the aging condition, and screening the chip under the aging condition.
The invention has the beneficial effects that: in the matrix test of aging conditions, the selection of time and temperature is relatively easy, and the industry usually finds the saturation current point Io by using the method of point testing the front light PI, and selects 0.8-1.0 Io. Io found by the method is inaccurate, the scheme is more accurate in selection of saturation current Io, and verification on a current range is more comprehensive. The wafers in the batch test comprise three wafers in different tape-out batches, so that accidental factors of a single wafer are eliminated, and the test result is more convincing and applicable. The optimal aging condition obtained by the method is adopted to screen the wafer, the aging rejection ratio is obviously improved in the aging process, the failure ratio in the Htol stage is obviously reduced and is only 0.003%, and the aging condition screened by the method can effectively reject early failure samples without overstress.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
FIG. 1 is a scatter plot of drive current and backlight power values II at an aging temperature of 85 deg.C.
FIG. 2 is a scatter plot of drive current and backlight power values II at an aging temperature of 100 ℃.
FIG. 3 is a scatter plot of drive current and backlight power values II at a burn-in temperature of 110 ℃.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be obtained by a person skilled in the art based on the embodiments of the present invention without inventive step, are within the scope of the present invention.
Example 1
A method of obtaining optimal aging conditions for an edge-emitting laser chip, comprising the steps of:
(1) At least 64 chips with qualified performance and appearance are selected from one wafer for TO packaging. And testing after the packaging is finished, removing samples with poor performance and poor appearance, and selecting 64 qualified TO particles as a chip set I. And selecting three wafers in different tape-out batches, wherein each wafer is not less than 64 chips with qualified performance and appearance. And testing after the packaging TO is finished, eliminating samples with poor performance and poor appearance, and selecting 64 residual qualified TO in each wafer TO form a chip set II with 192 chips.
(2) The temperature of the aging box is set TO be 85 ℃, the initial driving current is 60mA, the final driving current is 120mA, the current is stepped by 5mA, the operation is carried out for 10min under each current point, the backlight power value is recorded once per minute in the operation process, after the test is finished, the backlight power value I of the last minute of each driving current point is taken, and the average value of the backlight power values I of 64 TO at the same driving current point is taken and recorded as the backlight power value II under the driving current point.
(3) And (3) testing the backlight power value II at the driving current point corresponding to the temperature of 100 ℃ and 110 ℃ according to the method in the step (2). Taking the driving currents and the backlight power value II under the three groups of temperatures as a scatter diagram, and finding the corresponding driving current Io under the maximum backlight power value, as shown in FIG. 1-3, io =105mA/85 ℃, io =95mA/100 ℃, and Io =85mA/110 ℃.
(4) An aging condition matrix is formed by combining a driving current I, an aging temperature II and aging time, the driving current I is 0.9 Io, io and 1.1 Io, the aging temperature II is 85 ℃, 100 ℃ and 110 ℃, the aging time is 48h, and the matrix experimental conditions are shown in table 1 and are totally divided into 9 groups. Aging tests were performed and the failure rate for each aging condition was recorded.
TABLE 1
(5) And performing an Htol test on all chip sets II subjected to the aging test, wherein the Htol test conditions are as follows: the temperature is 85 ℃, the current is 75mA, and the time is 2000h. And after the Htol test is finished, the failure rate of each group of chips Htol is counted.
(6) The test results are shown in table 2, and the groups 2, 3, 6, 7, 9 have failed TO at the htol stage, which indicates that the aging condition of the group is too weak TO eliminate early failure or too strong, the laser chip is overstressed, and the service life is shortened. No failed TO exists in the Htol stages of the groups 1, 4, 5 and 8, and 2 failed TO are removed in the aging stage of the group 5. No failure TO exists in the aging stages of the groups 1, 4 and 8, which shows that the group has no early failure sample, and whether the aging condition can eliminate the early failure cannot be judged. In conclusion, the aging condition of the set 5 can effectively remove early failure samples, can not cause overstress of the laser chip, and is the optimal aging condition.
TABLE 2
Example 2
A method of obtaining optimal aging conditions for an edge-emitting laser chip, comprising the steps of:
(1) At least 96 chips with qualified performance and appearance are selected from one wafer for COC packaging. And testing after the packaging is finished, removing samples with poor performance and poor appearance, and selecting 96 qualified COCs and recording the COCs as chip sets I. And selecting three wafers in different tape-out batches, wherein each wafer is not less than 96 chips with qualified performance and appearance. And testing after the COC is packaged, removing samples with poor performance and appearance, and selecting 96 residual qualified COCs from each wafer to form a chip set II with 288 chips.
(2) The temperature of the aging box is set to be 80 ℃, the driving current is started to be 40mA, the driving current is stopped to be 130mA, the current is stepped by 5mA, the operation is carried out for 15min under each current point, the backlight power value is recorded once per minute in the operation process, after the test is finished, the backlight power value I of the last minute of each driving current point is taken, and the backlight power value I of 96 COCs at the same driving current point is averaged and is recorded as the backlight power value II under the driving current point.
(3) And (3) testing the backlight power value II at the driving current point corresponding to the temperature of 90 ℃ and the temperature of 100 ℃ according to the method in the step (2). And (3) making a scatter diagram of the driving current and the backlight power value II under the three groups of temperatures, and finding out the corresponding driving current Io under the maximum backlight power value, wherein Io =110mA/80 ℃, io =100mA/90 ℃ and Io =95mA/100 ℃.
(4) An aging condition matrix is formed by combining driving current I, aging temperature II and aging time, the driving current I is 0.8 Io, io and 1.2 Io, the aging temperature II is 80 ℃, 90 ℃ and 100 ℃, the aging time is 24 hours, and the aging condition matrix is totally divided into 9 groups. Aging tests were performed and the failure rate for each aging condition was recorded.
(5) And performing an Htol test on all chip sets II subjected to the aging test, wherein the Htol test conditions are as follows: the temperature is 80 ℃, the current is 70mA, and the time is 3000h. And after the Htol test is finished, the failure rate of each group of chips Htol is counted.
(6) The test results are shown in table 3, and the failure COC exists at the 1, 2, 5, 7, 9, htol stage of the group, which indicates that the aging condition of the group is too weak to eliminate the early failure or too strong, the laser chip is overstressed, and the service life is shortened. No failure COC exists in the stages of 3, 4, 6 and 8 Htol in the groups, and 1 failure COC is removed in the stages of 3, 4 and 6 aging in the groups. Group 8 was aged to remove 2 failed COCs, indicating that group 8 had a higher probability of completely removing early failure samples. In conclusion, the aging condition of the set 8 can effectively remove early failure samples, can not cause overstress of laser chips, and is the optimal aging condition.
TABLE 3
Example 3
A method of obtaining optimal burn-in conditions for an edge-emitting laser chip, comprising the steps of:
(1) At least 64 chips with qualified performance and appearance are selected from one wafer for TO packaging. And testing after the packaging is finished, removing samples with poor performance and poor appearance, and selecting 64 qualified TO particles as a chip set I. And selecting three wafers in different tape-out batches, wherein each wafer is not less than 64 chips with qualified performance and appearance. And testing after the TO is packaged, removing samples with poor performance and appearance, and selecting 64 residual qualified TO in each wafer TO form a chipset II with 192 chips.
(2) Setting the temperature of the aging box at 80 ℃, starting drive current of 60mA, stopping drive current of 120mA, stepping current by 10mA, operating for 10min under each current point, recording backlight power value every minute in the operation process, after the test is finished, taking the backlight power value I of the last minute of each drive current point, and averaging the backlight power values I of 64 TO at the same drive current point TO be recorded as the backlight power value II under the drive current point.
(3) And (3) testing the backlight power value II at the corresponding driving current point at 90 ℃, 100 ℃, 110 ℃, 120 ℃ and 130 ℃ according to the method in the step (2). And (3) making a scatter diagram of the driving current and the backlight power value II at three temperatures of 90 ℃, 110 ℃ and 130 ℃ to find out the corresponding driving current Io at the maximum backlight power value, wherein Io =100mA/90 ℃, io =85mA/110 ℃ and Io =70mA/130 ℃.
(4) An aging condition matrix is formed by combining a driving current I, an aging temperature II and aging time, wherein the driving current I is 0.8 Io, 0.9 Io, 0.1.1 Io and 1.2 Io, the aging temperature II is 90 ℃, 110 ℃ and 130 ℃, the aging time is 36h, and the aging condition matrix is divided into 15 groups. Aging tests were performed and the failure rate for each aging condition was recorded.
(5) And performing Htol test on all the chip sets II subjected to the aging test, wherein the Htol test conditions are as follows: the temperature is 90 ℃, the current is 80mA, and the time is 2500h. And after the Htol test is finished, the failure rate of each group of chips Htol is counted.
(6) The test results are shown in table 4, and the failure TO exists in the htol stages of the groups 1, 2, 5, 7, 10, 11 and 13, which shows that the aging condition of the group is too weak TO eliminate the early failure or too strong, the laser chip is overstressed, and the service life is shortened. Groups 3, 4, 6, 8, 9, 12, 14, 15 had no failed TO in the Htol stage, and groups 4, 6, 8, 12, 14, and 15 had aging stages that rejected 1-2 early failed TO. Groups 3 and 9 aged stages rejected 3 early failure TO, groups 3 and 9 aged conditions had a higher probability of completely rejecting early failure samples. In conclusion, the aging conditions of the sets 3 and 9 can effectively remove early failure samples, can not cause overstress of the laser chip, and are optimal aging conditions.
TABLE 4
Example 4
A method for screening a chip under an aging condition, which employs the aging condition screened in example 1: and aging and screening batch chips by aging time of 48h, aging temperature of 100 ℃ and aging current of 95mA, and screening out early failure chip samples.
Comparative example
In order to prove that the aging conditions obtained by the method are more accurate, two groups of aging conditions obtained by point testing of the front light PI curve are applied to batch sheet examination, the test result is compared with the result of the embodiment 4, the result is shown in the table 5, the aging rejection ratio of the aging conditions is obviously improved in the aging process, the failure ratio of the Htol stage is obviously reduced and is only 0.003%, and the aging conditions screened by the method can effectively reject early failure samples without overstress.
TABLE 5
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents, improvements and the like that fall within the spirit and principle of the present invention are intended to be included therein.
Claims (10)
1. A method of obtaining optimal burn-in conditions for an edge-emitting laser chip, comprising the steps of:
(1) Dividing the packaged chip into a chip set I and a chip set II, and respectively carrying out aging tests on the chip set I at different aging temperatures I;
(2) Setting initial driving current, final driving current and driving current stepping in an aging test, testing at each driving current point, continuously recording backlight power values in the testing process, taking the backlight power value I recorded at the last time of each driving current point after the testing is finished, averaging the backlight power values I of all chips in a chip set I at the same driving current point, and recording as the backlight power value II under the driving current point;
(3) Comparing a backlight power value II at a tested driving current point from the initial driving current to the final driving current, recording the driving current corresponding to the maximum backlight power value II as the saturation current Io of the chip set I at the corresponding aging temperature I, and testing the saturation currents Io corresponding to different aging temperatures I respectively;
(4) Combining the driving current I, the aging temperature II and the aging time into an aging condition matrix, and selecting the aging temperature II to the aging temperature I tested in the step (1); each aging condition corresponds to one chip set II to carry out aging test, and after the aging test is finished, the aging failure rate of each group of chips is counted;
(5) Performing an Htol test on the aged chip set II, and counting the failure rate of the Htol after the test is finished; and comparing the aging failure rate of the Htol failure rate to 0 chip set II, wherein the aging condition corresponding to the chip set II with the highest aging failure rate is the optimal aging condition of the chip.
2. The method for obtaining the optimal aging condition of the edge-emitting laser chip according TO claim 1, wherein the step (1) is TO package the chip into a TO or COC package; all chips in the chip set I are of the same type and come from the same wafer, and the chip set I comprises at least 64 chips.
3. The method for obtaining the optimal aging condition of the edge-emitting laser chip according to claim 2, wherein the aging temperature I in the step (1) is 80-130 ℃, and the temperature interval between two adjacent aging temperatures I is 1-10 ℃.
4. The method for obtaining the optimal aging condition of the edge-emitting laser chip according to claim 3, wherein in the step (2), the initial driving current is 40-60mA, the final driving current is 120-130mA, and the driving current is stepped to 1-10mA; the running time of each driving current point is an integer part of 10-15min, and the time interval when the backlight power value is continuously recorded is 1min.
5. The method for obtaining the optimal aging condition of an edge-emitting laser chip as claimed in claim 4, wherein the driving current I in said step (4) is 0.8-1.2 times the saturation current Io at the corresponding aging temperature II in the aging condition matrix.
6. The method for obtaining the optimal aging condition of the edge-emitting laser chip according to claim 5, wherein the driving current I in the aging condition matrix of step (4) is composed of 2 or 4 of any two of saturation currents Io of 0.8, 0.9, 1.1 and 1.2 times, and the saturation current Io.
7. The method for obtaining the optimal aging condition of the edge-emitting laser chip as claimed in claim 5, wherein the chips in the chip set II are from at least 3 wafers of the same type, and each wafer has at least 64 chips.
8. The method for obtaining the optimal aging condition of the edge-emitting laser chip according to claim 7, wherein the aging time in the aging test of step (4) is 24-48h.
9. The method for obtaining the optimal aging condition of the edge-emitting laser chip according to claim 8, wherein the Htol test condition in the step (5) is: the temperature is 80-90 ℃, the current is 70-80mA, and the time is 2000-3000h.
10. A method of screening a chip using the aging conditions obtained by the method of any one of claims 1 to 9, wherein the chip is subjected to aging screening under the aging conditions.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210908119.3A CN115189219A (en) | 2022-07-29 | 2022-07-29 | Method for obtaining optimal aging condition of edge-emitting laser chip and method for screening chip by adopting condition |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210908119.3A CN115189219A (en) | 2022-07-29 | 2022-07-29 | Method for obtaining optimal aging condition of edge-emitting laser chip and method for screening chip by adopting condition |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN115189219A true CN115189219A (en) | 2022-10-14 |
Family
ID=83521630
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202210908119.3A Pending CN115189219A (en) | 2022-07-29 | 2022-07-29 | Method for obtaining optimal aging condition of edge-emitting laser chip and method for screening chip by adopting condition |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN115189219A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116804697A (en) * | 2023-06-25 | 2023-09-26 | 武汉敏芯半导体股份有限公司 | Aging condition acquisition method and system for laser chip and chip screening method |
-
2022
- 2022-07-29 CN CN202210908119.3A patent/CN115189219A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116804697A (en) * | 2023-06-25 | 2023-09-26 | 武汉敏芯半导体股份有限公司 | Aging condition acquisition method and system for laser chip and chip screening method |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US5240866A (en) | Method for characterizing failed circuits on semiconductor wafers | |
| CN109741779B (en) | Method for dynamically adjusting test conditions in wafer test process | |
| CN116804697A (en) | Aging condition acquisition method and system for laser chip and chip screening method | |
| CN115189219A (en) | Method for obtaining optimal aging condition of edge-emitting laser chip and method for screening chip by adopting condition | |
| CN106443539B (en) | A method of for the correction of LED light splitting machines and repetition measurement | |
| CN108693456A (en) | A kind of chip wafer test method | |
| CN115078887A (en) | Semiconductor laser aging test method and device | |
| CN110732503B (en) | Method and device for screening vertical cavity surface emitting laser chip | |
| US10658211B2 (en) | Data structures for semiconductor die packaging | |
| TW583406B (en) | Method for analyzing final test parameters | |
| US6483334B1 (en) | Method for reliability testing of semiconductor IC | |
| US20070276623A1 (en) | Semiconductor Component Test Process and a System for Testing Semiconductor Components | |
| CN111146106A (en) | Method for rapidly screening failure risk of chip | |
| CN114210605B (en) | Silicon carbide power semiconductor device testing method | |
| CN113945824B (en) | Radio frequency chip screening method | |
| US6442499B1 (en) | Methods and apparatus for statistical process control of test | |
| CN112103215B (en) | Method for monitoring attenuation of slice or series welding performance of battery piece | |
| CN115686898A (en) | Multi-stage fault mode and influence analysis method and system | |
| JP3210505B2 (en) | Screening method for semiconductor laser diode | |
| CN112630627B (en) | Extraction and measurement method and system based on multi-station serial measurement | |
| US6476617B1 (en) | Method of sorting monolithic ceramic capacitors by measuring the insulation resistance thereof | |
| CN114448497B (en) | Quick full-temperature optical module testing method | |
| CN114152823A (en) | Method for evaluating quick reliability of high-reliability long-life liquid crystal display device | |
| CN113030711B (en) | Power amplifier chip, chip testing system and method | |
| CN111934186B (en) | Method for judging optical catastrophe type of semiconductor laser chip |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |