CN115179186B - Method for manufacturing semiconductor device - Google Patents

Method for manufacturing semiconductor device Download PDF

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Publication number
CN115179186B
CN115179186B CN202210858675.4A CN202210858675A CN115179186B CN 115179186 B CN115179186 B CN 115179186B CN 202210858675 A CN202210858675 A CN 202210858675A CN 115179186 B CN115179186 B CN 115179186B
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Prior art keywords
metal layer
acid
semiconductor device
manufacturing
polishing
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CN202210858675.4A
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Chinese (zh)
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CN115179186A (en
Inventor
杨一凡
高志强
张志军
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Wuhan Xinxin Semiconductor Manufacturing Co Ltd
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Wuhan Xinxin Semiconductor Manufacturing Co Ltd
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Classifications

    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B24—GRINDING; POLISHING
    • B24B—MACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING; DRESSING OR CONDITIONING OF ABRADING SURFACES; FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS
    • B24B37/00—Lapping machines or devices; Accessories
    • B24B37/04—Lapping machines or devices; Accessories designed for working plane surfaces
    • B24B37/07—Lapping machines or devices; Accessories designed for working plane surfaces characterised by the movement of the work or lapping tool
    • B24B37/10—Lapping machines or devices; Accessories designed for working plane surfaces characterised by the movement of the work or lapping tool for single side lapping
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B24—GRINDING; POLISHING
    • B24B—MACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING; DRESSING OR CONDITIONING OF ABRADING SURFACES; FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS
    • B24B37/00—Lapping machines or devices; Accessories
    • B24B37/11—Lapping tools
    • B24B37/20—Lapping pads for working plane surfaces
    • B24B37/24—Lapping pads for working plane surfaces characterised by the composition or properties of the pad materials
    • B24B37/245—Pads with fixed abrasives
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B24—GRINDING; POLISHING
    • B24B—MACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING; DRESSING OR CONDITIONING OF ABRADING SURFACES; FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS
    • B24B57/00—Devices for feeding, applying, grading or recovering grinding, polishing or lapping agents
    • B24B57/02—Devices for feeding, applying, grading or recovering grinding, polishing or lapping agents for feeding of fluid, sprayed, pulverised, or liquefied grinding, polishing or lapping agents
    • C—CHEMISTRY; METALLURGY
    • C09—DYES; PAINTS; POLISHES; NATURAL RESINS; ADHESIVES; COMPOSITIONS NOT OTHERWISE PROVIDED FOR; APPLICATIONS OF MATERIALS NOT OTHERWISE PROVIDED FOR
    • C09K—MATERIALS FOR MISCELLANEOUS APPLICATIONS, NOT PROVIDED FOR ELSEWHERE
    • C09K3/00—Materials not provided for elsewhere
    • C09K3/14—Anti-slip materials; Abrasives
    • C09K3/1454—Abrasive powders, suspensions and pastes for polishing
    • C09K3/1463—Aqueous liquid suspensions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30625—With simultaneous mechanical treatment, e.g. mechanico-chemical polishing

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  • Engineering & Computer Science (AREA)
  • Mechanical Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Organic Chemistry (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)

Abstract

The invention provides a manufacturing method of a semiconductor device, which comprises the following steps: providing a substrate, wherein a dielectric layer is formed on the substrate; forming an opening in the dielectric layer and the substrate, and filling the opening with a metal layer to cover the upper surface of the dielectric layer; and grinding the part of the metal layer higher than the dielectric layer, wherein a grinding pad contacts the metal layer for grinding, hard particles are arranged on the surface of the grinding pad, and the particle size range of the hard particles is 6000-10000 of the mesh number of the international screen specification. In the grinding process, the grinding pad adopts hard particles with smaller particle size to grind the metal layer, so as to grind the ultra-thick metal layer (such as copper metal layer).

Description

Method for manufacturing semiconductor device
Technical Field
The invention belongs to the technical field of integrated circuit manufacturing, and particularly relates to a manufacturing method of a semiconductor device.
Background
Three-dimensional (3D) packaging technology may meet the increasing demands of consumers for smaller, more convenient, and higher reliability of electronic products, and among many 3D packaging technologies, openings (TSVs) are considered as the core of 3D packaging. In the process of manufacturing the TSV, a method of electroplating is required to fill copper in the TSV through hole as an interconnection structure. In the fabrication process, copper is used to fill the openings, cover the surface of the film above the substrate (e.g., silicon substrate), and polish the copper by Chemical Mechanical Polishing (CMP) to remove the copper from the surface of the film above the substrate and planarize the wafer surface.
The thickness of copper on the surface of the film layer above the substrate is usually controlled within 10 μm; however, for some applications, the thickness of copper on the surface of the film layer above the substrate may be on the order of tens of μm, and for such ultra-thick copper (Cu) polishing, conventional Cu process polishing is currently adopted, the rate is low, the polishing time is very long, for example, the polishing time reaches tens of minutes through multiple polishing, and the polishing consistency is poor, and the process is difficult to control.
Disclosure of Invention
The invention aims to provide a manufacturing method of a semiconductor device, wherein a polishing pad adopts hard particles with smaller particle size to polish a metal layer in the CMP process, so as to polish an ultra-thick metal layer (such as a copper metal layer).
The invention provides a manufacturing method of a semiconductor device, which comprises the following steps:
providing a substrate, wherein a dielectric layer is formed on the substrate; forming an opening in the dielectric layer and the substrate, and filling the opening with a metal layer to cover the upper surface of the dielectric layer;
and grinding the part of the metal layer higher than the dielectric layer, wherein a grinding pad contacts the metal layer for grinding, hard particles are arranged on the surface of the grinding pad, and the particle size range of the hard particles is 6000-10000 of the mesh number of the international screen specification.
Further, the hard micro-particles include diamond particles.
Further, the metal layer is made of Cu, and deionized water, cu grinding fluid and Cu protection fluid are added in the grinding process for grinding.
Further, the Cu polishing liquid is acidic, and includes: aqueous medium, abrasive particles, oxidizing agent, acids, and organic additives; the content of the abrasive particles, the oxidizing agent, the acids and the organic additives is 1 to 30wt% respectively, relative to the total weight of the Cu polishing slurry; 1-10wt%;0.001-5wt%;0.001-1wt% of the balance of the aqueous medium.
Further, the abrasive particles are colloidal silica particles or colloidal alumina particles, the oxidizing agent is at least one substance containing peroxy groups, the acid is at least one organic acid or inorganic acid or a mixture of the two, and the organic additive is quaternary ammonium salt.
Further, the organic acid in the acid is at least one component selected from benzotriazole, citric acid, citrate and ethylenediamine tetraacetic acid.
Further, the inorganic acid in the acids is at least one component selected from sulfuric acid, nitric acid, hydrochloric acid and phosphoric acid.
Further, the Cu protection solution includes: a mixed solution of benzotriazole, ethanol and soap.
Further, the flow range of the Cu grinding fluid is as follows: 100 ml/min-300 ml/min; the rotating speed range of the grinding pad is as follows: 20 rpm-30 rpm.
Further, a barrier layer is formed on the side wall and the bottom surface of the opening, and the metal layer covers the barrier layer and fills the opening.
Compared with the prior art, the invention has the following beneficial effects:
the invention provides a manufacturing method of a semiconductor device, which comprises the following steps: providing a substrate, wherein a dielectric layer is formed on the substrate; forming an opening in the dielectric layer and the substrate, and filling the opening with a metal layer to cover the upper surface of the dielectric layer; and (3) polishing the part of the metal layer higher than the dielectric layer by executing a CMP process, wherein a polishing pad contacts the metal layer for polishing, hard particles are arranged on the surface of the polishing pad, and the particle size range of the hard particles is 6000-10000 of mesh number of international screen mesh specification. In the CMP process, the polishing pad adopts hard particles with smaller particle size to polish the metal layer, so as to realize the polishing of the ultra-thick metal layer (such as copper metal layer).
Furthermore, the invention adopts the grinding pad with smaller particle size of hard particles, and simultaneously combines deionized water, cu grinding fluid and Cu protection fluid to efficiently thin ultra-thick Cu, thereby realizing the grinding process of ultra-thick copper.
Drawings
Fig. 1 is a schematic flow chart of a method for manufacturing a semiconductor device according to an embodiment of the invention.
Fig. 2 is a schematic diagram of a semiconductor device after forming an opening in the method for manufacturing the semiconductor device according to an embodiment of the invention.
Fig. 3 is a schematic diagram illustrating polishing in a method for manufacturing a semiconductor device according to an embodiment of the invention.
Fig. 4 is a schematic diagram of a semiconductor device manufactured by the method according to an embodiment of the invention after polishing.
Wherein, the reference numerals are as follows:
10-a substrate; 11-a dielectric layer; 12-a metal layer; 20-a polishing pad; 30-spraying pipe; v-openings.
Detailed Description
Based on the above study, the embodiment of the invention provides a manufacturing method of a semiconductor device. The invention is described in further detail below with reference to the drawings and the specific examples. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the drawings are in a very simplified form and are not to scale precisely, but rather merely for the purpose of facilitating and clearly aiding in the description of the embodiments of the invention.
For ease of description, some embodiments of the present application may use spatially relative terms such as "above" …, "" below "…," "top," "below," and the like to describe one element or component's relationship to another element(s) or component(s) as illustrated in the various figures of the embodiments. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements or components described as "below" or "beneath" other elements or components would then be oriented "above" or "over" the other elements or components. The terms "first," "second," and the like, herein below, are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that such terms so used are interchangeable under appropriate circumstances.
An embodiment of the present invention provides a method for manufacturing a semiconductor device, as shown in fig. 1, including:
step S1, providing a substrate, wherein a dielectric layer is formed on the substrate; forming openings in the dielectric layer and the substrate, and filling the openings with a metal layer to cover the surface of the dielectric layer;
and S2, grinding the part of the metal layer higher than the medium layer, wherein a grinding pad contacts with the metal layer for grinding, hard particles are arranged on the surface of the grinding pad, and the particle size range of the hard particles is 6000-10000 of the mesh number of the international screen mesh specification.
The steps of the method for manufacturing a semiconductor device according to an embodiment of the present invention will be described with reference to fig. 2 to 4.
As shown in fig. 2 and 3, a substrate 10 is provided, a dielectric layer 11 is formed on the substrate 10, an opening V is formed in the dielectric layer 11 and the substrate 10, and a metal layer 12 fills the opening and covers the upper surface of the dielectric layer 11.
Specifically, a substrate 10 is provided, and a dielectric layer 11 is formed on the substrate 10. The dielectric layer 11 is, for example, a silicon oxide layer and/or a silicon nitride layer. The substrate 10 may comprise a semiconductor material such as silicon, germanium, silicon-germanium, or the like, or a III-V semiconductor compound such as GaP, gaAs, gaSb, or the like. In some embodiments, the substrate 10 may be a silicon-on-insulator (SOI) substrate or a germanium-on-insulator (GOI) substrate. Further, although not shown, the substrate 10 may include a conductive pattern. The conductive pattern may be a metal line, a contact, a conductive pad, or the like, and may be a gate electrode of a transistor, a source/drain of a transistor, or a diode, but the embodiment is not limited thereto.
An opening V is formed, which extends through the dielectric layer 11 and a part of the thickness of the substrate 10. The opening V may be formed, for example, by dry etching.
A metal layer 12 is formed, the metal layer 12 filling the opening V and covering the upper surface of the dielectric layer 11. The material of the metal layer 12 includes at least one of copper, tungsten and cobalt. A conventional damascene process may be used to deposit a metal barrier layer (not shown) and metal layer 12 in the openings. A barrier layer may be formed on the sidewalls and bottom of the opening, and may include, for example, titanium nitride, tantalum nitride, and the like. The barrier layer prevents metal ions in the metal layer 12 from diffusing into the substrate 10. The metal layer 12 covers the barrier layer and fills the opening, i.e. the sides and bottom of the metal layer 12 in the opening are surrounded by the barrier layer. Illustratively, the thickness of the metal layer 12 on the upper surface of the dielectric layer 11 is 20 μm or more.
As shown in fig. 3, the portion of the metal layer 12 higher than the dielectric layer 11 may be polished by performing a CMP process, the polishing pad 20 contacts the metal layer 12 and is polished, and hard particles having a particle size ranging from 6000 to 10000 mesh of international screen size are provided on the surface of the polishing pad 20. The hard fine particles are diamond particles, for example. The higher the mesh number, the smaller the particle size. The mesh is the number of holes per unit area of the screen, and the higher the mesh, the more holes. In addition to the mesh of the screen, the mesh is used to indicate the particle size of particles passing through the screen, with the mesh being smaller as the number of the mesh is higher. The embodiment of the invention adopts the grinding process of ultra-thick copper, wherein the size of the hard particles of the grinding pad is smaller.
Specifically, a wafer thinning (Grind) device is provided with a polishing table for polishing a wafer and a chuck for carrying the polished wafer. Wherein the chuck holds the back side of the wafer and then presses the front side of the wafer against a polishing table provided with a layer of polishing pad 20. When performing chemical mechanical polishing, the polishing table rotates along a fixed direction, and the motion direction of the polishing head is, for example, linear motion or rotates along a fixed direction as the polishing table. The material of the metal layer comprises Cu, and deionized water, cu grinding liquid and Cu protection liquid are added in the CMP process for grinding. Deionized water, cu slurry, and Cu protection liquid may be sprayed from the spray bar 30.
As shown in fig. 4, the metal layer on the surface of the dielectric layer over the substrate 10 is removed and the surface of the semiconductor device is planarized by polishing using a Chemical Mechanical Polishing (CMP) method.
The Cu polishing liquid is, for example, an acidic polishing liquid having PH 2 to 5, and includes: aqueous medium, abrasive particles, oxidizing agent, acids and organic additives. The content of the above-mentioned abrasive particles, oxidizing agent, acids and organic additives is 1-30wt% respectively relative to the total weight of the Cu polishing liquid; 1-10wt%;0.001-5wt%;0.001-1wt% of an aqueous medium for the rest; wt% is weight percent. Illustratively, the abrasive particles are colloidal oxide particles, the oxidizing agent is at least one peroxy-containing material, the acid is at least one organic acid or inorganic acid or a mixture thereof, and the organic additive is a quaternary ammonium salt. Aqueous mediumThe quality is deionized water or distilled water. The abrasive particles and colloidal oxide particles are colloidal Silica (SIO) 2 ) Particles or colloidal alumina particles. The substance containing peroxy group is at least one selected from hydrogen peroxide, ammonium persulfate, peracetic acid and periodic acid. The organic acid in the acid is at least one component selected from benzotriazole, citric acid, citrate and ethylenediamine tetraacetic acid. The inorganic acid in the acid is at least one component selected from sulfuric acid, nitric acid, hydrochloric acid and phosphoric acid. Cu polishing liquid flow range: the rotation speed range of the polishing pad is 100 ml/min-300 ml/min: 20 rpm-30 rpm.
The Cu protective solution prevents oxidative discoloration of the Cu metal layer. The Cu protective liquid may include: a mixed solution of Benzotriazole (BTA), ethanol and soap; for example, 200-400 g of benzotriazole and 100-200 ml of ethanol are prepared into a solution, and then the solution is dissolved in 160-240 ml of soap solution with the mass concentration of 3-4%, so that the Cu protection solution is prepared. Cu is substituted with H+ in Benzotriazole (BTA) molecule to form a film of chain polymer oriented parallel to copper surface, which film has a certain degree of stability even at a relatively high temperature, thereby inhibiting oxidation of copper.
In the embodiment, the particle size of the hard particles of the grinding pad is smaller, and meanwhile, the ultra-thick Cu is efficiently thinned by matching with deionized water, cu grinding fluid and Cu protection fluid, so that the ultra-thick copper grinding process is realized.
In summary, the present invention provides a method for manufacturing a semiconductor device, including: providing a substrate, wherein a dielectric layer is formed on the substrate; forming an opening in the dielectric layer and the substrate, and filling the opening with a metal layer to cover the upper surface of the dielectric layer; and (3) polishing the part of the metal layer higher than the dielectric layer by executing a CMP process, wherein a polishing pad contacts the metal layer for polishing, hard particles are arranged on the surface of the polishing pad, and the particle size range of the hard particles is 6000-10000 of mesh number of international screen mesh specification. In the CMP process, the polishing pad adopts hard particles with smaller particle size to polish the metal layer, so as to realize the polishing of the ultra-thick metal layer (such as copper metal layer).
In the present specification, each embodiment is described in a progressive manner, and each embodiment is mainly described in a different point from other embodiments, and identical and similar parts between the embodiments are all enough to refer to each other. For the method disclosed in the embodiment, the description is relatively simple since it corresponds to the device disclosed in the embodiment, and the relevant points refer to the description of the method section.
The foregoing description is only illustrative of the preferred embodiments of the present invention, and is not intended to limit the scope of the claims, and any person skilled in the art may make any possible variations and modifications to the technical solution of the present invention using the method and technical content disclosed above without departing from the spirit and scope of the invention, so any simple modification, equivalent variation and modification made to the above embodiments according to the technical matter of the present invention fall within the scope of the technical solution of the present invention.

Claims (9)

1. A method for manufacturing a semiconductor device for polishing a metal layer having a thickness of more than 10 μm, comprising:
providing a substrate, wherein a dielectric layer is formed on the substrate; forming openings in the dielectric layer and the substrate, and filling the openings with a metal layer to cover the surface of the dielectric layer;
grinding the part of the metal layer higher than the dielectric layer, wherein a grinding pad contacts the metal layer for grinding, the surface of the grinding pad is provided with hard particles, and the particle size range of the hard particles is 6000-10000 of mesh size of international screen mesh specification;
the material of the metal layer comprises Cu, and a Cu protective solution is added in the grinding process; the Cu protective solution comprises: a mixed solution of benzotriazole, ethanol and soap; the Cu protection liquid configuration proportion comprises: firstly, preparing 200-400 g of benzotriazole and 100-200 ml of ethanol into a solution, and then dissolving the solution into 160-240 ml of soap solution with the mass concentration of 3-4%, thus preparing the Cu protection solution; cu is replaced by H+ in the benzotriazole molecule to form a chain polymer film which is oriented parallel to the surface of copper, so that oxidation of copper is inhibited; the Cu protective solution prevents oxidative discoloration of the Cu metal layer.
2. The method of manufacturing a semiconductor device according to claim 1, wherein the hard particles comprise diamond particles.
3. The method of manufacturing a semiconductor device according to claim 1, wherein deionized water and Cu polishing liquid are further added to the polishing process for polishing.
4. The method for manufacturing a semiconductor device according to claim 3, wherein the Cu polishing liquid is acidic, comprising: aqueous medium, abrasive particles, oxidizing agent, acids, and organic additives; the content of the abrasive particles, the oxidizing agent, the acids and the organic additives is 1 to 30wt% respectively, relative to the total weight of the Cu polishing slurry; 1-10wt%;0.001-5wt%;0.001-1wt% of the balance of the aqueous medium.
5. The method according to claim 4, wherein the abrasive particles are colloidal silica particles or colloidal alumina particles, the oxidizing agent is at least one peroxy-containing substance, the acid is at least one organic acid or inorganic acid or a mixture of both, and the organic additive is a quaternary ammonium salt.
6. The method for manufacturing a semiconductor device according to claim 5, wherein the organic acid in the acid is at least one member selected from the group consisting of benzotriazole, citric acid, citrate, and ethylenediamine tetraacetic acid.
7. The method for manufacturing a semiconductor device according to claim 5, wherein the inorganic acid in the acid is at least one member selected from the group consisting of sulfuric acid, nitric acid, hydrochloric acid and phosphoric acid.
8. The method for manufacturing a semiconductor device according to claim 3, wherein a flow rate range of the Cu polishing slurry is: 100 ml/min-300 ml/min; the rotating speed range of the grinding pad is as follows: 20 rpm-30 rpm.
9. The method of manufacturing a semiconductor device according to claim 1, wherein a barrier layer is further formed on a side wall and a bottom surface of the opening, and the metal layer covers the barrier layer and fills the opening.
CN202210858675.4A 2022-07-20 2022-07-20 Method for manufacturing semiconductor device Active CN115179186B (en)

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Citations (10)

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Publication number Priority date Publication date Assignee Title
JP2004319759A (en) * 2003-04-16 2004-11-11 Hitachi Chem Co Ltd Polishing solution for metal and polishing method
JP2006165272A (en) * 2004-12-07 2006-06-22 Hitachi Chem Co Ltd Polishing solution and polishing method
JP2007103485A (en) * 2005-09-30 2007-04-19 Fujifilm Corp Polishing method, and polishing liquid used therefor
CN101463227A (en) * 2007-12-21 2009-06-24 安集微电子（上海）有限公司 Chemico-mechanical polishing solution for barrier layer
CN102615584A (en) * 2011-01-31 2012-08-01 中芯国际集成电路制造(上海)有限公司 Chemical mechanical grinding method
CN103681309A (en) * 2012-09-07 2014-03-26 中芯国际集成电路制造(上海)有限公司 Manufacturing method for ultra-thickness metal
CN204748298U (en) * 2014-12-08 2015-11-11 智胜科技股份有限公司 Polishing system and polishing pad assembly
CN110491790A (en) * 2018-05-09 2019-11-22 台湾积体电路制造股份有限公司 The manufacturing method of semiconductor device
CN112171513A (en) * 2020-09-29 2021-01-05 合肥晶合集成电路股份有限公司 Polishing pad processing method and chemical mechanical polishing equipment
TW202225352A (en) * 2020-12-30 2022-07-01 大陸商安集微電子科技(上海)股份有限公司 Chemical mechanical polishing slurry and method of using the same

Patent Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004319759A (en) * 2003-04-16 2004-11-11 Hitachi Chem Co Ltd Polishing solution for metal and polishing method
JP2006165272A (en) * 2004-12-07 2006-06-22 Hitachi Chem Co Ltd Polishing solution and polishing method
JP2007103485A (en) * 2005-09-30 2007-04-19 Fujifilm Corp Polishing method, and polishing liquid used therefor
CN101463227A (en) * 2007-12-21 2009-06-24 安集微电子（上海）有限公司 Chemico-mechanical polishing solution for barrier layer
CN102615584A (en) * 2011-01-31 2012-08-01 中芯国际集成电路制造(上海)有限公司 Chemical mechanical grinding method
CN103681309A (en) * 2012-09-07 2014-03-26 中芯国际集成电路制造(上海)有限公司 Manufacturing method for ultra-thickness metal
CN204748298U (en) * 2014-12-08 2015-11-11 智胜科技股份有限公司 Polishing system and polishing pad assembly
CN110491790A (en) * 2018-05-09 2019-11-22 台湾积体电路制造股份有限公司 The manufacturing method of semiconductor device
CN112171513A (en) * 2020-09-29 2021-01-05 合肥晶合集成电路股份有限公司 Polishing pad processing method and chemical mechanical polishing equipment
TW202225352A (en) * 2020-12-30 2022-07-01 大陸商安集微電子科技(上海)股份有限公司 Chemical mechanical polishing slurry and method of using the same

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