CN115179186A - Method for manufacturing semiconductor device - Google Patents

Method for manufacturing semiconductor device Download PDF

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Publication number
CN115179186A
CN115179186A CN202210858675.4A CN202210858675A CN115179186A CN 115179186 A CN115179186 A CN 115179186A CN 202210858675 A CN202210858675 A CN 202210858675A CN 115179186 A CN115179186 A CN 115179186A
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China
Prior art keywords
acid
metal layer
semiconductor device
particles
manufacturing
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CN202210858675.4A
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Chinese (zh)
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CN115179186B (en
Inventor
杨一凡
高志强
张志军
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Wuhan Xinxin Semiconductor Manufacturing Co Ltd
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Wuhan Xinxin Semiconductor Manufacturing Co Ltd
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Publication of CN115179186A publication Critical patent/CN115179186A/en
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    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B24—GRINDING; POLISHING
    • B24B—MACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING; DRESSING OR CONDITIONING OF ABRADING SURFACES; FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS
    • B24B37/00—Lapping machines or devices; Accessories
    • B24B37/04—Lapping machines or devices; Accessories designed for working plane surfaces
    • B24B37/07—Lapping machines or devices; Accessories designed for working plane surfaces characterised by the movement of the work or lapping tool
    • B24B37/10—Lapping machines or devices; Accessories designed for working plane surfaces characterised by the movement of the work or lapping tool for single side lapping
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B24—GRINDING; POLISHING
    • B24B—MACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING; DRESSING OR CONDITIONING OF ABRADING SURFACES; FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS
    • B24B37/00—Lapping machines or devices; Accessories
    • B24B37/11—Lapping tools
    • B24B37/20—Lapping pads for working plane surfaces
    • B24B37/24—Lapping pads for working plane surfaces characterised by the composition or properties of the pad materials
    • B24B37/245—Pads with fixed abrasives
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B24—GRINDING; POLISHING
    • B24B—MACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING; DRESSING OR CONDITIONING OF ABRADING SURFACES; FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS
    • B24B57/00—Devices for feeding, applying, grading or recovering grinding, polishing or lapping agents
    • B24B57/02—Devices for feeding, applying, grading or recovering grinding, polishing or lapping agents for feeding of fluid, sprayed, pulverised, or liquefied grinding, polishing or lapping agents
    • C—CHEMISTRY; METALLURGY
    • C09—DYES; PAINTS; POLISHES; NATURAL RESINS; ADHESIVES; COMPOSITIONS NOT OTHERWISE PROVIDED FOR; APPLICATIONS OF MATERIALS NOT OTHERWISE PROVIDED FOR
    • C09K—MATERIALS FOR MISCELLANEOUS APPLICATIONS, NOT PROVIDED FOR ELSEWHERE
    • C09K3/00—Materials not provided for elsewhere
    • C09K3/14—Anti-slip materials; Abrasives
    • C09K3/1454—Abrasive powders, suspensions and pastes for polishing
    • C09K3/1463—Aqueous liquid suspensions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30625—With simultaneous mechanical treatment, e.g. mechanico-chemical polishing

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  • Engineering & Computer Science (AREA)
  • Mechanical Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Materials Engineering (AREA)
  • Organic Chemistry (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)

Abstract

The invention provides a manufacturing method of a semiconductor device, which comprises the following steps: providing a substrate, wherein a dielectric layer is formed on the substrate; forming openings in the dielectric layer and the substrate, and filling the openings with a metal layer and covering the upper surface of the dielectric layer; grinding the part of the metal layer higher than the dielectric layer, wherein the grinding pad is in contact with the metal layer for grinding, hard micro-particles are arranged on the surface of the grinding pad, and the particle size range of the hard micro-particles is 6000-10000 meshes of the international screen specification. In the grinding process, the grinding pad adopts the hard particles with smaller particle size to grind the metal layer, thereby realizing the grinding of the ultra-thick metal layer (such as a copper metal layer).

Description

Method for manufacturing semiconductor device
Technical Field
The invention belongs to the technical field of integrated circuit manufacturing, and particularly relates to a manufacturing method of a semiconductor device.
Background
Three-dimensional (3D) packaging technology can meet the increasing demands of consumers for smaller, more convenient and more reliable electronic products, and among the 3D packaging technologies, an opening (TSV) is considered as a core of the 3D package. In the process of manufacturing the TSV, an electroplating method is required to fill copper in the TSV as an interconnect structure. In the fabrication process, copper covers the surface of the film layer over the substrate (e.g., silicon substrate) in addition to filling the opening, and the copper is polished by Chemical Mechanical Polishing (CMP) to remove the copper from the surface of the film layer over the substrate and planarize the wafer surface.
The thickness of copper on the surface of the film layer above the substrate is generally controlled to be within 10 μm; however, for some applications, the thickness of the copper on the surface of the film layer above the substrate may be in the order of tens of μm, and for such ultra-thick copper (Cu) polishing, the conventional Cu process is currently used, the polishing rate is low, the polishing time is extremely long, for example, by multiple times of polishing, the polishing time reaches tens of minutes, and the polishing consistency is poor, and the process is difficult to control.
Disclosure of Invention
The invention aims to provide a method for manufacturing a semiconductor device, wherein a polishing pad in a CMP process of the invention adopts hard particles with smaller particle size to polish a metal layer, thereby realizing the polishing of an ultra-thick metal layer (such as a copper metal layer).
The invention provides a manufacturing method of a semiconductor device, which comprises the following steps:
providing a substrate, wherein a dielectric layer is formed on the substrate; forming openings in the dielectric layer and the substrate, and filling the openings with a metal layer and covering the upper surface of the dielectric layer;
grinding the part of the metal layer higher than the dielectric layer, wherein the grinding pad is in contact with the metal layer for grinding, hard micro-particles are arranged on the surface of the grinding pad, and the particle size range of the hard micro-particles is 6000-10000 meshes of the international screen specification.
Further, the hard microparticles include diamond particles.
Further, the material of the metal layer comprises Cu, and deionized water, cu grinding liquid and Cu protection liquid are added in the grinding process for grinding.
Further, the Cu polishing liquid is acidic, and includes: aqueous medium, abrasive particles, oxidizing agent, acid and organic additive; the contents of the abrasive particles, the oxidizing agent, the acid, and the organic additive are each 1 to 30wt% with respect to the total weight of the Cu polishing liquid; 1-10wt%;0.001-5wt%;0.001 to 1wt%, the balance being the aqueous medium.
Further, the grinding particles are colloidal silica particles or colloidal alumina particles, the oxidant is at least one substance containing peroxy groups, the acid is at least one organic acid or inorganic acid or a mixture of the organic acid and the inorganic acid, and the organic additive is a quaternary ammonium salt.
Further, the organic acid in the acid group is at least one member selected from the group consisting of benzotriazole, citric acid, citrate, and ethylenediaminetetraacetic acid.
Further, the inorganic acid in the acid group is at least one member selected from the group consisting of sulfuric acid, nitric acid, hydrochloric acid and phosphoric acid.
Further, the Cu protective solution includes: benzotriazole, ethanol and soap solution.
Further, the flow range of the Cu polishing liquid is: 100 ml/min-300 ml/min; the rotation speed range of the grinding pad is as follows: 20rpm to 30rpm.
Furthermore, barrier layers are formed on the side walls and the bottom surfaces of the openings, and the metal layer covers the barrier layers and fills the openings.
Compared with the prior art, the invention has the following beneficial effects:
the invention provides a manufacturing method of a semiconductor device, which comprises the following steps: providing a substrate, wherein a dielectric layer is formed on the substrate; forming openings in the dielectric layer and the substrate, and filling the openings with a metal layer and covering the upper surface of the dielectric layer; and executing a CMP process to grind the part of the metal layer higher than the dielectric layer, wherein a grinding pad is in contact with the metal layer for grinding, hard particles are arranged on the surface of the grinding pad, and the particle size range of the hard particles is 6000-10000 of the mesh number of the international screen specification. In the CMP process, the grinding pad adopts the hard particles with smaller particle size to grind the metal layer, thereby realizing the grinding of the ultra-thick metal layer (such as a copper metal layer).
Furthermore, the grain size of the hard particles of the grinding pad is smaller, and the ultra-thick Cu is efficiently thinned by matching with deionized water, cu grinding liquid and Cu protective liquid, so that the grinding process of the ultra-thick copper is realized.
Drawings
Fig. 1 is a schematic flow chart of a method for manufacturing a semiconductor device according to an embodiment of the present invention.
Fig. 2 is a schematic diagram illustrating a semiconductor device according to an embodiment of the present invention after an opening is formed.
Fig. 3 is a schematic diagram illustrating a polishing process performed in the method for manufacturing a semiconductor device according to an embodiment of the present invention.
Fig. 4 is a schematic diagram of a semiconductor device after polishing in the method for manufacturing the semiconductor device according to the embodiment of the invention.
Wherein the reference numbers are as follows:
10-a substrate; 11-a dielectric layer; 12-a metal layer; 20-a polishing pad; 30-a spray pipe; v-opening.
Detailed Description
Based on the above research, an embodiment of the present invention provides a method for manufacturing a semiconductor device. The invention is described in further detail below with reference to the figures and specific examples. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the drawings are in a very simplified form and are not to precise scale, which is intended merely for convenience and clarity in assisting in the description of the embodiments of the invention.
For ease of description, some embodiments of the present application may use spatially relative terms such as "above 8230; above", "below 8230; top", "below", and the like to describe the relationship of one element or component to another (or other) element or component as illustrated in the various figures of the embodiments. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements or components described as "below" or "beneath" other elements or components would then be oriented "above" or "over" the other elements or components. The terms "first," "second," and the like in the following description are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the terms so used are interchangeable under appropriate circumstances.
An embodiment of the present invention provides a method for manufacturing a semiconductor device, as shown in fig. 1, including:
the method comprises the following steps of S1, providing a substrate, wherein a dielectric layer is formed on the substrate; forming openings in the dielectric layer and the substrate, and filling the openings with a metal layer and covering the surface of the dielectric layer;
and S2, grinding the part of the metal layer higher than the dielectric layer, grinding the part of the metal layer by contacting a grinding pad with the metal layer, wherein hard particles are arranged on the surface of the grinding pad, and the particle size range of the hard particles is 6000-10000 of the mesh number of the international screen specification.
The steps of the method for manufacturing a semiconductor device according to the embodiment of the present invention will be described with reference to fig. 2 to 4.
As shown in fig. 2 and fig. 3, a substrate 10 is provided, a dielectric layer 11 is formed on the substrate 10, an opening V is formed in the dielectric layer 11 and the substrate 10, and a metal layer 12 fills the opening and covers an upper surface of the dielectric layer 11.
Specifically, a substrate 10 is provided, and a dielectric layer 11 is formed on the substrate 10. The dielectric layer 11 is, for example, a silicon oxide layer and/or a silicon nitride layer. The substrate 10 may comprise a semiconductor material such as silicon, germanium, silicon-germanium, or the like, or a III-V semiconductor compound such as GaP, gaAs, gaSb, or the like. In some embodiments, the substrate 10 may be a silicon-on-insulator (SOI) substrate or a germanium-on-insulator (GOI) substrate. Further, although not shown, the substrate 10 may include a conductive pattern. The conductive pattern may be a metal line, a contact, a conductive pad, etc., and may be a gate electrode of a transistor, a source/drain of a transistor, or a diode, but the embodiment is not limited thereto.
An opening V is formed through the dielectric layer 11 and a portion of the thickness of the substrate 10. The opening V can be formed, for example, by dry etching.
And forming a metal layer 12, wherein the metal layer 12 fills the opening V and covers the upper surface of the dielectric layer 11. The material of the metal layer 12 includes at least one of copper, tungsten, and cobalt. A metal barrier layer (not shown) and metal layer 12 may be deposited in the openings using a conventional damascene process. A barrier layer can be formed on the sidewalls and bottom surface of the opening and can comprise, for example, titanium nitride, tantalum nitride, and the like. The barrier layer prevents metal ions in the metal layer 12 from diffusing into the substrate 10. The metal layer 12 covers the barrier layer and fills the opening, i.e. the sides and bottom of the metal layer 12 in the opening are surrounded by the barrier layer. Illustratively, the metal layer 12 on the upper surface of the dielectric layer 11 has a thickness of 20 μm or more.
As shown in fig. 3, a portion of the metal layer 12 higher than the dielectric layer 11 may be polished by performing a CMP process, a polishing pad 20 contacting the metal layer 12 may be polished, and hard particles having a particle size range of 6000 to 10000 according to international mesh size may be disposed on a surface of the polishing pad 20. The hard fine particles are, for example, diamond particles. The higher the mesh number, the smaller the particle size. The mesh refers to the number of holes on a unit area screen, and the higher the mesh is, the more the holes are. In addition to indicating the mesh of the screen, mesh is also used to indicate the particle size of the particles that can pass through the screen, with higher mesh numbers leading to smaller particle sizes. The embodiment of the invention adopts the grinding pad with the hard particles with smaller particle size to realize the grinding process of the ultra-thick copper.
Specifically, the wafer thinning (Grind) apparatus is provided with a polishing table for polishing the wafer and a chuck for supporting the wafer to be polished. Wherein the suction cups hold the back side of the wafer and then press the front side of the wafer against a polishing table provided with a layer of polishing pad 20. When performing chemical mechanical polishing, the polishing table rotates in a fixed direction, and the motion direction of the polishing head is, for example, linear movement or rotation in a fixed direction as the polishing table. The material of the metal layer comprises Cu, for example, and deionized water, cu grinding liquid and Cu protective liquid are added in the CMP process for grinding. Deionized water, cu slurry and Cu protective solution may be sprayed from the spray tube 30.
As shown in fig. 4, the surface of the semiconductor device is polished by a Chemical Mechanical Polishing (CMP) method to remove the metal layer of the dielectric layer surface above the substrate 10 and planarize the surface of the semiconductor device.
The Cu polishing liquid is, for example, an acidic polishing liquid having a pH of 2 to 5, and includes: aqueous medium, abrasive particles, oxidizing agent, acid and organic additive. The contents of the abrasive particles, the oxidizing agent, the acid and the organic additive are 1 to 30wt% relative to the total weight of the Cu polishing liquid; 1-10wt%;0.001-5wt%;0.001-1wt%, the balance being aqueous medium; wt% is weight percent. Illustratively, the abrasive particles are colloidal oxide particles, the oxidizing agent is at least one peroxy-containing material, the acid is at least one organic or inorganic acid or a mixture thereof, and the organic additive is a quaternary ammonium salt. The aqueous medium is deionized water or distilled water. Abrasive particles colloidal oxide particles are colloidal Silica (SIO) 2 ) Particles or colloidal alumina particles. The peroxy-containing substance is at least one selected from the group consisting of hydrogen peroxide, ammonium persulfate, peracetic acid, and periodic acid. The organic acid in the acid group is at least one component selected from benzotriazole, citric acid, citrate and ethylenediamine tetraacetic acid. The inorganic acid in the acid group is at least one member selected from the group consisting of sulfuric acid, nitric acid, hydrochloric acid and phosphoric acid. Cu slurry flow range: 100 ml/min-300 ml/min, the rotation speed range of the grinding pad is as follows: 20rpm to 30rpm.
The Cu protective solution prevents the oxidation and discoloration of the Cu metal layer. The Cu protective solution may include: a mixed solution of Benzotriazole (BTA), ethanol and soap lye; for example, 200-400 g of benzotriazole and 100-200 ml of ethanol are prepared into a solution, and then the solution is dissolved in 160-240 ml of soap solution with the mass concentration of 3-4% to prepare the Cu protective solution. Cu is substituted with H + in the Benzotriazole (BTA) molecule to form a thin film of a chain polymer oriented parallel to the copper surface, which has a certain degree of stability even at a high temperature, thereby suppressing oxidation of copper.
In this embodiment, the hard particles of the polishing pad have smaller particle size, and the ultra-thick Cu is efficiently thinned by using deionized water, a Cu polishing solution and a Cu protective solution, so as to realize the ultra-thick copper polishing process.
In summary, the present invention provides a method for manufacturing a semiconductor device, including: providing a substrate, wherein a dielectric layer is formed on the substrate; forming openings in the dielectric layer and the substrate, and filling the openings with a metal layer and covering the upper surface of the dielectric layer; and executing a CMP process to grind the part of the metal layer higher than the dielectric layer, wherein a grinding pad is in contact with the metal layer for grinding, hard particles are arranged on the surface of the grinding pad, and the particle size range of the hard particles is 6000-10000 of the mesh number of the international screen specification. In the CMP process, the grinding pad adopts hard particles with smaller particle size to grind the metal layer, thereby realizing the grinding of the ultra-thick metal layer (such as a copper metal layer).
The embodiments in the present description are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other. For the method disclosed by the embodiment, the description is relatively simple because the method corresponds to the device disclosed by the embodiment, and the relevant points can be referred to the description of the method part.
The above description is only for the purpose of describing preferred embodiments of the present invention and is not intended to limit the scope of the claims of the present invention, and any person skilled in the art may make possible variations and modifications of the technical solution of the present invention using the method and technical content disclosed above without departing from the spirit and scope of the present invention, and therefore, any simple modifications, equivalent changes and modifications of the above embodiments according to the technical essence of the present invention shall fall within the protection scope of the technical solution of the present invention.

Claims (10)

1. A method for fabricating a semiconductor device for polishing a metal layer having a thickness greater than 10 μm, comprising:
providing a substrate, wherein a dielectric layer is formed on the substrate; forming openings in the dielectric layer and the substrate, and filling the openings with a metal layer and covering the surface of the dielectric layer;
grinding the part of the metal layer higher than the dielectric layer, wherein the grinding pad is in contact with the metal layer for grinding, hard micro-particles are arranged on the surface of the grinding pad, and the particle size range of the hard micro-particles is 6000-10000 meshes of the international screen specification.
2. The method of manufacturing a semiconductor device according to claim 1, wherein the hard fine particles comprise diamond particles.
3. The method of claim 1, wherein the metal layer comprises Cu, and deionized water, a Cu polishing solution, and a Cu protective solution are added to the polishing process to polish the metal layer.
4. The method for manufacturing a semiconductor device according to claim 3, wherein the Cu polishing liquid is acidic and comprises: aqueous medium, abrasive particles, oxidizing agent, acids, and organic additives; the contents of the abrasive particles, the oxidizing agent, the acid, and the organic additive are each 1 to 30wt% with respect to the total weight of the Cu polishing liquid; 1-10wt%;0.001-5wt%;0.001 to 1wt%, the balance being the aqueous medium.
5. The method for manufacturing a semiconductor device according to claim 4, wherein the abrasive particles are colloidal silica particles or colloidal alumina particles, the oxidizing agent is at least one peroxy group-containing substance, the acid is at least one organic acid or inorganic acid or a mixture thereof, and the organic additive is a quaternary ammonium salt.
6. The method for manufacturing a semiconductor device according to claim 5, wherein the organic acid in the acid group is at least one member selected from the group consisting of benzotriazole, citric acid, a citrate, and ethylenediaminetetraacetic acid.
7. The method for manufacturing a semiconductor device according to claim 5, wherein the inorganic acid in the acid group is at least one member selected from the group consisting of sulfuric acid, nitric acid, hydrochloric acid, and phosphoric acid.
8. The method for manufacturing a semiconductor device according to claim 3, wherein the Cu protective solution comprises: benzotriazole, ethanol and soap solution.
9. The method for manufacturing a semiconductor device according to claim 3, wherein a flow rate range of the Cu polishing liquid is: 100 ml/min-300 ml/min; the rotating speed range of the grinding pad is as follows: 20rpm to 30rpm.
10. The method for manufacturing a semiconductor device according to claim 1, wherein a barrier layer is further formed on the side wall and the bottom surface of the opening, and the metal layer covers the barrier layer and fills the opening.
CN202210858675.4A 2022-07-20 2022-07-20 Method for manufacturing semiconductor device Active CN115179186B (en)

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Citations (10)

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Publication number Priority date Publication date Assignee Title
JP2004319759A (en) * 2003-04-16 2004-11-11 Hitachi Chem Co Ltd Polishing solution for metal and polishing method
JP2006165272A (en) * 2004-12-07 2006-06-22 Hitachi Chem Co Ltd Polishing solution and polishing method
JP2007103485A (en) * 2005-09-30 2007-04-19 Fujifilm Corp Polishing method, and polishing liquid used therefor
CN101463227A (en) * 2007-12-21 2009-06-24 安集微电子（上海）有限公司 Chemico-mechanical polishing solution for barrier layer
CN102615584A (en) * 2011-01-31 2012-08-01 中芯国际集成电路制造(上海)有限公司 Chemical mechanical grinding method
CN103681309A (en) * 2012-09-07 2014-03-26 中芯国际集成电路制造(上海)有限公司 Manufacturing method for ultra-thickness metal
CN204748298U (en) * 2014-12-08 2015-11-11 智胜科技股份有限公司 Polishing system and polishing pad assembly
CN110491790A (en) * 2018-05-09 2019-11-22 台湾积体电路制造股份有限公司 The manufacturing method of semiconductor device
CN112171513A (en) * 2020-09-29 2021-01-05 合肥晶合集成电路股份有限公司 Polishing pad processing method and chemical mechanical polishing equipment
TW202225352A (en) * 2020-12-30 2022-07-01 大陸商安集微電子科技(上海)股份有限公司 Chemical mechanical polishing slurry and method of using the same

Patent Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004319759A (en) * 2003-04-16 2004-11-11 Hitachi Chem Co Ltd Polishing solution for metal and polishing method
JP2006165272A (en) * 2004-12-07 2006-06-22 Hitachi Chem Co Ltd Polishing solution and polishing method
JP2007103485A (en) * 2005-09-30 2007-04-19 Fujifilm Corp Polishing method, and polishing liquid used therefor
CN101463227A (en) * 2007-12-21 2009-06-24 安集微电子（上海）有限公司 Chemico-mechanical polishing solution for barrier layer
CN102615584A (en) * 2011-01-31 2012-08-01 中芯国际集成电路制造(上海)有限公司 Chemical mechanical grinding method
CN103681309A (en) * 2012-09-07 2014-03-26 中芯国际集成电路制造(上海)有限公司 Manufacturing method for ultra-thickness metal
CN204748298U (en) * 2014-12-08 2015-11-11 智胜科技股份有限公司 Polishing system and polishing pad assembly
CN110491790A (en) * 2018-05-09 2019-11-22 台湾积体电路制造股份有限公司 The manufacturing method of semiconductor device
CN112171513A (en) * 2020-09-29 2021-01-05 合肥晶合集成电路股份有限公司 Polishing pad processing method and chemical mechanical polishing equipment
TW202225352A (en) * 2020-12-30 2022-07-01 大陸商安集微電子科技(上海)股份有限公司 Chemical mechanical polishing slurry and method of using the same

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