CN115173998A - Multiprocessor interactive communication method, system and storage medium - Google Patents
Multiprocessor interactive communication method, system and storage medium Download PDFInfo
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- CN115173998A CN115173998A CN202210790858.7A CN202210790858A CN115173998A CN 115173998 A CN115173998 A CN 115173998A CN 202210790858 A CN202210790858 A CN 202210790858A CN 115173998 A CN115173998 A CN 115173998A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
- H04L1/0041—Arrangements at the transmitter end
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
- G06F15/163—Interprocessor communication
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F2213/0042—Universal serial bus [USB]
Abstract
The application provides a multiprocessor interactive communication method, a multiprocessor interactive communication system and a storage medium, and relates to the technical field of data transmission. The method comprises the steps of obtaining data to be output according to a data output instruction; encoding data to be output by adopting a digital zero insertion encoding method based on reverse non-return-to-zero encoding to obtain encoded output data; the encoded output data is transmitted to a target processor of the plurality of processors via a universal serial bus. Therefore, the universal serial bus is adopted for data transmission, so that the data transmission is more stable and efficient, and the wiring cost is saved; the digital zero insertion coding method based on the reverse non-return-to-zero coding is adopted to code the data to be output, so that the data transmission is more accurate, and the data transmission efficiency is improved.
Description
Technical Field
The present invention relates to the field of data transmission technologies, and in particular, to a multiprocessor interactive communication method, system, and storage medium.
Background
At present, in an automatic control system, because the requirements of controllers are more and more complex, and the functions carried by a single controller module are more and more, in order to improve the processing capacity of the controllers, a plurality of embedded microprocessors are often adopted to cooperatively process the tasks of a control station, and in order to enable the system to operate more stably and accurately, interactive communication between the processors is necessary.
In the existing multiprocessor interaction mode, in a scenario where the communication output bandwidth between processors is greater than 100Mbps, the bandwidth of a UART (Universal Asynchronous receiver transmitter) is low, and is not suitable for a scenario where the data volume is large and the real-time performance is high. The ethernet signal speed is fast, but the number of ethernet MAC (Media Access Control) interfaces of a general processor is fixed and limited, and the controller often needs to communicate with the outside through the ethernet, so when a plurality of processors are in a communication scenario, the bandwidth of the UART is low, the ethernet has limitations, and the problem of low interaction efficiency exists.
Disclosure of Invention
The present invention provides a charging control method, apparatus, server, storage medium, and system to solve the problem of low interaction efficiency between processors in the prior art.
In order to achieve the above purpose, the technical solutions adopted in the embodiments of the present application are as follows:
in a first aspect, an embodiment of the present application provides a multiprocessor interactive communication method, which is applied to any processor in a multiprocessor interactive communication system, where multiple processors in the multiprocessor interactive communication system are connected by a universal serial bus, and the method includes:
acquiring data to be output according to the data output instruction;
coding the data to be output by adopting a digital zero insertion coding method based on reverse non-return-to-zero coding to obtain coded output data;
transmitting the encoded output data to a target processor of the plurality of processors via the universal serial bus.
Optionally, the encoding the data to be output by using a digital zero-insertion encoding method based on reverse non-return-to-zero encoding to obtain encoded output data includes:
carrying out 01 encoding on the data to be output to obtain the data to be output containing 01 codes;
if the number of continuous 1 in the data to be output containing the 01 codes is greater than or equal to the preset number, performing 0 interpolation operation on the data to be output containing the 01 codes to obtain the data to be output after 0 interpolation;
and adopting a reverse non-return-to-zero encoding method to perform encoding operation on the data to be output after 0 insertion, and acquiring the encoded output data.
Optionally, the method further comprises:
acquiring data to be input through the universal serial bus according to a data input instruction and a corresponding endpoint mode;
and decoding the data to be input by adopting a digital zero insertion decoding method based on reverse non-return-to-zero coding to finish data transmission.
Optionally, the processor comprises: a driving software module, a driver and a controller driver;
the transmitting the encoded output data to a target processor of the plurality of processors via the universal serial bus comprises:
sending a data output instruction and the encoded output data to the driver through the driving software module;
and calling the controller driver through the driver according to the data output instruction, and transmitting the coded output data to a target processor in the processors through the universal serial bus.
Optionally, the plurality of processors in the multiprocessor interactive communication system includes: a master processor, one or more slave processors.
Optionally, the multiprocessor interactive communication system includes: and the processors are connected based on Printed Circuit Board (PCB) wiring of universal serial bus signals in the coprocessing board card.
In a second aspect, an embodiment of the present application provides a multiprocessor interactive communication system, including: the system comprises a plurality of processors, a plurality of storage units and a plurality of communication units, wherein the processors are connected through a universal serial bus;
each of the processors is configured to perform the method according to any one of the first aspect.
Optionally, the plurality of processors in the multiprocessor interactive communication system includes: a master processor, one or more slave processors.
Optionally, the multiprocessor interactive communication system includes: and the processors are connected based on Printed Circuit Board (PCB) wiring of universal serial bus signals in the co-processing board card.
In a third aspect, an embodiment of the present application provides a computer-readable storage medium, where a computer program is stored on the computer-readable storage medium, and the computer program is executed by a processor to perform the steps of the multiprocessor interactive communication method according to any one of the first aspects.
Compared with the prior art, the method has the following beneficial effects:
the application provides a multiprocessor interactive communication method, a system and a storage medium, wherein the method acquires data to be output according to a data output instruction; encoding data to be output by adopting a digital zero insertion encoding method based on reverse non-return-to-zero encoding to obtain encoded output data; the encoded output data is transmitted to a target processor of the plurality of processors via a universal serial bus. Therefore, the universal serial bus is adopted for data transmission, so that the data transmission is more stable and efficient, and the wiring cost is saved; the digital zero insertion coding method based on the reverse non-return-to-zero coding is adopted to code the data to be output, so that the data transmission is more accurate, and the data transmission efficiency is improved.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required in the embodiments will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present invention and therefore should not be considered as limiting the scope, and those skilled in the art can also obtain other related drawings based on the drawings without inventive efforts.
Fig. 1 is a schematic structural diagram of a multiprocessor interactive communication system according to an embodiment of the present application;
FIG. 2 is a block diagram of a multi-processor interaction topology between modules according to an embodiment of the present disclosure;
fig. 3 is a schematic flowchart illustrating a multiprocessor interactive communication method according to an embodiment of the present application;
FIG. 4 is a logic diagram of a method based on inverse non-return-to-zero coding according to an embodiment of the present application;
fig. 5 is a schematic flowchart of a digital zero-insertion coding method based on reverse non-return-to-zero coding according to an embodiment of the present application;
fig. 6 is a flowchart illustrating a method for receiving data according to an embodiment of the present application;
fig. 7 is a schematic flowchart of a transmission method of output data according to an embodiment of the present application;
fig. 8 is a schematic diagram of a driver software module according to an embodiment of the present application;
fig. 9 is a schematic diagram of a processor according to an embodiment of the present application.
Icon: 100-processor, 200-universal serial bus, 300-first module, 400-second module, 801-acquisition sub-module, 802-coding sub-module, 803-transmission sub-module, 901-processing module, 902-storage medium.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are some embodiments of the present application, but not all embodiments. The components of the embodiments of the present application, generally described and illustrated in the figures herein, can be arranged and designed in a wide variety of different configurations.
Thus, the following detailed description of the embodiments of the present application, presented in the accompanying drawings, is not intended to limit the scope of the claimed application, but is merely representative of selected embodiments of the application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures.
Furthermore, the appearances of the terms "first," "second," and the like, if any, are used solely to distinguish one from another and are not to be construed as indicating or implying relative importance.
It should be noted that the features of the embodiments of the present invention may be combined with each other without conflict.
At present, in an automatic control system, because the requirements of controllers are more and more complex, and the functions carried by a single controller module are more and more, in order to improve the processing capacity of the controllers, a plurality of embedded microprocessors are often adopted to cooperatively process the tasks of a control station, and in order to enable the system to operate more stably and accurately, interactive communication between the processors is necessary. In order to enable interactive communication among processors to be more stable and efficient, the application provides a multiprocessor interactive communication method, a multiprocessor interactive communication system and a storage medium.
A multiprocessor interactive communication system provided in an embodiment of the present application is explained first as follows. Fig. 1 is a schematic structural diagram of a multiprocessor interactive communication system according to an embodiment of the present application.
As shown in fig. 1, the system includes: a plurality of processors 100, the plurality of processors 100 being connected to each other by a USB (Universal Serial Bus) 200; each processor 100 is configured to perform any of the methods provided by the embodiments of the present application.
The universal serial bus 200 connects the universal serial interface terminals of the processors 100 to connect the plurality of processors 100.
For example, the connection manner of the four processors 100 shown in fig. 1 is only an example, in the system, the number of the processors 100 may be multiple, the connection manner between the processors 100 may be that every two processors 100 are connected through the universal serial bus 200, or one processor 100 is connected with some processors 100 in other processors 100 through the universal serial bus 200, which may be set according to actual requirements, and is not limited herein. The topology among the processors 100 may be a star topology, a mesh topology, or a semi-mesh topology, in addition to the ring topology shown in fig. 1.
Illustratively, the processor 100 may be: a CPU (central processing unit), an FPGA (Field Programmable Gate Array), and a CPLD (Complex Programmable Logic Device). The universal serial bus 200 may be: USB2.0 or USB3.0, the transmission bandwidth of USB2.0 is 480Mbps, the transmission bandwidth of USB3.0 is 5.0Gbps, the application in the scene that the communication bandwidth between the processors 100 is more than 100Mbps is supported, and the data transmission efficiency is improved. The universal serial bus 200 can realize interactive communication without external devices such as an Ethernet PHY chip, a network transformer and the like, so that the material cost of a product is reduced, fault points are reduced, and the reliability of the product is improved.
In summary, in the embodiment, the system includes: the system comprises a plurality of processors, a plurality of storage units and a plurality of communication units, wherein the plurality of processors are connected through a universal serial bus; each processor is configured to perform any one of the methods provided by the embodiments of the present application. Therefore, the universal serial bus with larger communication bandwidth is adopted, the data transmission efficiency is improved, in addition, the universal serial bus can realize interactive communication without external devices such as an Ethernet PHY chip, a network transformer and the like, and the cost is saved.
Further, with continued reference to FIG. 1, a plurality of processors 100 in a multiprocessor interactive communication system includes: a master processor, one or more slave processors.
In a multiprocessor interactive communication system, when a plurality of processors 100 perform interactive communication, the processors 100 may be configured to transmit output data, and the processors 100 may also be configured to receive input data. When the processor 100 is used to transmit output data, the processor 100 is a main processor; when the processor 100 is configured to receive input data, the processor 100 is a slave processor.
Further, fig. 2 is a block diagram of a multi-processor interaction topology between modules according to an embodiment of the present application, as shown in fig. 2.
In the embodiment of the present application, one possible scenario is: the plurality of processors are located in a plurality of different modules, each module including at least one processor, each module for performing a corresponding processing task. Alternatively, the processors inside each module are connected by a universal serial bus, and the processors between each module are also connected by a universal serial bus. Illustratively, the plurality of modules are divided according to entity relationships, for example, modules are divided according to physical distances or according to physical locations. Taking the example shown in fig. 2, the multiprocessor interactive communication system includes two modules, namely a first module 300 and a second module 400.
For example, the Universal Serial Bus 200 for interconnection among The modules may be a USB OTG (Universal Serial Bus On-The-Go) port, the Universal Serial Bus 200 for interconnection inside The modules still adopts a USB port, and The interconnection among The modules may communicate based On The USB OTG port. The work right bits between the modules are divided into work and standby, so when the work right bits are switched, the USB ports need to be matched again. Taking the processor a as an example, when the first module 300 is a working card and the second module 400 is a standby card, the USB OTG port in the processor a of the first module 300 is configured as a USB master port to control a USB bus, and the USB OTG port in the processor C of the second module 400 is configured as a USB slave port. The second module 400 is a working card, and when the first module 300 is a standby card, the USB OTG port in the processor C in the second module 400 is configured as a USB master port to control a USB bus, and the USB OTG port in the processor a in the first module 300 is configured as a USB slave port.
The connection relationship of the multiple processors in the multi-processor interactive communication system is further explained on the basis of the embodiments provided in fig. 1-2.
Optionally, with continued reference to fig. 1, the multiprocessor interactive communication system includes: the processors 100 are connected by printed circuit board wiring of the usb 200 signal inside the co-processing board.
By setting a co-processing Board, the processors 100 are embedded in the co-processing Board, and the co-processing Board connects the processors 100 by using a Printed Circuit Board (PCB) wiring. The printed circuit board transmits the universal serial bus 200 signal, so that the universal serial bus 200 signal transmission among the processors 100 is realized, the hardware circuit for transmitting the universal serial bus 200 signal is more stable, and the data transmission is facilitated.
On the basis of the multiprocessor interactive communication system shown in fig. 1-2, the embodiment of the application also provides a multiprocessor interactive communication method. Fig. 3 is a flowchart illustrating a multiprocessor interactive communication method according to an embodiment of the present application. As shown in fig. 3, the method is applied to any processor in a multiprocessor interactive communication system, wherein a plurality of processors in the multiprocessor interactive communication system are connected through a universal serial bus, and the method comprises:
and S101, acquiring data to be output according to the data output instruction.
For example, after receiving a data output instruction sent by a target processor, the target processor may further obtain data to be output according to the received data output instruction, where the target processor is a processor for obtaining the data to be output, and the target processor may also be any processor in the multiprocessor interactive communication system. Alternatively, the data to be output may be acquired at a preset transmission cycle. Illustratively, the data to be output may be control data, query data, and the like in the control system.
S102, encoding data to be output by adopting a digital zero insertion encoding method based on reverse non-return-to-zero encoding, and acquiring encoded output data.
For example, fig. 4 is a logic diagram based on reverse non-return-to-zero coding according to an embodiment of the present application. As shown in fig. 4, the universal serial bus is data-encoded using NRZI (Non-Return-to-Zero) encoded logic. In the figure, data is original Data, NRZI is encoded Data, level inversion represents logic 0, and level invariance represents logic 1. That is, in the process of data transmission, the level of the data needs to be turned over at 0, and the level of the data at 1 is unchanged. Since the logic 0 can cause the USB level to be inverted, when the data has a length of 0, the receiving end can adjust the synchronization frequency according to the inverted signal while receiving the data.
However, errors still exist in the receiving end and the transmitting end of the universal serial bus during the actual data transmission process. Particularly, in a severe environment, there is a possibility that the timing may be disturbed, which may cause communication abnormality and loss of transmission data. Thus, a digital zero-insertion coding method based on inverse non-return-to-zero coding can be preset. And performing forced zero insertion coding on the data to be output by adopting a digital zero insertion coding method based on reverse non-return-to-zero coding to obtain coded output data. Therefore, the output data after being coded can overcome time sequence disturbance, so that the data transmission is more accurate, and the data transmission efficiency is improved.
And S103, transmitting the coded output data to a target processor in the plurality of processors through the universal serial bus.
And determining a target processor in the plurality of processors according to the data output instruction, and transmitting the encoded output data to the target processor through the universal serial bus. Illustratively, universal serial bus based communication between multiprocessing relies on interrupt communication or polling communication.
The universal serial bus is adopted for data transmission, so that the data transmission is more stable and efficient, the universal serial bus is concise in wiring, and the wiring cost is saved.
In summary, in the embodiment, the data to be output is obtained according to the data output instruction; encoding data to be output by adopting a digital zero insertion encoding method based on reverse non-return-to-zero encoding to obtain encoded output data; the encoded output data is transmitted to a target processor of the plurality of processors via a universal serial bus. Therefore, the universal serial bus is adopted for data transmission, so that the data transmission is more stable and efficient, and the wiring cost is saved; the digital zero insertion coding method based on the reverse non-return-to-zero coding is adopted to code the data to be output, so that the data transmission is more accurate, and the data transmission efficiency is improved.
Fig. 5 is a schematic flowchart of a digital zero-insertion coding method based on reverse non-return-to-zero coding according to an embodiment of the present application. As shown in fig. 5, the encoding of the data to be output by using the digital zero-insertion encoding method based on the reverse non-return-to-zero encoding in S102 to obtain the encoded output data includes:
s201, encoding 01 for data to be output to obtain the data to be output containing 01 codes.
Illustratively, binary system is adopted, 01 encoding is performed on data to be output, and the data to be output containing 01 codes is obtained. The data to be output is expressed in the form of 0 and 1, so that the data is convenient to transmit in a digital circuit and is identified.
S202, if the number of continuous 1 in the data to be output containing the 01 codes is larger than or equal to the preset number, performing 0 interpolation operation on the data to be output containing the 01 codes to obtain the data to be output after 0 interpolation.
A predetermined number of consecutive 1's is predetermined, for example, two 1's are consecutive if the predetermined number is 2, and three 1's are consecutive if the predetermined number is 3. When it is detected that the number of consecutive 1's in the data to be output including the 01 code is greater than or equal to the preset number, timing disturbance may occur, which may cause communication abnormality, loss of transmission data, and the like. Therefore, 0 interpolation can be performed between the bits of consecutive 1 in the data to be output, and the data to be output after 0 interpolation is obtained. The number of the data to be output after 0 insertion is not larger than or equal to the preset number of the continuous 1, so that data loss is avoided.
Illustratively, the data before 0 insertion is: 01111001, if the predetermined number is 3, the data after 0 insertion is: 011011001.
and S203, coding the data to be output after the 0 insertion by adopting a reverse non-return-to-zero coding method, and acquiring coded output data.
And adopting a reverse non-return-to-zero coding method to perform coding operation on the data to be output after 0 insertion, and acquiring coded output data. The coded output data is easy to identify, the conditions that the data transmission is unstable and the like caused by the condition of continuous 1 in the data are avoided, and the accuracy of the data transmission is improved.
In summary, in the embodiment, the data to be output including 01 codes is obtained by encoding the data to be output by 01; if the number of continuous 1 in the data to be output containing the 01 code is greater than or equal to the preset number, performing 0 interpolation operation on the data to be output containing the 01 code to obtain the data to be output after 0 interpolation; and adopting a reverse non-return-to-zero coding method to perform coding operation on the data to be output after 0 insertion, and acquiring coded output data. Therefore, the conditions of unstable data transmission and the like caused by the condition of continuous 1 in the data are avoided, and the accuracy of data transmission is improved.
Fig. 6 is a flowchart illustrating a method for receiving data according to an embodiment of the present application. As shown in fig. 6, the method further includes:
s301, acquiring data to be input through the universal serial bus according to the data input instruction and the corresponding endpoint mode.
In the present application, in addition to the method of processing output data transmitted by a processor provided above, there are also cases where a processor receives input data.
When a data input command and a corresponding endpoint mode are received, data to be input needs to be received. At this time, the data to be input is sent to the universal serial bus by the processor sending the data to be input, and the data to be input can be obtained through the universal serial bus. The endpoint mode is an endpoint mode of the universal serial bus, that is, which port in the universal serial bus is a sending end and which port is an endpoint of a receiving end is carried in the endpoint mode, and the endpoint mode of the universal serial bus can be adjusted according to the requirement of data transmission.
S302, decoding the data to be input by adopting a digit zero insertion decoding method based on reverse non-return-to-zero coding to finish data transmission.
In the above embodiments, the transmission data is encoded by a digital zero-insertion encoding method based on reverse non-return-to-zero encoding. Therefore, after receiving the data to be input, the digital zero insertion decoding method based on the reverse non-return-to-zero encoding needs to be adopted to perform decoding operation on the data to be input, so as to complete data transmission. The specific digital zero-insertion decoding method based on the reverse non-return-to-zero coding is just opposite to the coding method thereof, and is not described herein again.
In summary, in the embodiment, the data to be input is acquired through the usb according to the data input instruction and the corresponding endpoint mode; and (3) decoding the data to be input by adopting a digital zero insertion decoding method based on reverse non-return-to-zero coding to finish data transmission. Therefore, the data is received by adopting the universal serial bus, and the data to be input is decoded by adopting a digit zero insertion decoding method based on reverse non-return-to-zero coding, so that the data transmission is more accurate.
Fig. 7 is a flowchart illustrating a method for transmitting output data according to an embodiment of the present disclosure. As shown in fig. 7, the processor includes: a driving software module, a driver and a controller driver.
Transmitting the encoded output data to a target processor of the plurality of processors via the universal serial bus in S103, including:
s401, sending a data output instruction and the coded output data to a driver through a driving software module.
In the processor for sending the output data, after the driving software module receives the data output instruction and obtains the encoded output data, the data output instruction and the encoded output data are sent to the driver, and the driver performs subsequent operation.
S402, calling a controller driver through the driver according to the data output instruction, and transmitting the coded output data to a target processor in the plurality of processors through the universal serial bus.
The driver receives the data output command and the encoded output data. Firstly, determining that data output operation is required according to a data output instruction, determining a target processor in the data output instruction, and calling a controller driver. And secondly, sending the coded output data and the corresponding target processor to a controller driver, and transmitting the coded output data to the target processor in the plurality of processors by the controller driver through a universal serial bus. Therefore, the data transmission efficiency is improved through the universal serial bus.
In summary, in the embodiment, the driving software module sends the data output instruction and the encoded output data to the driver; and calling the controller driver through the driver according to the data output instruction, and transmitting the coded output data to a target processor in the plurality of processors through the universal serial bus. Therefore, the data transmission efficiency is improved through the universal serial bus.
Further, the plurality of processors in the multiprocessor interactive communication system includes: a master processor, one or more slave processors. In a multiprocessor interactive communication system, when a plurality of processors perform interactive communication, each processor may be configured to transmit output data and each processor may be configured to receive input data. When the processor is used for transmitting output data, the processor is a main processor; when a processor is used to receive input data, the processor is a slave processor.
Further, the multiprocessor interactive communication system includes: and the multiple processors are connected based on Printed Circuit Board (PCB) wiring of universal serial bus signals in the cooperative processing board card. Through setting up the coprocessing integrated circuit board, adopt printed circuit board PCB wiring transmission universal serial bus signal for the hardware circuit of universal serial bus signal transmission is more stable, is convenient for data transmission.
The following describes a driver software module, a device, a storage medium, and the like provided by the present application for execution, and the specific implementation process and technical effects thereof are referred to above, and are not described in detail below.
Fig. 8 is a schematic diagram of a driver software module according to an embodiment of the present application, where, as shown in fig. 8, the driver software module is applied to any one processor in a multiprocessor interactive communication system, and multiple processors in the multiprocessor interactive communication system are connected by a universal serial bus, and the driver software module may include:
the obtaining sub-module 801 is configured to obtain data to be output according to the data output instruction.
The encoding submodule 802 is further configured to encode the data to be output by using a digital zero insertion encoding method based on reverse non-return-to-zero encoding, and obtain encoded output data;
the transmission sub-module 803 is configured to transmit the encoded output data to a target processor of the plurality of processors via a universal serial bus.
Further, the encoding submodule 802 is configured to encode 01 for data to be output, so as to obtain data to be output including 01 codes; if the number of continuous 1 in the data to be output containing the 01 codes is larger than or equal to the preset number, performing 0 interpolation operation on the data to be output containing the 01 codes to obtain the data to be output after 0 interpolation; and adopting a reverse non-return-to-zero encoding method to perform encoding operation on the data to be output after 0 insertion, and acquiring the encoded output data.
Further, the encoding sub-module 802 is specifically configured to obtain data to be input through a universal serial bus according to the data input instruction and the corresponding endpoint mode; and performing decoding operation on the data to be input by adopting a digital zero insertion decoding method based on reverse non-return-to-zero coding to finish data transmission.
Further, the transmission sub-module 803 includes: a driving software module, a driver and a controller driver;
the transmitting encoded output data to a target processor of a plurality of processors via a universal serial bus comprises: sending a data output instruction and the encoded output data to a driver through a driving software module; the controller driver is called by the driver according to the data output instruction, and the coded output data is transmitted to a target processor in the plurality of processors through the universal serial bus.
The above modules may be one or more integrated circuits configured to implement the above methods, such as: one or more Application Specific Integrated Circuits (ASICs), or one or more microprocessors (DSPs), or one or more Field Programmable Gate Arrays (FPGAs), among others. For another example, when one of the above modules is implemented in the form of a Processing element scheduler code, the Processing element may be a general-purpose processor, such as a Central Processing Unit (CPU) or other processor capable of calling program code. As another example, these modules may be integrated together and implemented in the form of a system-on-a-chip (SOC).
Fig. 9 is a schematic diagram of a processor according to an embodiment of the present application, where the processor may be a device with a computing processing function.
The processor includes: a processing module 901 and a storage medium 902. The processing module 901 and the storage medium 902 are connected by a bus.
The storage medium 902 is used for storing programs, and the processing module 901 calls the programs stored in the storage medium 902 to execute the above-mentioned method embodiments. The specific implementation and technical effects are similar, and are not described herein again.
Optionally, the present invention also provides a computer-readable storage medium comprising a program which, when executed by a processor, is adapted to perform the above-described method embodiments.
In the embodiments provided in the present invention, it should be understood that the disclosed apparatus and method may be implemented in other ways. For example, the above-described apparatus embodiments are merely illustrative, and for example, the division of the units is only one type of logical functional division, and other divisions may be realized in practice, for example, multiple units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or units, and may be in an electrical, mechanical or other form.
The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.
In addition, functional units in the embodiments of the present invention may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit. The integrated unit can be realized in a form of hardware, or in a form of hardware plus a software functional unit.
The integrated unit implemented in the form of a software functional unit may be stored in a computer readable storage medium. The software functional unit is stored in a storage medium and includes several instructions to enable a computer device (which may be a personal computer, a server, or a network device) or a processor (processor) to execute some steps of the methods according to the embodiments of the present invention. And the aforementioned storage medium includes: a U disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk or an optical disk, and other various media capable of storing program codes.
The above description is only for the specific embodiments of the present application, but the scope of the present application is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present application, and shall be covered by the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.
Claims (10)
1. A multiprocessor interactive communication method applied to any one processor in a multiprocessor interactive communication system, wherein a plurality of processors in the multiprocessor interactive communication system are connected through a universal serial bus, the method comprising:
acquiring data to be output according to the data output instruction;
coding the data to be output by adopting a digital zero insertion coding method based on reverse non-return-to-zero coding to obtain coded output data;
transmitting the encoded output data to a target processor of the plurality of processors via the universal serial bus.
2. The method according to claim 1, wherein the encoding the data to be output by using a digital zero-insertion coding method based on inverse non-return-to-zero coding to obtain encoded output data comprises:
carrying out 01 encoding on the data to be output to obtain the data to be output containing 01 codes;
if the number of continuous 1 in the data to be output containing the 01 codes is greater than or equal to the preset number, performing 0 interpolation operation on the data to be output containing the 01 codes to obtain the data to be output after 0 interpolation;
and adopting a reverse non-return-to-zero coding method to carry out coding operation on the data to be output after 0 insertion, and acquiring the coded output data.
3. The method of claim 1, further comprising:
acquiring data to be input through the universal serial bus according to a data input instruction and a corresponding endpoint mode;
and decoding the data to be input by adopting a digital zero insertion decoding method based on reverse non-return-to-zero coding to finish data transmission.
4. The method of claim 3, wherein the processor comprises: a driving software module, a driver and a controller driver;
the transmitting the encoded output data to a target processor of the plurality of processors via the universal serial bus comprises:
sending a data output instruction and the coded output data to the driver through the driving software module;
and calling the controller driver through the driver according to the data output instruction, and transmitting the coded output data to a target processor in the processors through the universal serial bus.
5. The method of any of claims 1-4, wherein the plurality of processors in the multiprocessor interactive communication system comprise: a master processor, one or more slave processors.
6. The method of claim 5, wherein the multiprocessor interactive communication system comprises: and the processors are connected based on Printed Circuit Board (PCB) wiring of universal serial bus signals in the coprocessing board card.
7. A multiprocessor interactive communication system, comprising: the system comprises a plurality of processors, a plurality of storage units and a plurality of communication units, wherein the processors are connected through a universal serial bus;
each of the processors is configured to perform the method of any one of claims 1-6.
8. The system of claim 7, wherein the plurality of processors in the multiprocessor interactive communication system comprise: a master processor, one or more slave processors.
9. The system of claim 8, wherein the multiprocessor interactive communication system comprises: and the processors are connected based on Printed Circuit Board (PCB) wiring of universal serial bus signals in the coprocessing board card.
10. A computer-readable storage medium, characterized in that a computer program is stored on the computer-readable storage medium, which computer program, when being executed by a processor, performs the steps of the multiprocessor interactive communication method as claimed in any one of claims 1 to 6.
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