CN115172424A - Array substrate, display panel and display device - Google Patents

Array substrate, display panel and display device Download PDF

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Publication number
CN115172424A
CN115172424A CN202210766798.5A CN202210766798A CN115172424A CN 115172424 A CN115172424 A CN 115172424A CN 202210766798 A CN202210766798 A CN 202210766798A CN 115172424 A CN115172424 A CN 115172424A
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sub
signal line
gap
array substrate
bridge
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CN115172424B (en
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盛晨航
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Shanghai Tianma Microelectronics Co Ltd
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Shanghai Tianma Microelectronics Co Ltd
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Nonlinear Science (AREA)
  • Mathematical Physics (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • General Physics & Mathematics (AREA)
  • Optics & Photonics (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

The embodiment of the application provides an array substrate, a display panel and a display device. The array substrate comprises a first sub-signal line, a second sub-signal line, a third sub-signal line and a fourth sub-signal line, wherein the first sub-signal line and the second sub-signal line extend along a first direction; and the first direction intersects the second direction; a first gap is formed between the first sub-signal line and the second sub-signal line which are adjacently arranged along the first direction; a second gap is formed between the third sub-signal line and the fourth sub-signal line which are adjacently arranged along the second direction; wherein at least a portion of the first gap overlaps the second gap; in the first gap and the second gap which are overlapped, at least two of the first sub-signal line and the second sub-signal line on two sides of the first gap and the third sub-signal line and the fourth sub-signal line on two sides of the second gap are electrically connected and at least two of the first sub-signal line and the second sub-signal line are electrically insulated; the display device can solve the problem that the display device caused by the reflection difference of the signal line has visual effect difference, so that the display device realizes visual effect uniformity.

Description

Array substrate, display panel and display device
[ technical field ] A
The present application relates to the field of display technologies, and in particular, to an array substrate, a display panel and a display device.
[ background of the invention ]
With the development of technology, people are pursuing to realize frameless display or narrow-frame display. In the related art, a narrow bezel display device in which a display panel is provided in a rounded rectangle has been realized. However, in practical production and life, it is found that when the display device works, the display screen has phenomena of visual effect difference and display unevenness, and the display effect of the display device is affected.
[ application contents ]
In view of the foregoing, embodiments of the present application provide an array substrate, a display panel and a display device.
In a first aspect, the present application provides an array substrate, including:
a first sub-signal line and a second sub-signal line extending in a first direction; a first gap is formed between the first sub-signal line and the second sub-signal line which are adjacently arranged along the first direction;
a third sub-signal line and a fourth sub-signal line extending in a second direction; a second gap is formed between the third sub-signal line and the fourth sub-signal line which are adjacently arranged along the second direction; the first direction intersects the second direction;
wherein at least a portion of the first gap overlaps the second gap; in the first gap and the second gap which are overlapped, at least two of the first sub-signal line and the second sub-signal line on two sides of the first gap and the third sub-signal line and the fourth sub-signal line on two sides of the second gap are electrically connected and at least two of the first sub-signal line and the second sub-signal line are electrically insulated.
In one implementation form of the first aspect, the first gap and the second gap form a first pattern, the first pattern is symmetric about a first axis of symmetry and the first pattern is symmetric about a second axis of symmetry; the first axis of symmetry is parallel to the first direction and the second axis of symmetry is parallel to the second direction.
In one implementation manner of the first aspect, the array substrate further includes a first bridge;
the first sub-signal line and the third sub-signal line are electrically connected through the first bridge.
In one implementation manner of the first aspect, the array substrate further includes a first bridge;
the first sub-signal line and the second sub-signal line are electrically connected through the first bridge.
In an implementation manner of the first aspect, the film layer where the first bridge is located on a side, away from the light emitting surface, of the film layer where the first sub-signal line is located.
In one implementation manner of the first aspect, the array substrate further includes a virtual bridge;
and the virtual bridge is arranged between the electrically-connected two of the first sub-signal line, the second sub-signal line, the third sub-signal line and the fourth sub-signal line, and the virtual bridge is arranged between the electrically-connected two of the first sub-signal line, the second sub-signal line, the third sub-signal line and the fourth sub-signal line.
In one implementation manner of the first aspect, in the first sub-signal line and the second sub-signal line on both sides of the first gap, a shape of an end portion of the first sub-signal line close to the first gap is the same as a shape of an end portion of the second sub-signal line close to the first gap;
in the third sub-signal line and the fourth sub-signal line on both sides of the second gap, a shape of an end portion of the third sub-signal line close to the second gap is the same as a shape of an end portion of the fourth sub-signal line close to the second gap.
In one implementation manner of the first aspect, there is an overlap around the first gap and the second gap, and a shape of an end portion of the first sub-signal line close to the first gap, a shape of an end portion of the second sub-signal line close to the first gap, a shape of an end portion of the third sub-signal line close to the second gap, and a shape of an end portion of the fourth sub-signal line close to the second gap are the same.
In one implementation form of the first aspect, an end of the first sub-signal line near the first gap is one of rectangular and fan-shaped;
the end part of the second sub-signal line close to the first gap is one of a rectangle and a sector;
the end part of the third sub-signal line close to the second gap is one of a rectangle and a sector;
the end of the fourth sub-signal line close to the second gap is one of rectangular and fan-shaped.
In one implementation manner of the first aspect, in an end portion of the first sub-signal line close to the first gap, an edge far away from the first gap is arc-shaped;
the edge of the second sub-signal wire, which is far away from the first gap, in the end part of the second sub-signal wire, which is close to the first gap, is in an arc shape;
the edge of the third sub-signal wire, which is far away from the second gap, in the end part of the third sub-signal wire, which is close to the second gap, is in an arc shape;
in the end part of the fourth sub-signal wire close to the second gap, the edge far away from the second gap is in an arc shape.
In a second aspect, the present application provides a display panel including the array substrate provided in the first aspect.
In a third aspect, the present application provides a display device comprising the display panel as provided in the second aspect.
The array substrate, the display panel and the display device provided by the embodiment of the application have the advantages that the sub-signal lines are symmetrically arranged, the cross bridges are arranged on different layers of the sub-signal lines to electrically connect or electrically insulate the sub-signal lines, the problem that the visual effect difference of the display device caused by the reflection difference of the intersection of the signal lines can be solved, the visual effect uniformity of the display device is realized in the first direction and the second direction, and the display quality of the display device is improved.
[ description of the drawings ]
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings needed to be used in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
Fig. 1 is a schematic projection diagram of a signal line in an array substrate according to an embodiment of the present invention;
FIG. 2 is a schematic plan view of a signal line in an array substrate according to the prior art;
FIG. 3 is an enlarged partial view of the AA1 region of FIG. 2;
fig. 4 is a schematic plan view illustrating signal lines in an array substrate according to an embodiment of the present invention;
fig. 5 is a schematic projection diagram of a signal line in an array substrate according to an embodiment of the present invention;
fig. 6 is a schematic projection diagram of a signal line in an array substrate according to an embodiment of the present invention;
FIG. 7 is a partial cross-sectional view of the signal lines along MN in the array substrate of FIG. 6;
fig. 8 is a schematic projection diagram of a signal line in an array substrate according to an embodiment of the present invention;
fig. 9 is a schematic projection diagram of a signal line in an array substrate according to an embodiment of the present invention;
FIG. 10 is a partial cross-sectional view of a display panel according to an embodiment of the present invention;
fig. 11 is a schematic diagram of a display device according to an embodiment of the present invention.
[ detailed description ] A
For better understanding of the technical solutions of the present application, the following detailed descriptions of the embodiments of the present application are provided with reference to the accompanying drawings.
It should be understood that the embodiments described are only a few embodiments of the present application, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
The terminology used in the embodiments of the present application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used in the examples of this application and the appended claims, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.
It should be understood that the term "and/or" as used herein is merely one type of association that describes an associated object, meaning that three relationships may exist, e.g., a and/or B may mean: a exists alone, A and B exist simultaneously, and B exists alone. In addition, the character "/" herein generally indicates that the former and latter related objects are in an "or" relationship.
In the description herein, it is to be understood that the terms "substantially", "approximately", "about", "substantially", and the like, as used in the claims and the examples herein, are intended to be generally accepted as not being precise, within the scope of reasonable process operation or tolerance.
It should be understood that although the terms first, second, third, etc. may be used to describe directions, sub-signal lines, gaps, etc. in the embodiments of the present application, the directions, etc. should not be limited to these terms. These terms are only used to distinguish one direction from another. For example, a first direction may also be referred to as a second direction, and similarly, a second direction may also be referred to as a first direction, without departing from the scope of embodiments of the present application.
The applicant provides a solution to the problems of the prior art through intensive research.
Fig. 1 is a schematic projection diagram of a signal line in an array substrate according to an embodiment of the present invention.
As shown in fig. 1, the array substrate according to the embodiment of the present invention includes a first sub-signal line 01 and a second sub-signal line 02 extending along a first direction X, and a third sub-signal line 03 and a fourth sub-signal line 04 extending along a second direction Y.
A first gap 11 is included between the first sub-signal line 01 and the second sub-signal line 02 which are adjacently arranged along the first direction X; a second gap 12 is included between the third sub-signal line 03 and the fourth sub-signal line 04 which are adjacently arranged along the second direction Y; and the first direction X intersects the second direction Y.
Wherein at least part of the first gap 11 overlaps the second gap 12. In the first and second gaps 11 and 12 that overlap, at least two of the first and second sub-signal lines 01 and 02 on both sides of the first gap 11 and the third and fourth sub-signal lines 03 and 04 on both sides of the second gap 12 are electrically connected and at least two are electrically insulated. That is, in the present embodiment, only two of the four sub-signal lines are electrically connected, and the other two sub-signal lines are electrically insulated from each other and also electrically insulated from the electrically connected two sub-signal lines; or, in the four sub-signal lines, the three sub-signal lines are electrically connected with each other, and the other sub-signal line is electrically insulated from the electrically connected three sub-signal lines.
Fig. 2 is a schematic plan view illustrating a signal line in an array substrate according to the related art, and fig. 3 is an enlarged view illustrating an AA1 region in fig. 2.
As shown in fig. 2 and 3, an application scenario of the inventive concept of the present application is an array substrate including a chamfer. As shown in fig. 2, the array substrate includes a display area AA and a non-display area NA surrounding the display area AA, and four corners of the array substrate are chamfered.
The display area AA includes data lines DL extending in a column direction, and the data lines DL need to extend into a bonding area NA in the non-display area NA. When the data lines DL at the chamfered position (i.e., the data lines close to the left and right sides of the display panel in fig. 2) need to be led to the bonding area NA, if the wires are wound from the non-display area NA at the chamfered position, the width of the non-display area NA at the chamfered position is increased, which is not favorable for realizing a narrow frame. Therefore, as shown in fig. 2, the data line DL at the chamfered position can be led to the binding region NA1 after being led to the upper side of the binding region NA1 through the connecting lead CL arranged in the display region AA, and thus the design does not need to perform a winding design on the non-display region NA at the chamfered position, which is beneficial to realizing a narrow frame.
The introduction of the connecting lead line CL in the display area AA causes different visual effects in different areas and causes different loads on different data lines DL and other signal lines. In order to solve this problem, a typical design is shown in fig. 3, that is, a plurality of dummy signal lines DL 'are further introduced into the display area AA, and the dummy signal lines DL' are distributed uniformly and extend in a direction corresponding to the connecting leads CL.
However, the inventors of the present invention conducted analysis and tests on the array substrate shown in fig. 2 and 3 and the display panel including the same, and found that the design of the dummy signal line DL 'causes a visual effect difference between the dummy signal line DL' and the signal line having a longer actual length. The dummy signal line DL 'is designed to avoid the longer signal line, so that gaps exist between the dummy signal line DL' and the longer signal line, and the gaps are not uniformly distributed, thereby causing visual effect difference.
In the embodiment of the present application, of the first sub-signal line 01 and the second sub-signal line 02 on both sides of the first gap 11 and the third sub-signal line 03 and the fourth sub-signal line 04 on both sides of the second gap 12, the two electrically connected sub-signal lines are configured as a part of the connection lead DL ', or the three electrically connected sub-signal lines are configured as the data line DL and the connection lead DL' electrically connected thereto. And among the first sub-signal line 01 and the second sub-signal line 02 on both sides of the first gap 11 and the third sub-signal line 03 and the fourth sub-signal line 04 on both sides of the second gap 12, the sub-signal line electrically insulated from the other sub-signal lines is a dummy signal line DL'.
Based on the above problems and the analysis of the cause of the above problems, the present application provides a new array substrate to solve the above problems.
In the present embodiment, as shown in fig. 1, both sides of the first gap 11 are provided with a partial region of the second gap 12, that is, a portion including the first gap 11 between the first sub-signal line 01 and the second gap 12, and a portion including the first gap 11 between the second sub-signal line 02 and the second gap 12. A gap is formed between the straight line where the third sub-signal line 03 and the fourth sub-signal line 04 are located and the first sub-signal line 01, and a gap is also formed between the straight line and the second sub-signal line 02, so that the uniformity of the visual effect in the first direction X can be achieved.
In the present embodiment, as shown in fig. 1, both sides of the second gap 12 are provided with a partial region of the first gap 11, that is, a portion including the second gap 12 between the third sub-signal line 03 and the first gap 11, and a portion including the second gap 12 between the fourth sub-signal line 04 and the first gap 11. A gap is formed between the straight line where the first sub-signal line 01 and the second sub-signal line 02 are located and the third sub-signal line 03, and a gap is formed between the straight line and the fourth sub-signal line 04, so that the visual effect uniformity can be realized in the second direction Y.
Alternatively, the first sub-signal line 01 may be located on the same conductive film layer as the second sub-signal line 02, and the third sub-signal line 03 may be located on the same conductive film layer as the fourth sub-signal line 04.
Furthermore, the first sub-signal line 01, the second sub-signal line 02, the third sub-signal line 03 and the fourth sub-signal line 04 are all located on the same conductive film layer.
In the technical scheme, the problem of visual effect difference of the display device caused by reflection difference of the signal lines is solved by arranging the sub-signal lines as shown in fig. 1, so that the visual effect uniformity of the display device is realized in the first direction X and the second direction Y, and the display quality of the display device is improved.
Fig. 4 is a schematic plan view of a signal line in an array substrate according to an embodiment of the present invention.
As shown in fig. 4, a first gap 11 between the first sub-signal line 01 and the second sub-signal line 02 and a second gap 12 between the third sub-signal line 03 and the fourth sub-signal line 04 constitute a first pattern 13.
The first pattern 13 is symmetrical about a first axis of symmetry L1 and the first pattern 13 is symmetrical about a second axis of symmetry L2; the first axis of symmetry L1 is parallel to the first direction X, and the second axis of symmetry L2 is parallel to the second direction Y. It will be appreciated that the first pattern 13 is an axisymmetric pattern.
In the technical scheme, the first gap 11 and the second gap are symmetrically arranged, so that the problem of visual effect difference of the display device caused by reflection difference at the intersection of the signal lines can be solved, the visual effect uniformity of the display device is realized in the first direction X and the second direction Y, and the display quality of the display device is improved.
As shown in fig. 1, the array substrate 101 provided by the embodiment of the present invention further includes a first bridge 14; the first sub-signal line 01 and the third sub-signal line 03 are electrically connected by a first bridge 14. The first bridge 14 is disposed on a different layer from the first sub-signal line 01 and the third sub-signal line 03. The electrically connected first and third sub-signal lines 01 and 03 may be portions of the connection lead DL' that extend in different directions, respectively.
In an embodiment of the present application, the first bridge 14 electrically connecting the first sub-signal line 01 and the third sub-signal line 03 is disposed on different layers, so that the first bridge 14 is prevented from affecting the visual effects of the films on which the first sub-signal line 01 and the third sub-signal line 03 are disposed at different viewing angles.
Fig. 5 is a schematic projection diagram of a signal line in an array substrate according to an embodiment of the present invention.
As shown in fig. 5, the array substrate 101 provided by the embodiment of the present invention further includes a first bridge 14; the first sub-signal line 01 and the second sub-signal line 02 are electrically connected by a first bridge 14. The first bridge 14 is disposed on a different layer from the first sub-signal line 01 and the second sub-signal line 02. The electrically connected first and second sub-signal lines 01 and 02 may be different portions of the connection lead DL' extending in the same direction, respectively.
In an embodiment of the present application, the first bridge 14 electrically connecting the first sub-signal line 01 and the third sub-signal line 03 is disposed on different layers, so that the first bridge 14 is prevented from affecting the visual effects of the film layers on which the first sub-signal line 01 and the third sub-signal line 03 are disposed at different viewing angles.
Fig. 6 is a schematic projection diagram of a signal line in an array substrate according to an embodiment of the present invention.
As shown in fig. 6, the array substrate 101 provided in the embodiment of the present invention further includes a virtual bridge 15, where the virtual bridge 15 is disposed on the same layer as the first bridge 14, and the virtual bridge 15 is not electrically connected to the signal line. Around the first gap 11 and the second gap 12 which overlap with each other, a first bridge 14 is provided between electrically connected ones of the first sub-signal line 01, the second sub-signal line 02, the third sub-signal line 03, and the fourth sub-signal line 04, and a dummy bridge 15 is provided between electrically insulated ones.
In the present embodiment, specifically described with reference to fig. 6, there are the first gap 11 and the second gap 12 which are overlapped, the first sub-signal line 01 and the third sub-signal line 03 are electrically connected, and then a first bridge 14 is disposed between the first sub-signal line 01 and the third sub-signal line 03 and the two are electrically connected through the first bridge 14. A virtual bridge 15 is disposed between the first sub-signal line 01 and the fourth sub-signal line 04, a virtual bridge 15 is disposed between the second sub-signal line 02 and the third sub-signal line 03, and a virtual bridge 15 is disposed between the second sub-signal line 02 and the fourth sub-signal line 04.
In addition, the shapes of the first bridge span 14 and the virtual bridge span 15 can be different, and both are protruded away from the areas where the first gap 11 and the second gap 12 are located.
In one embodiment of the present application, a first bridge 14 is disposed between electrically connected ones of the first sub-signal line 01, the second sub-signal line 02, the third sub-signal line 03, and the fourth sub-signal line 04, and a dummy bridge 15 is disposed between electrically insulated ones of the electrically connected ones. The influence of only setting the first bridge span 14 on the visual effect difference in different directions can be relieved by setting the virtual bridge span 15.
In one embodiment of the present application, as shown in fig. 6, in the first sub-signal line 01 and the second sub-signal line 02 on both sides of the first gap 11, the shape of the end portion of the first sub-signal line 01 near the first gap 11 is the same as the shape of the end portion of the second sub-signal line 02 near the first gap 11; in the third sub-signal line 03 and the fourth sub-signal line 04 on both sides of the second gap 12, the shape of the end portion of the third sub-signal line 03 close to the second gap 12 is the same as the shape of the end portion of the fourth sub-signal line 04 close to the second gap 12.
That is, the two end portions of the first gap 11 are the same in shape and the two end portions of the second gap 12 are the same in shape, further ensuring an extremely low visual effect difference.
Preferably, in one implementation of the embodiment of the present invention, as shown in fig. 6, there are overlapping peripheries of the first gap 11 and the second gap 12, and a shape of an end portion of the first sub-signal line 01 close to the first gap 11, a shape of an end portion of the second sub-signal line 02 close to the first gap 11, a shape of an end portion of the third sub-signal line 03 close to the second gap 12, and a shape of an end portion of the fourth sub-signal line 04 close to the second gap 12 are the same.
Fig. 7 is a partial cross-sectional view of the signal line along MN in the array substrate provided in fig. 6.
In an embodiment of the present application, as shown in fig. 7, an array substrate according to an embodiment of the present invention includes a substrate 001, and a first bridge 14 disposed on the substrate 001, where the first bridge 14 may electrically connect a first sub-signal line 01 and a second sub-signal line 02, and/or the first bridge 14 may electrically connect the first sub-signal line 01 and a third sub-signal line 03. For example, as shown in fig. 7, the first bridge 14 electrically connects the first sub-signal line 01 and the second sub-signal line 02.
The film layer where the first bridge 14 is located on one side, away from the light emitting surface, of the film layer where the first sub-signal line 01 is located, an insulating layer is arranged between the film layer and the light emitting surface, and the first bridge 14 is electrically connected with the first sub-signal line 01 through a via hole penetrating through the insulating layer. The film layer where the first bridge 14 is located is also located on one side, away from the light emitting surface, of the film layer where the second sub-signal line 02/the third sub-signal line 03 are located, and the two sides are also separated by the insulating layer. For example, as shown in fig. 7, the first bridge 14 is electrically connected to the first sub-signal line 01 and the third sub-signal line 03 through vias. In this embodiment, the first sub-signal line 01 and the third sub-signal line 03 are electrically connected through the first overpass 14 disposed in a different layer.
In addition, when the array substrate further includes the virtual bridge 15, the film layer where the virtual bridge 15 is located is also located on a side of the film layer where the first sub-signal line 01 is located, which is far away from the light emitting surface. Wherein the virtual bridge 15 may be arranged on the same layer as the first bridge 14.
As shown in fig. 7, a first bridge 14 is disposed between the third sub-signal line 03 and the first sub-signal line 01, and the first bridge 14 electrically connects the first sub-signal line 01 and the third sub-signal line 03. A virtual bridge 15 is arranged between the first sub-signal line 01 and the fourth sub-signal line 04, a virtual bridge 15 is arranged between the fourth sub-signal line 04 and the second sub-signal line 02, a virtual bridge 15 is arranged between the second sub-signal line 02 and the third sub-signal line 03, and the virtual bridge 15 is electrically insulated from the sub-signal lines. The film layers where the first bridge 14 and the virtual bridge 15 are located on one side of the film layer where the sub-signal line is located, which is far away from the light-emitting surface. The influence of the first bridge span 14 and the virtual bridge span 15 on the visual effect in different directions can be reduced.
It should be noted that the materials of the first overpass 14, the dummy overpass 15, the first sub-signal line 01, and the second sub-signal line 02 are one or a combination of several of molybdenum (Mo), titanium (Ti), aluminum (Al), copper (Cu), and nickel (Ni). The insulating layer is made of silicon oxide (SiOx), silicon nitride (SiNx) or a combination of the two.
Fig. 8 is a schematic projection diagram of a signal line in an array substrate according to an embodiment of the present invention.
In one embodiment of the present application, as shown in fig. 6 and 8, an end of the first sub-signal line 01 in the array substrate 101 near the first gap 11 is one of a rectangle and a sector; the end of the second sub-signal line 02 close to the first gap 11 is one of rectangular and fan-shaped; the end of the third sub-signal line 03 close to the second gap 12 is one of a rectangle and a sector; the end of the fourth sub-signal line 04 near the second gap 12 is one of rectangular and fan-shaped.
In one implementation manner of the present embodiment, as shown in fig. 6, an end portion of the first sub-signal line 01 close to the first gap 11 is rectangular, an end portion of the second sub-signal line 02 close to the first gap 11 is rectangular, an end portion of the third sub-signal line 03 close to the second gap 12 is rectangular, and an end portion of the fourth sub-signal line 04 close to the second gap 12 is rectangular. That is, the first sub-signal line 01 and the second sub-signal line 02 on both sides of the first gap 11 have the same shape at the end portions close to the first gap 11 as the third sub-signal line 03 and the fourth sub-signal line 04 on both sides of the second gap 12 have the same shape at the end portions close to the second gap 12, and both have a rectangular shape.
In addition, as shown in fig. 6, the array substrate 101 provided by the embodiment of the invention further includes a first bridge 14 and a virtual bridge 15. A first overpass 14 is arranged in a region between the first sub-signal line 01 and the third sub-signal line 03, and the first overpass 14 is used for electrically connecting the first sub-signal line 01 and the third sub-signal line 03; a dummy bridge 15 is provided in a region between the first sub-signal line 01 and the fourth sub-signal line 04, a region between the second sub-signal line 02 and the third sub-signal line 03, and a region between the second sub-signal line 02 and the fourth sub-signal line 04, and the dummy bridge 15 is not electrically connected to the sub-signal lines.
In this embodiment, the first sub-signal line 01 and the second sub-signal line 02 on both sides of the first gap 11 are disposed in a rectangular shape at the end portions close to the first gap 11, and the third sub-signal line 03 and the fourth sub-signal line 04 on both sides of the second gap 12 are disposed in a rectangular shape at the end portions close to the second gap 12. It will be easier to route on the array substrate.
In another implementation manner of this embodiment, as shown in fig. 8, the end of the first sub-signal line 01 close to the first gap 11 is in a fan shape, the end of the second sub-signal line 02 close to the first gap 11 is in a fan shape, the end of the third sub-signal line 03 close to the second gap 12 is in a fan shape, and the end of the fourth sub-signal line 04 close to the second gap 12 is in a fan shape. That is, the first sub-signal line 01 and the second sub-signal line 02 on both sides of the first gap 11 have the same shape at the end portions close to the first gap 11 as the third sub-signal line 03 and the fourth sub-signal line 04 on both sides of the second gap 12 at the end portions close to the second gap 12, and are fan-shaped.
Specifically, as shown in fig. 8, the array substrate 101 provided by the embodiment of the invention further includes a first bridge span 14 and a virtual bridge span 15. A first bridge 14 is disposed in a gap between the first sub-signal line 01 and the third sub-signal line 03, and the first bridge 14 is used for electrically connecting the first sub-signal line 01 and the third sub-signal line 03; a virtual bridge 15 is provided in a region between the first sub-signal line 01 and the fourth sub-signal line 04, a region between the second sub-signal line 02 and the third sub-signal line 03, and a region between the second sub-signal line 02 and the fourth sub-signal line 04, and the virtual bridge 15 is not electrically connected to the sub-signal lines.
In this embodiment, the first sub-signal line 01 and the second sub-signal line 02 on both sides of the first gap 11 are disposed in a fan shape at the end portions close to the first gap 11, and the third sub-signal line 03 and the fourth sub-signal line 04 on both sides of the second gap 12 are disposed in a fan shape at the end portions close to the second gap 12. The transition between the sub-signal lines crossing in the extending direction is smoother, and the visual effect is also improved.
Fig. 9 is a schematic projection diagram of a signal line in an array substrate according to an embodiment of the present invention.
As shown in fig. 9, in an end portion of the first sub-signal line 01 of the array substrate 101 close to the first gap 11, an edge far from the first gap 11 is an arc shape facing away from the first gap 11; in the end part of the second sub-signal line 02 of the array substrate 101 close to the first gap 11, the edge far away from the first gap 11 is in an arc shape facing away from the first gap 11; in the end part of the third sub-signal line 03 of the array substrate 101 close to the second gap 12, the edge far away from the second gap 12 is arc-shaped and faces away from the second gap 12; in the end portion of the fourth sub-signal line 04 of the array substrate 101 close to the second gap 12, the edge far from the second gap 12 is in the shape of an arc facing away from the second gap 12.
In this technical scheme, set up in the tip that each sub-signal line is close to corresponding clearance, the edge of keeping away from this corresponding clearance is for deviating from the arc shape of this clearance, and then the transition between the crossed sub-signal line of extending direction is more smooth, and the visual effect also can promote.
Fig. 10 is a partial cross-sectional view of a display panel according to an embodiment of the invention.
As shown in fig. 10, in an embodiment of the present application, there is further provided a display panel 100, where the display panel 100 includes the array substrate 101 provided in any one of the above embodiments. The display panel 100 may be any one or more of a liquid crystal display panel, an organic light emitting display panel, or the like.
With continued reference to fig. 10, the display panel 100 includes, in addition to the array substrate 101, a color filter substrate 102 disposed opposite to the array substrate 101, and the color filter substrate 102 may be disposed with a color filter 16 and a black matrix 17 surrounding the color filter 16.
In the display panel 100 provided by the embodiment of the present invention, both sides of the first gap 11 are provided with the partial regions of the second gap 12, and both sides of the second gap 12 are provided with the partial regions of the first gap 11. A gap is formed between the straight line where the third sub-signal line 03 and the fourth sub-signal line 04 are located and the first sub-signal line 01, and a gap is also formed between the straight line and the second sub-signal line 02, so that the visual effect uniformity can be realized in the first direction X; the portion including the second gap 12 between the third sub-signal line 03 and the first gap 11 and the portion including the second gap 12 between the fourth sub-signal line 04 and the first gap 11 enable visual uniformity in the second direction Y. Therefore, the uniformity of the visual effect of the display panel 100 in the first direction X and the second direction Y is achieved, and the display quality of the display panel 100 is improved.
Fig. 11 is a schematic diagram of a display device according to an embodiment of the disclosure.
As shown in fig. 11, an embodiment of the present application further provides a display device, which includes the display panel 100 provided in the foregoing embodiment, and a housing, where the housing forms an accommodating space for accommodating the display panel, and the housing may be rigid or flexible, and the present invention is not limited in this respect. It should be understood that the display device provided in the embodiment of the present invention may be other display devices with a display function, such as a computer, a television, a vehicle-mounted display device, and the present invention is not limited thereto.
According to the display device provided by the embodiment of the invention, the visual effect uniformity is realized in the first direction X and the second direction Y, and the display quality of the display device is improved.
The above description is only exemplary of the present application and should not be taken as limiting the present application, as any modification, equivalent replacement, or improvement made within the spirit and principle of the present application should be included in the scope of protection of the present application.

Claims (12)

1. An array substrate, comprising:
a first sub-signal line and a second sub-signal line extending in a first direction; a first gap is formed between the first sub-signal line and the second sub-signal line which are adjacently arranged along the first direction;
a third sub-signal line and a fourth sub-signal line extending in a second direction; a second gap is arranged between the third sub-signal line and the fourth sub-signal line which are adjacently arranged along the second direction; the first direction intersects the second direction;
wherein at least a portion of the first gap overlaps the second gap; in the first gap and the second gap which are overlapped, at least two of the first sub-signal line and the second sub-signal line on both sides of the first gap and the third sub-signal line and the fourth sub-signal line on both sides of the second gap are electrically connected and at least two of the first sub-signal line and the second sub-signal line are electrically insulated.
2. The array substrate of claim 1, wherein the first gaps and the second gaps form a first pattern, the first pattern is symmetric about a first axis of symmetry and the first pattern is symmetric about a second axis of symmetry; the first axis of symmetry is parallel to the first direction and the second axis of symmetry is parallel to the second direction.
3. The array substrate of claim 1, further comprising a first bridge;
the first sub-signal line and the third sub-signal line are electrically connected through the first bridge.
4. The array substrate of claim 1, further comprising a first bridge;
the first sub-signal line and the second sub-signal line are electrically connected through the first bridge.
5. The array substrate of claim 3 or 4, wherein the film layer where the first bridge is located on one side, away from the light emitting surface, of the film layer where the first sub-signal line is located.
6. The array substrate of claim 3 or 4, wherein the array substrate further comprises a virtual bridge;
and the virtual bridge is arranged between the electrically-connected two of the first sub-signal line, the second sub-signal line, the third sub-signal line and the fourth sub-signal line, and the virtual bridge is arranged between the electrically-connected two of the first sub-signal line, the second sub-signal line, the third sub-signal line and the fourth sub-signal line.
7. The array substrate of claim 1,
in the first sub-signal line and the second sub-signal line on both sides of the first gap, the shape of the end portion of the first sub-signal line close to the first gap is the same as the shape of the end portion of the second sub-signal line close to the first gap;
in the third sub-signal line and the fourth sub-signal line on both sides of the second gap, a shape of an end portion of the third sub-signal line near the second gap is the same as a shape of an end portion of the fourth sub-signal line near the second gap.
8. The array substrate of claim 7, wherein there is an overlap around the first gap and the second gap, and a shape of an end portion of the first sub-signal line near the first gap, a shape of an end portion of the second sub-signal line near the first gap, a shape of an end portion of the third sub-signal line near the second gap, and a shape of an end portion of the fourth sub-signal line near the second gap are the same.
9. The array substrate of claim 1,
the end part of the first sub-signal line close to the first gap is one of a rectangle and a sector;
the end part of the second sub-signal line close to the first gap is one of a rectangle and a sector;
the end part of the third sub-signal line close to the second gap is one of a rectangle and a sector;
the end of the fourth sub-signal line close to the second gap is one of rectangular and fan-shaped.
10. The array substrate of claim 1,
in the end part of the first sub-signal wire close to the first gap, the edge far away from the first gap is in an arc shape;
the edge of the second sub-signal wire, which is far away from the first gap, in the end part of the second sub-signal wire, which is close to the first gap, is in an arc shape;
in the end part of the third sub-signal wire close to the second gap, the edge far away from the second gap is in an arc shape;
in the end part of the fourth sub-signal wire close to the second gap, the edge far away from the second gap is in an arc shape.
11. A display panel comprising the array substrate according to any one of claims 1 to 10.
12. A display device comprising the display panel according to any one of claim 11.
CN202210766798.5A 2022-06-30 2022-06-30 Array substrate, display panel and display device Active CN115172424B (en)

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108878455A (en) * 2018-06-29 2018-11-23 厦门天马微电子有限公司 A kind of array substrate, display panel and display device
CN109541865A (en) * 2018-12-26 2019-03-29 厦门天马微电子有限公司 Array substrate, display panel and display device
US20190392771A1 (en) * 2018-06-21 2019-12-26 Shanghai Tianma Micro-electronics Co., Ltd. Array Substrate, Electronic Paper Display Panel and Drive Method Thereof and Display Device
CN112436047A (en) * 2020-11-30 2021-03-02 湖北长江新型显示产业创新中心有限公司 Display panel and display device
CN113160743A (en) * 2021-02-24 2021-07-23 合肥维信诺科技有限公司 Array substrate, display panel and display device

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20190392771A1 (en) * 2018-06-21 2019-12-26 Shanghai Tianma Micro-electronics Co., Ltd. Array Substrate, Electronic Paper Display Panel and Drive Method Thereof and Display Device
CN108878455A (en) * 2018-06-29 2018-11-23 厦门天马微电子有限公司 A kind of array substrate, display panel and display device
CN109541865A (en) * 2018-12-26 2019-03-29 厦门天马微电子有限公司 Array substrate, display panel and display device
CN112436047A (en) * 2020-11-30 2021-03-02 湖北长江新型显示产业创新中心有限公司 Display panel and display device
CN113160743A (en) * 2021-02-24 2021-07-23 合肥维信诺科技有限公司 Array substrate, display panel and display device

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