CN115172339B - Capacitor and preparation method thereof - Google Patents
Capacitor and preparation method thereof Download PDFInfo
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- CN115172339B CN115172339B CN202211059956.XA CN202211059956A CN115172339B CN 115172339 B CN115172339 B CN 115172339B CN 202211059956 A CN202211059956 A CN 202211059956A CN 115172339 B CN115172339 B CN 115172339B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/64—Impedance arrangements
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
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- H01L28/75—Electrodes comprising two or more layers, e.g. comprising a barrier layer and a metal layer
Abstract
The invention provides a capacitor and a preparation method thereof, belonging to the field of semiconductor manufacturing, wherein the capacitor comprises a first electrode, a dielectric layer and a second electrode, wherein the second electrode and the first electrode are arranged in parallel and oppositely and are respectively positioned at two sides of the dielectric layer; the second electrode comprises a metal structure and a silicon substrate, the silicon substrate is located between the dielectric layer and the metal structure, the metal structure covers the silicon substrate and the surface of the silicon substrate opposite to the silicon substrate, and the resistance of the metal structure is smaller than that of the silicon substrate. The metal structure and the silicon substrate are jointly used as the second electrode of the capacitor, so that the combination of the traditional capacitor and the silicon capacitor is realized, the capacitor has the characteristics of the silicon capacitor, namely the capacitor has the characteristics of larger temperature range and voltage range and small capacitance change when the capacitor is heated or bears higher voltage, and the problem of loss increase caused by poor conductivity of the silicon substrate in the silicon capacitor is solved.
Description
Technical Field
The invention relates to the field of semiconductor manufacturing, in particular to a capacitor and a preparation method thereof.
Background
As microelectronic circuits increase in energy efficiency, the required energy storage devices can also be made better, which means that integrating energy storage devices directly into a chip may be a cost-effective solution. Energy storage devices include conventional energy storage devices (e.g., parallel plate capacitors) and silicon capacitors. The conventional energy storage device has the advantages of large discharge curve window and almost constant voltage curve, so that energy is transferred to consumption circuit components more easily, the loss is lower, and the discharge current is very low, thereby ensuring the long-term availability of stored energy. However, conventional energy storage devices change capacitance large when heated or subjected to higher voltages, such that the capacitance becomes unstable.
The capacitance of the silicon capacitor has high stability in a wide temperature range and a wide voltage range, which means that the capacitance of the silicon capacitor does not change when being heated or subjected to higher voltage, and meanwhile, the silicon capacitor has low leakage current, so that the silicon capacitor can be greatly applied, specifically, for example, a high-density silicon capacitor of Murata, the surface area of the capacitor can be greatly increased by realizing three-dimensionality through a MOS (metal oxide semiconductor) process of a semiconductor, so that the electrostatic capacity of a unit area of a silicon substrate is improved, the advanced 3D structures provide an active capacitance area equivalent to 80 ceramic layers, and the capacitance value and the electrical performance are optimized, so that better performance can be provided.
Taking the application of capacitors in the automotive field as an example, as the innovation of automotive electronic systems requires more power electronic devices to meet the demand for higher temperatures in hybrid and fuel cell vehicles, many sensors on vehicles such as exhaust gas sensors, pressure sensors or combustion sensors must operate in high temperature environments, while most capacitors are limited to operating below 150 ℃ and electronic devices are limited to operating below 175 ℃. Therefore, under high voltage and large current, the capacitor needs to increase the temperature range to design a micro capacitor with high reliability, small leakage current, and good stability of voltage, time and humidity. In order to solve this problem, a silicon capacitor is generally used directly on a metal substrate in a power amplifier module, and the silicon capacitor is connected to a field effect transistor by wire bonding, so that a small silicon capacitor capable of holding a large capacity under actual conditions is used, and thus the silicon capacitor can be realized in a small size and a large capacity under actual conditions (under applied voltage and in a high temperature environment). However, poor conductivity of the Si material of the silicon capacitor increases the loss of the silicon capacitor.
Therefore, how to combine the conventional capacitor with the silicon capacitor to form a high frequency capacitor is a problem to be solved in the present stage.
Disclosure of Invention
The present invention is directed to a novel high frequency capacitor formed by combining a conventional capacitor with a silicon capacitor, which can solve the problem of a conventional capacitor that the capacitance is largely changed when the conventional capacitor is heated or subjected to a higher voltage, and the problem of an increase in loss due to poor conductivity of a silicon substrate.
In order to solve the above problems, the present invention provides a capacitor, including a first electrode, a dielectric layer and a second electrode, wherein the second electrode and the first electrode are parallel and opposite to each other, and are respectively located on two sides of the dielectric layer; the second electrode comprises a metal structure and a silicon substrate, the silicon substrate is located between the dielectric layer and the metal structure, the metal structure covers the silicon substrate and the surface, opposite to the silicon substrate, of the silicon substrate, and the resistance of the metal structure is smaller than that of the silicon substrate.
Optionally, the silicon substrate is doped with N-type ions or P-type ions.
Further, the doping concentration of the N-type ions or the P-type ions is 10 17 cm -3 ^3~10 21 cm -3 。
Optionally, the silicon substrate has a front surface and a back surface which are oppositely arranged, the dielectric layer is arranged on the front surface, and the metal structure is arranged on the back surface;
the metal structure at least comprises a conductive metal layer, and the conductive metal layer covers the back surface.
Furthermore, a groove is formed in the back surface of the silicon substrate, the groove is located in the silicon substrate, and the groove is filled with the conductive metal layer.
Furthermore, the longitudinal section of the groove is trapezoidal, and the width of the opening of the groove is the largest.
Further, the longitudinal section of the groove is rectangular.
Further, the metal structure further comprises a first transition metal layer and/or a second transition metal layer, and the first transition metal layer and/or the second transition metal layer are/is located between the conductive metal layer and the silicon substrate;
when the metal structure further comprises a first transition metal layer and a second transition metal layer, the first transition metal layer is arranged close to the silicon substrate, and the second transition metal layer is arranged close to the conductive metal layer.
Further, the material of the first transition metal layer includes Ti, the material of the second transition metal layer includes Ni, and the material of the conductive metal layer includes silver.
On the other hand, the invention also provides a preparation method of the capacitor, and the preparation method of the capacitor comprises the following steps:
providing a silicon substrate, wherein the silicon substrate comprises a front surface and a back surface which are oppositely arranged, and a dielectric layer and a first electrode are sequentially formed on the front surface;
thinning the silicon substrate from the back side;
and forming a metal structure on the back surface to form a second electrode and a capacitor.
Optionally, the thinning the silicon substrate from the back side includes:
and thinning the silicon substrate from the back side through a grinding process to obtain the silicon substrate with a preset thickness.
In another aspect, the present invention further provides a method for manufacturing a capacitor, including the following steps:
providing a silicon substrate, wherein the silicon substrate comprises a front surface and a back surface which are oppositely arranged;
etching the silicon substrate from the back side by an etching process to form a groove in the silicon substrate;
and forming a metal structure, wherein the metal structure fills the groove and covers the back surface to form a first electrode and a capacitor.
Optionally, etching the silicon substrate from the back surface by an etching process to form a groove in the silicon substrate includes:
and etching the silicon substrate from the back surface through an isotropic etching process to form a groove with a trapezoidal longitudinal section in the silicon substrate, wherein the width of an opening of the groove is the largest.
Further, etching the silicon substrate from the back side by an etching process to form a recess in the silicon substrate includes:
and etching the silicon substrate from the back surface through an anisotropic etching process to form a groove with a rectangular longitudinal section in the silicon substrate.
Further, forming a metal structure that fills the recess and covers the backside to form a first electrode and a capacitor includes:
sequentially depositing a first transition metal layer and a second transition metal layer on the inner wall of the groove by a sputtering process;
filling a conductive metal layer in the groove by a sputtering process, wherein the conductive metal layer also covers the back surface;
the conductive metal layer is processed by CMP planarization.
Optionally, before forming the groove or after forming the first electrode, the method further includes:
a dielectric layer and a first electrode are sequentially formed on the front surface.
Compared with the prior art, the invention has the following beneficial effects:
the invention provides a capacitor and a preparation method thereof, wherein the capacitor comprises a first electrode, a dielectric layer and a second electrode, wherein the second electrode and the first electrode are arranged in parallel and oppositely and are respectively positioned at two sides of the dielectric layer; the second electrode comprises a metal structure and a silicon substrate, the silicon substrate is located between the dielectric layer and the metal structure, the metal structure covers the silicon substrate and the surface of the silicon substrate opposite to the silicon substrate, and the resistance of the metal structure is smaller than that of the silicon substrate. The metal structure and the silicon substrate are jointly used as the second electrode of the capacitor, so that the combination of the traditional capacitor and the silicon capacitor is realized, the capacitor has the characteristics of the silicon capacitor, namely, the capacitor has the characteristics of larger temperature range and voltage range and small capacitance change when heating or bearing higher voltage, and the problem of loss increase caused by poor conductivity of the silicon substrate in the silicon capacitor is solved.
Furthermore, the silicon substrate is doped with N-type ions or P-type ions, so that the resistance of the second electrode can be reduced, the resistance of the capacitor is reduced, and the quality factor Q value of the capacitor is improved.
Furthermore, a groove is formed in the back surface of the silicon substrate, the groove is located in the silicon substrate, and the groove is filled with the conductive metal layer, so that the contact area between the metal structure and the silicon substrate is increased, the resistance of the second electrode is further reduced, the resistance of the capacitor is reduced, and the quality factor Q value of the capacitor is improved.
In addition, the preparation method of the capacitor provided by the invention has simple and convenient process and easy operation, and forms the capacitor with low cost.
Drawings
FIG. 1 is a schematic diagram of a parallel plate capacitor;
fig. 2 is a schematic structural diagram of a capacitor according to an embodiment of the present invention;
fig. 3 is a schematic structural diagram of forming a groove on a silicon substrate according to a second embodiment of the present invention;
fig. 4 is a schematic structural diagram of a capacitor according to a second embodiment of the present invention;
fig. 5 is a schematic structural diagram of forming a groove on a silicon substrate according to a third embodiment of the present invention;
fig. 6 is a schematic structural diagram of a capacitor according to a third embodiment of the present invention.
Description of reference numerals:
1-an upper electrode; 2-a lower electrode; 3-a dielectric layer;
100-a second electrode; 110-a silicon substrate; 111-grooves; 120-metal structure; 121-a first transition metal layer; 122-a second transition metal layer; 123-a conductive metal layer; 200-a dielectric layer; 300-first electrode.
Detailed Description
As described in the background, how to combine the conventional capacitor and the silicon capacitor to form a high frequency capacitor is a problem to be solved in the present stage. An important index of a high-frequency capacitor is its quality factor Q (quality factor), which characterizes the quality index of the ratio of the stored power of the capacitor to the dissipated power of the capacitor, i.e. the quality factor Q satisfies the formula:
Q=Energy storage/Energy loss；
Q=1/WCR；
wherein, energy storage is the stored power of the capacitor; energy loss is the power loss of the capacitor; w is the resonant frequency of the circuit in which the capacitor is located; c is the capacitance of the capacitor; r is the resistance within the capacitor.
It can be known that the resistance of the capacitor is inversely proportional to the Q value, i.e., the smaller the resistance, the higher the Q value, the smaller the loss of the capacitor, and the higher the efficiency. Therefore, the quality factor Q value of the capacitor can be improved by reducing the resistance.
As shown in fig. 1, the parallel plate capacitor includes a lower electrode 2, a dielectric layer 3 and an upper electrode 1 stacked together, and when a certain potential difference exists between the upper electrode 1 and the lower electrode 2, an electrostatic field distribution exists between the upper electrode 1 and the lower electrode 2. The dielectric layer 3 is, for example, an oxide layer, and the upper electrode 1 and the lower electrode 2 are made of metal. Parallel plate capacitors are the simplest capacitors, so that any non-parallel plate capacitor can be viewed as being made up of several small parallel plate capacitors connected in series and in parallel. Since the dielectric layer is not absolutely insulating, there is a certain conductivity, there is a certain leakage current, and the parallel plate capacitor has a large capacitance change when heated or subjected to higher voltages, so that the capacitance of the capacitor becomes unstable as it goes. Taking a Knowles parallel plate capacitor as an example, the upper electrode 1 and the lower electrode 2 are all identical rectangles. Under the conditions that the length L of the upper electrode 1 and the length L of the lower electrode 2 are both 2.54mm, the width W is 2.286mm +/-0.254 mm, and the thickness D of the dielectric layer is 0.178mm +/-0.051 mm, when the parallel plate capacitor bears voltage of 25V, the minimum value of the capacitance of the capacitor is 6200pF, and the maximum value is 10000pF; when the parallel plate capacitor bears a voltage of 50V, the capacitance of the capacitor takes a minimum value of 3700pF and a maximum value of 5500pF. It is known that the capacitance of a parallel plate capacitor becomes unstable as the voltage increases. Meanwhile, since the melting point of metal is lower than that of silicon, it is difficult to form a dielectric layer on metal (e.g., a lower electrode). For this reason, the lower electrode is replaced with a silicon substrate, and a dense oxide layer is formed as a dielectric layer on the silicon substrate by thermal growth, but it still has a problem that the conductivity of the Si material (i.e., the silicon substrate) is poor so that the loss increases.
Meanwhile, current silicon capacitors such as high density trench capacitors have a 3D array of trenches in a silicon substrate, each trench filled with an oxygen nitride layer and a doped polysilicon layer, and then the silicon substrate is covered with a metal electrode layer. Silicon capacitors exhibit extremely high stability and reliability and are ideal for high temperature applications, however, the poor conductivity of the silicon substrate makes these silicon capacitors highly resistive and hence highly lossy.
Based on the above analysis, the invention provides a capacitor and a preparation method thereof, wherein the capacitor comprises a first electrode, a dielectric layer and a second electrode, the second electrode and the first electrode are arranged in parallel and oppositely and are respectively positioned at two sides of the dielectric layer; the second electrode comprises a metal structure and a silicon substrate, the silicon substrate is located between the dielectric layer and the metal structure, the metal structure covers the silicon substrate and the surface, opposite to the silicon substrate, of the silicon substrate, and the resistance of the metal structure is smaller than that of the silicon substrate. The metal structure and the silicon substrate are jointly used as the second electrode of the capacitor, so that the combination of the traditional capacitor and the silicon capacitor is realized, the capacitor has the characteristics of the silicon capacitor, namely the capacitor has the characteristics of larger temperature range and voltage range and small capacitance change when the capacitor is heated or bears higher voltage, and the problem of loss increase caused by poor conductivity of the silicon substrate in the silicon capacitor is solved.
A capacitor and a method for manufacturing the same according to the present invention will be described in further detail below. The present invention will now be described in more detail with reference to the accompanying drawings, in which preferred embodiments of the invention are shown, it being understood that one skilled in the art may modify the invention herein described while still achieving the advantageous effects of the invention. Accordingly, the following description should be construed as broadly as possible to those skilled in the art and not as limiting the invention.
In the interest of clarity, not all features of an actual implementation are described. In the following description, well-known functions or constructions are not described in detail since they would obscure the invention in unnecessary detail. It will of course be appreciated that in the development of any such actual embodiment, numerous implementation-specific details must be set forth in order to achieve the developer's specific goals, such as compliance with system-related and business-related constraints, which will vary from one implementation to another. Moreover, it will be appreciated that such a development effort might be complex and time-consuming, but would nevertheless be a routine undertaking for those of ordinary skill in the art.
In order to make the objects and features of the present invention more comprehensible, embodiments of the present invention are described in detail below with reference to the accompanying drawings. It is to be noted that the drawings are in a very simplified form and are all used in a non-precise ratio for the purpose of facilitating and distinctly aiding in the description of the embodiments of the invention.
Example one
Fig. 2 is a schematic structural diagram of a capacitor provided in this embodiment. As shown in fig. 2, the present embodiment provides a capacitor, which includes a first electrode 300, a dielectric layer 200, and a second electrode 100, where the second electrode 100 and the first electrode 300 are parallel and opposite to each other, and are respectively located on two sides of the dielectric layer 200.
The second electrode 100 includes a metal structure 120 and a silicon substrate 110, the silicon substrate 110 is located between the dielectric layer 200 and the metal structure 120, the silicon substrate 110 has a front surface and a back surface which are relatively parallel, the dielectric layer 200 is disposed on the front surface, and the metal structure 120 is disposed on the back surface. The metal structure 120 and the silicon substrate 110 together serve as the second electrode 100 of the capacitor, so that the combination of the conventional capacitor and the silicon capacitor is realized, and the capacitor has the characteristics of the silicon capacitor, that is, the capacitor of the present embodiment has a wider temperature range and voltage range, and has the characteristic of small capacitance change when heated or subjected to a higher voltage, and the problem of increased loss caused by poor conductivity of the silicon substrate 110 in the silicon capacitor is also solved. In this embodiment, the front and back surfaces are both planar.
The silicon substrate 110 is heavily doped with N-type ions or P-type ions, so that the resistance value of the doped silicon substrate 110 is smaller than that of the silicon substrate 110 which is not doped with ions, the resistance of the second electrode 100 can be reduced, the resistance of the capacitor is reduced, and the quality factor Q value of the capacitor is improved. Wherein the doping concentration of the N-type ions or the P-type ions is 10 17 cm -3 ~10 21 cm -3 。
The metal structure 120 at least includes a conductive metal layer 123, the conductive metal layer 123 covers the back surface of the silicon substrate 110, and the material of the conductive metal layer 123 may be silver, gold, or copper, but is not limited thereto. Since the resistance of the conductive metal layer 123 is smaller than that of the silicon substrate 110, the overall resistance of the second electrode 100 is reduced, so that the resistance of the second electrode 100 is further reduced, and the resistance of the capacitor is further reduced.
Optionally, the metal structure 120 further includes a first transition metal layer 121 and/or a second transition metal layer 122, where the first transition metal layer 121 and/or the second transition metal layer 122 are located between the conductive metal layer 123 and the silicon substrate 110, so as to increase adhesion between the conductive metal layer 123 and the silicon substrate 110 and improve conductivity of the second electrode 100. When the metal structure 120 further includes a first transition metal layer 121 and a second transition metal layer 122, the first transition metal layer 121 is disposed close to the silicon substrate 110, and the second transition metal layer 122 is disposed close to the conductive metal layer 123. The material of the first transition metal layer 121 may be Ti, and the material of the second transition metal layer 122 may be Ni. In this embodiment, the contact surface between the metal structure 120 and the silicon substrate 110 is the entire plane of the silicon substrate 110 facing the metal structure 120.
The dielectric layer 200 may be a dense oxide layer, such as silicon oxide, and the second metal layer may be made of a conventional metal material, such as silver, gold, or copper, but is not limited thereto.
The embodiment also provides a preparation method of the capacitor, which comprises the following steps:
step S11: providing a silicon substrate 110, wherein the silicon substrate 110 comprises a front surface and a back surface which are oppositely arranged, and a dielectric layer 200 and a first electrode 300 are sequentially formed on the front surface;
step S12: thinning the silicon substrate 110 from the back side of the silicon substrate 110;
step S13: a metal structure 120 is formed on the backside to form the second electrode 100 and the capacitor.
The following describes in detail a method for manufacturing a capacitor according to this embodiment with reference to fig. 2.
Step S11 is performed first, providing a silicon substrate 110, wherein the silicon substrate 110 includes a front surface and a back surface oppositely disposed, and a dielectric layer 200 and a first electrode 300 are sequentially formed on the front surface.
The method specifically comprises the following steps:
firstly, a silicon substrate 110 is provided, the silicon substrate 110 may be an N-type heavily doped silicon substrate, wherein the N-type ion doping concentration of the silicon substrate 110 is 10 17 cm -3 ~10 21 cm -3 (ii) a The silicon substrate 110 may also be an N-type heavily doped silicon substrate, wherein the P-type ion doping concentration of the silicon substrate 110 is 10 17 cm -3 ~10 21 cm -3 。
Next, a dense oxide layer, such as a silicon oxide layer, is formed on the front surface of the substrate by thermal (thermal) growth, the oxide layer is used as the dielectric layer 200 of the capacitor, the controllability of the thermal growth process is strong, the thickness of the formed oxide layer is uniform, and the melting point of the silicon substrate 110 is higher than that of the metal, so that the growth of the dielectric layer 200 is easily performed. The thickness of the dielectric layer 200 can be calculated according to the specific required capacitance value.
Next, a first electrode 300 is formed on the dielectric layer 200, and the first electrode 300 covers a surface of the dielectric layer 200 away from the front surface.
Next, step S12 is performed to thin the silicon substrate 110 from the back side. In detail, the silicon substrate 110 is thinned from the back side of the silicon substrate 110 by a grinding process to obtain the silicon substrate 110 with a preset thickness.
Next, step S13 is performed to form a metal structure 120 on the back surface to form the second electrode 100 and the capacitor. In detail, a first transition metal layer 121, a second transition metal layer 122 and a conductive metal layer 123 are sequentially deposited on the back surface of the silicon substrate 110 by a sputtering process.
The method of the embodiment is simple and convenient in process and easy to operate, and the capacitor with low cost is formed.
Example two
Fig. 4 is a schematic structural diagram of a capacitor provided in this embodiment. As shown in fig. 4, compared with the first embodiment, the second electrode 100 of the present embodiment has a groove 111 formed on the back surface of the silicon substrate 110, and the width a at the opening of the groove 111 is greater than the width B at the bottom of the groove 111, so that the longitudinal section of the groove 111 is trapezoidal, the metal structure 120 fills the groove 111 and covers the back surface outside the groove 111, the contact area between the metal structure 120 and the silicon substrate 110 can be increased, the resistance of the second electrode 100 can be further reduced, the resistance of the capacitor is reduced, and the Q value of the quality factor of the capacitor is further improved. The silicon substrate 110 of the capacitor of the embodiment does not need to be thinned, so that the hidden danger of damage to the silicon substrate 110 caused by thinning of the silicon substrate 110 is avoided.
Correspondingly, the preparation method of the capacitor provided by the embodiment comprises the following steps:
step S21: providing a silicon substrate 110, wherein the silicon substrate 110 comprises a front surface and a back surface which are oppositely arranged;
step S22: etching the silicon substrate 110 from the back side by an isotropic etching process to form a groove 111 in the silicon substrate 110;
step S23: a metal structure 120 is formed, and the metal structure 120 fills the groove 111 and covers the back surface to form a first electrode 300 and a capacitor.
Fig. 3 is a schematic structural diagram of forming a groove on a silicon substrate according to this embodiment. As shown in fig. 3, in step S22, the groove 111 is located in the silicon substrate 110, that is, the depth of the groove 111 is smaller than the thickness of the silicon substrate 110. In this step, a groove 111 is formed on the back surface of the silicon substrate 110 by a wet etching process. Wherein, the solution of the wet etching process is KOH solution.
As shown in fig. 4, step S23 specifically includes:
first, a first transition metal layer 121 and a second transition metal layer 122 are sequentially deposited on an inner wall of the groove 111 through a sputtering process, and the first transition metal layer 121 and the second transition metal layer 122 have a uniform thickness on the inner wall. Optionally, the first transition metal layer 121 and the second transition metal layer 122 also cover the back surface outside the groove 111.
Next, the groove 111 is filled with a conductive metal layer 123, and the conductive metal layer 123 also covers the back surface.
Finally, the conductive metal layer 123 is planarized by CMP (chemical vapor polishing), so that a metal structure 120 layer with a predetermined thickness remains on the back surface outside the groove 111.
The preparation method of the capacitor further comprises the following steps:
a dielectric layer 200 and a first electrode 300 are sequentially formed on the front surface of the silicon substrate 110. This step may be performed before the step of forming the groove 111, or may be performed after the step of forming the conductive metal layer 123.
EXAMPLE III
Fig. 6 is a schematic structural diagram of a capacitor provided in this embodiment. As shown in fig. 6, compared with the embodiment, the back surface of the silicon substrate 110 of the second electrode 100 of the embodiment is formed with the groove 111, the width of the opening of the groove 111 is the same as the width of the groove 111 at the bottom of the groove, and is a, that is, the width of the groove 111 is a, so that the longitudinal section of the groove 111 is rectangular, the contact area between the metal structure 120 and the silicon substrate 110 is further increased, the resistance of the second electrode 100 can be further reduced, the resistance of the capacitor is further reduced, and the Q value of the quality factor of the capacitor is further improved. The silicon substrate 110 of the capacitor of the embodiment also does not need thinning treatment, thereby avoiding the hidden danger of damage of the silicon substrate 110 caused by thinning of the silicon substrate 110.
Correspondingly, the preparation method of the capacitor provided by the embodiment comprises the following steps:
step S31: providing a silicon substrate 110, wherein the silicon substrate 110 comprises a front surface and a back surface which are oppositely arranged;
step S32: etching the silicon substrate from the back side by an anisotropic etching process to form a groove 111 in the silicon substrate;
step S33: a metal structure 120 is formed, and the metal structure 120 fills the groove 111 and covers the back surface to form a first electrode 300 and a capacitor.
Fig. 5 is a schematic structural diagram of forming a groove on a silicon substrate according to this embodiment. As shown in fig. 5, in step S32, the groove 111 is located in the silicon substrate 110, that is, the depth of the groove 111 is smaller than the thickness of the silicon substrate 110. This step forms a groove 111 on the back surface of the silicon substrate 110 by a bosch process. Wherein the process gas of the bosch process is SF 6 And C 4 F 8 To pass through SF 6 Etching with gas and passing through C 4 F 8 The formation of the protective film is repeated at a high speed to realize high aspect ratio etching, thereby forming the groove 111 having a rectangular longitudinal section. Which further increases the inner wall area of the trench compared to the second embodiment, thereby increasing the contact area between the metal structure 120 and the silicon substrate 110 formed subsequently.
As shown in fig. 6, step S23 specifically includes:
first, a first transition metal layer 121 and a second transition metal layer 122 are sequentially deposited on the inner wall of the groove 111 through a sputtering process, and the first transition metal layer 121 and the second transition metal layer 122 have a uniform thickness on the inner wall. Optionally, the first transition metal layer 121 and the second transition metal layer 122 also cover the back surface outside the groove 111.
Next, the groove 111 is filled with a conductive metal layer 123 through a sputtering process, and the conductive metal layer 123 also covers the back surface.
Finally, the conductive metal layer 123 is planarized by CMP (chemical mechanical polishing), so that a layer of metal structures 120 of a predetermined thickness remains on the back surface outside the recess 111.
The preparation method of the capacitor further comprises the following steps:
a dielectric layer 200 and a first electrode 300 are sequentially formed on the front surface of the silicon substrate 110. This step may be performed before the step of forming the groove 111, or may be performed after the step of forming the conductive metal layer 123.
In summary, the present invention provides a capacitor and a method for manufacturing the same, wherein the capacitor includes a first electrode, a dielectric layer and a second electrode, the second electrode and the first electrode are parallel and opposite to each other, and are respectively located on two sides of the dielectric layer; the second electrode comprises a metal structure and a silicon substrate, the silicon substrate is located between the dielectric layer and the metal structure, the metal structure covers the silicon substrate and the surface of the silicon substrate opposite to the silicon substrate, and the resistance of the metal structure is smaller than that of the silicon substrate. The metal structure and the silicon substrate are jointly used as the second electrode of the capacitor, so that the combination of the traditional capacitor and the silicon capacitor is realized, the capacitor has the characteristics of the silicon capacitor, namely the capacitor has the characteristics of larger temperature range and voltage range and small capacitance change when the capacitor is heated or bears higher voltage, and the problem of loss increase caused by poor conductivity of the silicon substrate in the silicon capacitor is solved.
Furthermore, the silicon substrate is doped with N-type ions, so that the resistance of the second electrode can be reduced, the resistance of the capacitor is reduced, and the quality factor Q value of the capacitor is improved.
Furthermore, a groove is formed in the back surface of the silicon substrate, the groove is located in the silicon substrate, and the groove is filled with the conductive metal layer, so that the contact area between the metal structure and the silicon substrate is increased, the resistance of the second electrode is further reduced, the resistance of the capacitor is reduced, and the quality factor Q value of the capacitor is improved.
In addition, the preparation method of the capacitor provided by the invention has the advantages of simple and convenient process, easiness in operation and low cost.
In addition, it should be noted that the description of the terms "first", "second", and the like in the specification is only used for distinguishing each component, element, step, and the like in the specification, and is not used for representing a logical relationship or a sequential relationship between each component, element, step, and the like, unless otherwise specified or indicated.
It is to be understood that while the present invention has been described in conjunction with the preferred embodiments thereof, the foregoing description is not intended to limit the invention. It will be apparent to those skilled in the art that many changes and modifications can be made, or equivalents employed, to the presently disclosed embodiments without departing from the intended scope of the invention. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention are still within the scope of the protection of the technical solution of the present invention, unless the contents of the technical solution of the present invention are departed.
Claims (12)
1. A capacitor is characterized by comprising a first electrode, a dielectric layer and a second electrode, wherein the second electrode and the first electrode are arranged in parallel and oppositely and are respectively positioned at two sides of the dielectric layer; the second electrode comprises a metal structure and a silicon substrate, the silicon substrate is provided with a front surface and a back surface which are oppositely arranged, the dielectric layer is arranged on the front surface, the metal structure is arranged on the back surface, the resistance of the metal structure is smaller than that of the silicon substrate, a groove is further formed in the back surface of the silicon substrate, the groove is located in the silicon substrate, the metal structure at least comprises a conductive metal layer, and the conductive metal layer covers the back surface and is filled with the groove.
2. The capacitor of claim 1, wherein the silicon substrate is doped with N-type ions or P-type ions.
3. The capacitor of claim 2, wherein the N-type ions or P-type ions are doped at a concentration of 10 17 cm -3 ~10 21 cm -3 。
4. The capacitor of claim 1 wherein said groove is trapezoidal in longitudinal cross section and has a maximum width at the opening of said groove.
5. The capacitor of claim 1 wherein said flutes are rectangular in longitudinal cross section.
6. The capacitor of claim 1, wherein the metal structure further comprises a first transition metal layer and/or a second transition metal layer, the first transition metal layer and/or the second transition metal layer being located between the conductive metal layer and a silicon substrate;
when the metal structure further comprises a first transition metal layer and a second transition metal layer, the first transition metal layer is arranged close to the silicon substrate, and the second transition metal layer is arranged close to the conductive metal layer.
7. The capacitor of claim 6, wherein the material of the first transition metal layer comprises Ti, the material of the second transition metal layer comprises Ni, and the material of the conductive metal layer comprises silver.
8. A method of making a capacitor according to claim 1, comprising the steps of:
providing a silicon substrate, wherein the silicon substrate comprises a front surface and a back surface which are oppositely arranged;
etching the silicon substrate from the back side by an etching process to form a groove in the silicon substrate;
and forming a metal structure, wherein the metal structure fills the groove and covers the back surface to form a first electrode and a capacitor, and the metal structure at least comprises a conductive metal layer.
9. The method of manufacturing a capacitor of claim 8, wherein etching the silicon substrate from the backside by an etching process to form a recess in the silicon substrate comprises:
and etching the silicon substrate from the back surface by an isotropic etching process to form a groove with a trapezoidal longitudinal section in the silicon substrate, wherein the width of the opening of the groove is the largest.
10. The method of claim 8, wherein etching the silicon substrate from the back side by an etching process to form a recess in the silicon substrate comprises:
and etching the silicon substrate from the back surface through an anisotropic etching process to form a groove with a rectangular longitudinal section in the silicon substrate.
11. The method of claim 8, wherein forming a metal structure that fills the recess and covers the back surface to form a first electrode and a capacitor comprises:
sequentially depositing a first transition metal layer and a second transition metal layer on the inner wall of the groove through a sputtering process;
filling a conductive metal layer in the groove by a sputtering process, wherein the conductive metal layer also covers the back surface;
the conductive metal layer is processed by CMP planarization.
12. The method of manufacturing a capacitor as claimed in claim 8, further comprising, before forming the recess or after forming the first electrode:
a dielectric layer and a first electrode are sequentially formed on the front surface.
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| CN102568817A (en) * | 2012-03-01 | 2012-07-11 | 中北大学 | MEMS (Micro Electro Mechanical System) capacitor based on three-dimensional silicon micro structure and manufacturing method thereof |
| US9786592B2 (en) * | 2015-10-30 | 2017-10-10 | Taiwan Semiconductor Manufacturing Co., Ltd. | Integrated circuit structure and method of forming the same |
| CN105261657B (en) * | 2015-10-30 | 2018-05-11 | 中国振华集团云科电子有限公司 | A kind of manufacturing process of MIS thin film capacitors |
| CN105355448B (en) * | 2015-11-25 | 2018-02-02 | 太原理工大学 | A kind of MEMS supercapacitor based on high dielectric constant film and preparation method thereof |
| US10693019B2 (en) * | 2018-08-27 | 2020-06-23 | Taiwan Semiconductor Manufacturing Co., Ltd. | Film scheme for a high density trench capacitor |
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