CN115172178A - Chip vertical integrated packaging structure utilizing carrier plate and preparation method thereof - Google Patents
Chip vertical integrated packaging structure utilizing carrier plate and preparation method thereof Download PDFInfo
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- CN115172178A CN115172178A CN202210932038.7A CN202210932038A CN115172178A CN 115172178 A CN115172178 A CN 115172178A CN 202210932038 A CN202210932038 A CN 202210932038A CN 115172178 A CN115172178 A CN 115172178A
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- 238000004806 packaging method and process Methods 0.000 title claims abstract description 28
- 238000002360 preparation method Methods 0.000 title claims abstract description 19
- 238000000034 method Methods 0.000 claims abstract description 24
- 239000002184 metal Substances 0.000 claims abstract description 22
- 229910052751 metal Inorganic materials 0.000 claims abstract description 22
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims abstract description 14
- 229910052802 copper Inorganic materials 0.000 claims abstract description 14
- 239000010949 copper Substances 0.000 claims abstract description 14
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims abstract description 12
- 238000005553 drilling Methods 0.000 claims abstract description 7
- 238000005476 soldering Methods 0.000 claims description 14
- 238000004519 manufacturing process Methods 0.000 claims description 8
- 230000010354 integration Effects 0.000 claims description 7
- 239000011248 coating agent Substances 0.000 claims description 6
- 238000000576 coating method Methods 0.000 claims description 6
- 229910000679 solder Inorganic materials 0.000 claims description 6
- 238000001465 metallisation Methods 0.000 claims description 3
- 230000002093 peripheral effect Effects 0.000 claims description 3
- 238000007639 printing Methods 0.000 claims description 3
- 239000000758 substrate Substances 0.000 claims description 3
- 238000004381 surface treatment Methods 0.000 claims description 3
- 239000003292 glue Substances 0.000 claims description 2
- 238000010586 diagram Methods 0.000 description 4
- 238000011161 development Methods 0.000 description 2
- 238000012536 packaging technology Methods 0.000 description 2
- 238000013473 artificial intelligence Methods 0.000 description 1
- 239000000084 colloidal system Substances 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 238000007306 functionalization reaction Methods 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 238000010295 mobile communication Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 230000000750 progressive effect Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49838—Geometry or layout
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5386—Geometry or layout of the interconnection structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/818—Bonding techniques
- H01L2224/81801—Soldering or alloying
- H01L2224/81815—Reflow soldering
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Geometry (AREA)
- Manufacturing & Machinery (AREA)
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
Abstract
The invention discloses a chip vertical integrated packaging structure utilizing a carrier plate and a preparation method thereof, relating to the technical field of integrated circuit three-dimensional packaging, and comprising the following steps: preparing a copper column bump on a bonding pad of a first chip, and preparing a tin bump on a bonding pad of a second chip; exposing the conductive metal layer on any surface of the carrier plate based on the second chip; exposing the metal layer in the carrier plate on the basis of the first chip on the other surface of the carrier plate by adopting a laser drilling method to form a first conductive blind hole; respectively arranging a first chip and a second chip on two sides of a carrier plate according to different methods to finish the preparation of a packaging module; the invention realizes the reliable packaging of chips with various sizes and different functions by the carrier plate.
Description
Technical Field
The invention relates to the technical field of integrated circuit three-dimensional packaging, in particular to a chip vertical integrated packaging structure utilizing a carrier plate and a preparation method thereof.
Background
The integrated circuit packaging technology has been developed following the development of the chip, the packaging density has been continuously improved from single chip packaging to three-dimensional packaging, the miniaturization and functionalization of electronic information products are strongly promoted, and the development of system-in-package has been widely paid attention and paid attention on the premise of comprehensive consideration of the volume, processing speed, electrical characteristics and the like. Three-dimensional packaging is the mainstream of the packaging technology of communication semiconductor devices because of its many significant advantages such as high density integration, multiple functions, etc., and is particularly suitable for applications in the fields of flash control, mobile communication and mobile multimedia.
The sizes of chips with different functions are often different greatly, the size of a packaging module prepared by planar integration is large, the packaging module is not suitable for application scenes of electronic devices with space limitation, and the adoption of a three-dimensional stacked packaging structure becomes the most preferable scheme. However, in the three-dimensional stacking process, for the occasions with large size difference or the occasions with the requirement on heat dissipation, the stacking scheme is limited, and the reliability of the packaged module may be deteriorated; therefore, how to realize a small-sized and high-reliability package for chips with different sizes is a problem to be solved by those skilled in the art.
Disclosure of Invention
In view of the above, the present invention provides a vertical integrated chip package structure using a carrier and a method for manufacturing the same, which overcome the above-mentioned problems.
In order to achieve the above purpose, the invention provides the following technical scheme:
a method for preparing a chip vertical integrated packaging structure by utilizing a carrier plate comprises the following specific steps:
respectively carrying out bump preparation on the first chip and the second chip;
preparing a corresponding carrier plate containing a plurality of layers of conductive wires according to the first chip and the second chip;
and respectively arranging the first chip and the second chip on two sides of the carrier plate according to different methods to finish the preparation of the packaging module.
The method has the advantages that the chip is integrated through the carrier plate, and the integration process can be simplified.
Optionally, bump preparation is performed on the first chip and the second chip respectively, specifically: preparing a copper pillar bump on a bonding pad of a first chip; and preparing tin bumps on the bonding pads of the second chip.
Optionally, the preparation method of the carrier plate comprises: exposing the conductive metal layer on any surface based on the second chip; and exposing the metal layer in the carrier plate on the other surface of the first chip by adopting a laser drilling method to form a first conductive blind hole.
Optionally, the fixing method of the first chip is as follows:
aligning and attaching the copper pillar salient points of the first chip to the first conductive blind holes of the carrier plate;
reflow soldering the copper pillar salient points and the first conductive blind hole interface of the carrier plate;
filling underfill around the first chip, and curing and coating the first chip;
and laser drilling is adopted in the peripheral area of the first chip to expose metal interfaces which are interconnected with each other in the carrier plate, so that a second conductive blind hole is formed.
Optionally, the fixing method of the second chip is as follows:
filling solder paste or other metal paste/glue in the second conductive blind hole, and soft baking for metallization;
carrying out surface treatment on the corresponding surface of the carrier plate, and reversely pasting the second chip on the exposed conductive metal layer of the carrier plate;
reflowing the tin bumps of the second chip to complete the conductive interconnection;
coating underfill around the second chip to cover the second chip;
and printing the solder balls on the filled second conductive blind holes, and performing reflow soldering.
Optionally, the carrier is a printed circuit board or a substrate.
A chip vertical integrated package structure using a carrier plate comprises the carrier plate, a first chip and a second chip; the first chip and the second chip are respectively positioned on two sides of the carrier plate; the first chip is arranged in the corresponding first conductive blind hole on the carrier plate through the copper column salient point and is fixed through reflow soldering; and the second chip is fixed with the conductive metal layer on the surface of the carrier plate through tin bumps by reflow soldering.
Optionally, the carrier plate further includes a second conductive blind hole, and the second conductive blind hole is coplanar with the first chip.
According to the technical scheme, compared with the prior art, the invention discloses the chip vertical integrated packaging structure utilizing the carrier plate and the preparation method thereof, and the carrier plate is used for realizing the reliable packaging of chips with various sizes and different functions in a high integration manner.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.
FIG. 1 is a schematic structural view of the present invention;
FIG. 2 is a first chip structure diagram according to the present invention;
FIG. 3 is a diagram of a second chip structure according to the present invention;
FIG. 4 is a structural diagram of a carrier plate according to the present invention;
FIG. 5 is a diagram of a first chip after packaging;
FIG. 6 is a flow chart of a method of the present invention;
wherein, 1 is a first chip; 2 is a copper column salient point; 3 is a second chip; 4 is a tin bump; 5 is a carrier plate; 6 is a first conductive blind hole; 7 is a conductive metal layer; 8 is a second conductive blind hole; 9 is underfill; 10 is solder ball.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The embodiment of the invention discloses a preparation method of a chip vertical integrated packaging structure by utilizing a carrier plate, which comprises the following specific steps as shown in figure 6:
and 3, respectively arranging the first chip 1 and the second chip 3 on two sides of the carrier plate 5 according to different methods, and completing the preparation of the packaging module.
Two chips with larger size difference (for example, a smaller logic first chip 1 and a larger storage second chip 3) integrated by the packaging module; the final package module size is only slightly larger than the second chip 3.
In step 1 of this embodiment, bump preparation is performed on the first chip 1 and the second chip 3, specifically: preparing a copper pillar bump 2 on a bonding pad of a first chip 1, as shown in fig. 2; tin bumps 4 are prepared on the pads of the second chip 3 as shown in fig. 3.
The preparation method of the carrier plate 5 in step 2 of this embodiment is as follows: exposing the conductive metal layer 7 on any surface of the carrier plate 5 based on the second chip 3; based on the first chip 1, the metal layer in the carrier plate 5 is exposed on the other surface of the carrier plate 5 by a laser drilling method, so as to form a first conductive blind via 6, as shown in fig. 4.
The carrier board 5 in this embodiment has several metal conductive layers.
In step 3 of this embodiment, the fixing method of the first chip 1 is as follows:
aligning and attaching the copper pillar salient points 2 of the first chip 1 to a first conductive blind hole 6 prepared on a carrier plate 5 in advance;
reflow soldering the copper pillar salient points 2 and the interfaces of the first conductive blind holes 6 of the carrier plate 5;
filling underfill 9 around the first chip 1, and curing and coating the first chip 1;
exposing an externally interconnected metal interface in the carrier plate 5 in the peripheral area of the first chip 1 by adopting laser drilling to form a second conductive blind hole 8; the resulting structure is shown in fig. 5.
In step 3 of this embodiment, the second chip 3 is fixed by:
filling solder paste or other conductive metal-containing colloid in the second conductive blind holes 8, and soft baking for curing;
carrying out surface treatment on the corresponding surface of the carrier plate 5, and inversely sticking the second chip 3 on the exposed conductive metal layer 7;
reflow soldering the tin bumps 4 of the second chip 3 to complete conductive interconnection;
preparing a blind hole printing tin ball 10 filled with metallization, and finally performing reflow soldering to complete the preparation of the packaging module; the packaging module is externally interconnected through the large-size solder balls 10.
Through the above steps, the integrated structure shown in fig. 1 can be obtained.
In another embodiment, the carrier 5 is a printed circuit board or a substrate.
In another embodiment, a vertical integrated structure using a carrier 5, as shown in fig. 1, includes a carrier 5, a first chip 1, a second chip 3; the first chip 1 and the second chip 3 are located on two sides of the carrier plate 5; the first chip 1 is arranged in a corresponding first conductive blind hole 6 on the carrier plate 5 through the copper pillar salient point 2 and is fixed through reflow soldering; the second chip 3 is fixed with the conductive metal layer 7 on the surface of the carrier plate 5 through the tin salient points 4 by reflow soldering.
In this embodiment, the carrier 5 further includes a second conductive via 8, and the second conductive via 8 is coplanar with the first chip 1.
The packaging structure obtained by the preparation method is mainly used for preparing artificial intelligence devices and has wide application in mobile electronics, detection devices and the like.
The embodiments in the present description are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (8)
1. A preparation method of a chip vertical integration packaging structure by using a carrier plate is characterized by comprising the following specific steps:
respectively carrying out bump preparation on the first chip (1) and the second chip (3);
preparing a corresponding carrier plate (5) with a plurality of layers of conducting wires according to the first chip (1) and the second chip (3);
the first chip (1) and the second chip (3) are respectively arranged on two sides of the carrier plate (5) according to different methods.
2. The method for manufacturing a vertically integrated chip package structure using a carrier according to claim 1, wherein the bump manufacturing is performed on the first chip (1) and the second chip (3) respectively, specifically: preparing copper pillar bumps (2) on a bonding pad of a first chip (1); tin bumps (4) are prepared on the pads of the second chip (3).
3. The method for manufacturing a vertical integrated package for chip using carrier according to claim 2, wherein the method for manufacturing the carrier (5) comprises: exposing the conductive metal layer (7) on any surface of the carrier plate (5) based on the second chip (3); based on the first chip (1), the metal layer in the carrier plate (5) is exposed on the other surface of the carrier plate (5) by adopting a laser drilling method, and a first conductive blind hole (6) is formed.
4. The method for manufacturing a vertical integrated package for chips using a carrier according to claim 3, wherein the method for fixing the first chip (1) comprises:
aligning and attaching the copper column salient points (2) of the first chip (1) to the first conductive blind holes (6) of the carrier plate (5);
reflow soldering the copper pillar salient points (2) and the interfaces of the first conductive blind holes (6) of the carrier plate (5);
filling underfill (9) around the first chip (1), and curing and coating the first chip (1);
and laser drilling is adopted in the peripheral area of the first chip (1) to expose metal interfaces which are interconnected with each other inside and outside the carrier plate (5) so as to form a second conductive blind hole (8).
5. The method for manufacturing a chip vertical integration package structure using a carrier according to claim 4, wherein the second chip (3) is fixed by:
filling paste/glue containing conductive metal in the second conductive blind hole (8), and soft baking for metallization;
carrying out surface treatment on the corresponding surface of the carrier plate (5), and inversely sticking the second chip (3) on the conductive metal layer (7) exposed out of the carrier plate (5);
reflow soldering tin bumps (4) of the second chip (3) to complete conductive interconnection;
coating underfill (9) around the second chip (3) to coat the second chip (3);
and printing a solder ball (10) on the second conductive blind hole (8), and performing reflow soldering.
6. The method for manufacturing a vertical integrated package for chip utilizing carrier as claimed in claim 1, wherein the carrier (5) is a printed circuit board or a substrate.
7. A chip vertical integration packaging structure using a carrier plate is characterized by comprising a carrier plate (5), a first chip (1) and a second chip (3); the first chip (1) and the second chip (3) are respectively positioned at two sides of the carrier plate (5); the first chip (1) is arranged in a corresponding first conductive blind hole (6) on the carrier plate (5) through a copper column salient point (2) and is fixed through reflow soldering; the second chip (3) is fixed with the conductive metal layer (7) on the surface of the carrier plate (5) through the tin salient points (4) in a reflow soldering mode.
8. The vertically integrated chip package structure using carrier according to claim 7, further comprising a second conductive via (8) on the carrier (5), wherein the second conductive via (8) is coplanar with the first chip (1).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210932038.7A CN115172178A (en) | 2022-08-04 | 2022-08-04 | Chip vertical integrated packaging structure utilizing carrier plate and preparation method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210932038.7A CN115172178A (en) | 2022-08-04 | 2022-08-04 | Chip vertical integrated packaging structure utilizing carrier plate and preparation method thereof |
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| CN115172178A true CN115172178A (en) | 2022-10-11 |
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| CN202210932038.7A Pending CN115172178A (en) | 2022-08-04 | 2022-08-04 | Chip vertical integrated packaging structure utilizing carrier plate and preparation method thereof |
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20050073678A (en) * | 2004-01-09 | 2005-07-18 | 주식회사 하이닉스반도체 | Method for manufacturing bga type package |
| US20060284299A1 (en) * | 2005-06-20 | 2006-12-21 | Stats Chippac Ltd. | Module Having Stacked Chip Scale Semiconductor Packages |
| KR20070077685A (en) * | 2006-01-24 | 2007-07-27 | 삼성전자주식회사 | Semiconductor package using substrate with solder bump and manufacturing method thereof |
| EP3748672A1 (en) * | 2018-02-24 | 2020-12-09 | Huawei Technologies Co., Ltd. | Chip and packaging method |
| CN114649292A (en) * | 2022-03-11 | 2022-06-21 | 无锡中微高科电子有限公司 | Three-dimensional fan-out type packaging structure and manufacturing method thereof |
-
2022
- 2022-08-04 CN CN202210932038.7A patent/CN115172178A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20050073678A (en) * | 2004-01-09 | 2005-07-18 | 주식회사 하이닉스반도체 | Method for manufacturing bga type package |
| US20060284299A1 (en) * | 2005-06-20 | 2006-12-21 | Stats Chippac Ltd. | Module Having Stacked Chip Scale Semiconductor Packages |
| KR20070077685A (en) * | 2006-01-24 | 2007-07-27 | 삼성전자주식회사 | Semiconductor package using substrate with solder bump and manufacturing method thereof |
| EP3748672A1 (en) * | 2018-02-24 | 2020-12-09 | Huawei Technologies Co., Ltd. | Chip and packaging method |
| CN114649292A (en) * | 2022-03-11 | 2022-06-21 | 无锡中微高科电子有限公司 | Three-dimensional fan-out type packaging structure and manufacturing method thereof |
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