CN115168122A - Packaging structure for multi-chip module - Google Patents
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- CN115168122A CN115168122A CN202210853727.9A CN202210853727A CN115168122A CN 115168122 A CN115168122 A CN 115168122A CN 202210853727 A CN202210853727 A CN 202210853727A CN 115168122 A CN115168122 A CN 115168122A
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- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/2205—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested
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Abstract
The present disclosure provides a package structure for a multi-chip module, which includes: a plurality of chips and a plurality of pins, wherein the plurality of chips comprise a plurality of types of interfaces, and each of the plurality of chips comprises at least one type of interface, at least two of the plurality of chips having one or more interfaces of the same type, wherein the plurality of types of interfaces comprise interfaces for testing and calibration. The plurality of pins are used to connect various types of interfaces of the plurality of chips to devices external to the package structure. Wherein a first pin of the plurality of pins corresponds to at least two chips of the plurality of chips and is used to connect the same type of interface included by the at least two chips to a device external to the package structure.
Description
Technical Field
The present disclosure relates to the field of chip packaging technology, and more particularly to a multi-chip module package structure.
Background
With the rapid development of chip technology, various requirements for chips have been continuously increased, especially for chip cost. It is well known that the cost of a chip is largely limited by the size of the chip, for which chip design and packaging are important factors.
In recent years, in order to improve the overall yield of chips and reduce the cost, a technology of packaging a plurality of small-sized chips or dies (Die) together has appeared. Designing a large-sized chip into a plurality of small-sized chips has the advantages of simplifying the design, reducing the loss caused by design or manufacturing errors of the large-sized chip, improving the yield and the like, but inevitably increases the work of connecting, testing and the like among the chips for the plurality of small-sized chips. The size required for chip packaging is also increased by chip connection, testing, and the like, and therefore, how to reduce the overall size in a multi-chip scenario is a technical problem that needs to be solved at present.
Disclosure of Invention
In order to solve the technical problem of the increase of the overall size of a chip caused by multi-chip connection, test and the like in the prior art, the disclosure provides a packaging structure for a multi-chip module, which shares the same pin for interfaces of the same type in a plurality of chips, thereby reducing the number of pins required during chip packaging, further reducing the overall area of the chip and lowering the cost.
At least one embodiment of the present disclosure provides a package structure for a multi-chip module, including: a plurality of chips, the plurality of chips including a plurality of types of interfaces, and each of the plurality of chips including at least one type of interface, at least two of the plurality of chips having one or more interfaces of the same type, wherein the plurality of types of interfaces include interfaces for testing and calibration; and a plurality of pins for connecting the plurality of types of interfaces of the plurality of chips to devices outside the package structure, wherein a first pin of the plurality of pins corresponds to at least two chips of the plurality of chips and is used for connecting the same type of interfaces included in the at least two chips to devices outside the package structure.
For example, in the package structure provided by an embodiment of the present disclosure, at least two chips are connected to a device outside the package structure in a time-sharing manner through the first pins, and the device outside the package structure is one or more devices.
For example, in the package structure provided by an embodiment of the present disclosure, for each of at least a part of the plurality of chips, the chip further includes a first circuit, and the first circuit is configured to perform a predetermined operation on the chip in conjunction with a device outside the package structure.
For example, in the package structure provided by an embodiment of the present disclosure, the first circuit is a calibration circuit, the device outside the package structure is a calibration resistor, and the calibration circuit performs a calibration operation on the chip in combination with the calibration resistor to adjust an equivalent resistance value of an interface of the chip.
For example, in the package structure provided in an embodiment of the present disclosure, the first pin connects at least two chips to the same calibration resistor in a time-sharing manner; when the first interfaces of different chips in the plurality of chips have the same type, the plurality of chips are simultaneously connected with different calibration resistors with the same value through one first pin, or the plurality of chips are connected with the same calibration resistor through only one first pin in a time-sharing manner.
For example, in the package structure provided in an embodiment of the present disclosure, when the plurality of chips are connected to the same calibration resistor through only one first pin in a time-sharing manner, the plurality of first circuits corresponding to the plurality of chips are sequentially connected to the same calibration resistor according to a preset sequence and perform a calibration operation according to the preset sequence.
For example, in a package structure provided in an embodiment of the present disclosure, a calibration circuit includes: the adjustable resistor is used for adjusting the equivalent resistance value of the corresponding interface of the chip according to the control signal; the comparator is connected with the adjustable resistor and the calibration resistor and used for comparing a voltage value between the equivalent resistance value and the calibration resistor with a reference voltage signal to obtain a comparison result; and the controller is used for acquiring a comparison result when receiving an instruction signal for performing calibration operation, and generating a control signal according to the comparison result.
For example, in the package structure provided in an embodiment of the present disclosure, the first circuit is a test circuit, and the test circuit performs a test operation on the chip in combination with a device outside the package structure to detect a failure condition of the chip.
For example, in a package structure provided in an embodiment of the present disclosure, a test circuit includes: the multiplexer is connected with the first interface and the plurality of channels in the chip and is used for receiving a plurality of test signals of the plurality of channels and sequentially outputting the plurality of test signals to the first device when receiving the indication signal for testing operation; when at least one of the plurality of test signals cannot be received by the first device, determining that one chip corresponding to the test circuit is in a fault state.
For example, in the package structure provided in an embodiment of the present disclosure, the first pin is a package ball.
At least one embodiment of the present disclosure provides a package structure for a multi-chip module, which is configured to share a same pin for interfaces of the same type in a plurality of chips, such as a test or calibration interface, where each pin corresponds to at least one chip, so as to reduce the number of pins required for chip packaging, thereby reducing the overall area of the chip and reducing the cost.
Drawings
To more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly described below, and it should be apparent that the drawings described below only relate to some embodiments of the present disclosure and are not limiting on the present disclosure.
Fig. 1 is a schematic diagram of a package structure for a multi-chip module according to at least one embodiment of the present disclosure;
fig. 2A illustrates a first circuit schematic when the first circuit provided in accordance with at least one embodiment of the present disclosure is a calibration circuit;
FIG. 2B shows a schematic diagram of calibration circuits in multiple chips connected to an external device through the same pin;
fig. 3A illustrates a first circuit schematic when the first circuit provided in accordance with at least one embodiment of the present disclosure is a test circuit;
fig. 3B illustrates a schematic diagram of test circuits in multiple chips connected to a first device through the same pin provided in accordance with at least one embodiment of the present disclosure.
Detailed Description
To make the objects, technical solutions and advantages of the embodiments of the present disclosure more clear, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings. It is to be understood that the described embodiments are only a few embodiments of the present disclosure, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the described embodiments of the disclosure without any inventive step, are within the scope of protection of the disclosure.
Unless otherwise defined, technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this disclosure belongs. The use of "first," "second," and similar terms in this disclosure is not intended to indicate any order, quantity, or importance, but rather is used to distinguish one element from another. Also, the use of the terms "a," "an," or "the" and similar referents do not denote a limitation of quantity, but rather denote the presence of at least one. The word "comprising" or "comprises", and the like, means that the element or item preceding the word comprises the element or item listed after the word and its equivalent, but does not exclude other elements or items. The terms "connected" or "coupled" and the like are not restricted to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "upper", "lower", "left", "right", and the like are used only to indicate relative positional relationships, and when the absolute position of the object being described is changed, the relative positional relationships may also be changed accordingly.
At least one embodiment of the present disclosure provides a package structure for a multi-chip module, including: a plurality of chips, the plurality of chips including a plurality of types of interfaces, and each of the plurality of chips including at least one type of interface, at least two of the plurality of chips having one or more interfaces of the same type, wherein the plurality of types of interfaces include interfaces for testing and calibration; and a plurality of pins for connecting the plurality of types of interfaces of the plurality of chips to devices outside the package structure, wherein a first pin of the plurality of pins corresponds to at least two chips of the plurality of chips and is used for connecting the same type of interfaces included in the at least two chips to devices outside the package structure.
The packaging structure for the multi-chip module provided by the disclosure has the advantages that for interfaces of the same type in a plurality of chips, such as a test or calibration interface, each interface shares the same pin, and each pin corresponds to at least one chip, so that the number of pins required in chip packaging is reduced, the whole area of the chip is reduced, and the cost is reduced.
At least one embodiment of the present disclosure provides a package structure for a multi-chip module, including: a plurality of chips and a plurality of pins, wherein the plurality of chips comprise a plurality of types of interfaces, and each of the plurality of chips comprises at least one type of interface, at least two of the plurality of chips having one or more interfaces of the same type, wherein the plurality of types of interfaces comprise interfaces for testing and calibration. The plurality of pins are used to connect the plurality of types of interfaces of the plurality of chips to devices external to the package structure. Wherein a first pin of the plurality of pins corresponds to at least two chips of the plurality of chips and is used to connect the same type of interface included by the at least two chips to a device external to the package structure.
Fig. 1 illustrates a schematic diagram of a package structure for a multi-chip module provided in accordance with an embodiment of the present disclosure.
As shown in fig. 1, the package structure 100 includes a plurality of chips 110 and a plurality of pins 120. The plurality of chips includes a chip 111, a chip 112, a chip 113, and a chip 114. The plurality of pins includes pin 121 and pin 122. Each of the plurality of chips 110 includes a test interface and a calibration interface, wherein chip 111 has a test interface 131 and a calibration interface 141, chip 112 has a test interface 132 and a calibration interface 142, chip 113 has a test interface 133 and a calibration interface 143, and chip 114 has a test interface 134 and a calibration interface 144. A plurality of test interfaces 131-134 are connected to pin 121 and a plurality of calibration interfaces 141-144 are connected to pin 122. The pin 121 and the pin 122 both belong to a first pin of the plurality of pins 120, and the pin 121 and the pin 122 are used for connecting the plurality of test interfaces 131-134 and the plurality of calibration interfaces 141-144, respectively, to devices external to the package structure 100. It is understood that the pins 121 and 122 may be considered as an "interface" of the package structure 100 with an external device.
It is understood that the plurality of chips 110 shown in fig. 1 includes 4 chips 111-114, and the plurality of chips 110 may also include more than 4 chips or less than 4 chips, such as 2, 3, 5 or more. Accordingly, the number of pins in the plurality of pins 120 is related to the type of interface of the plurality of chips 110, for example, the number of pins of the plurality of pins 120 is equal to the number of types of interface of the plurality of chips 110. It will also be appreciated that although each of the chips 111-114 shown in fig. 1 has a test interface and a calibration interface, in practice, the chips need not all be provided with interfaces of all types, and the same type of interfaces may be connected to the same pins, or a separate interface may be provided for each chip for all interface types.
Compared with the prior art in which one interface of each chip is connected to one pin, as in the package structure 100 shown in fig. 1, the same type of interface only needs to be connected to one pin, and compared with 4 test interfaces or 4 calibration interfaces which need to be connected to 4 pins, 4 test interfaces or 4 calibration interfaces in the package interface only need to be connected to 1 pin, thereby effectively reducing the number of pins by 75%.
Optionally, the first pin in the embodiment of the present application is a package ball. For example, the leads 121 and 122 are both package balls.
Further alternatively, the first pin may be a metal wire or the like according to different packaging technologies. For example, when a package technology such as fan-out, 2D, 2.5D, embedded multi-chip on-die bridge, etc. is used, the first pin is a package ball such as a BGA ball.
Optionally, at least two of the plurality of chips are time-divisionally connected to the device outside the package structure through the first pins, and the device outside the package structure is one or more devices.
For example, the chip 111 and the chip 112 are connected to the pin 121 through the test interface 131 and the test interface 132, respectively, so as to be connected to an external test device in a time-sharing manner. As another example, chip 111 and chip 112 are connected to pin 122 through calibration interface 141 and calibration interface 142, respectively, so as to be connected to an external calibration resistor in a time-sharing manner.
Optionally, for each chip of at least a part of the plurality of chips, the chip further includes a first circuit, and the first circuit is configured to perform a preset operation on the chip in conjunction with a device outside the package structure.
For example, the first circuit is related to the kind of interface, e.g. the chip 111 has the test interface 131 and the calibration interface 141, then the first circuit inside the chip 111 comprises the test circuit and the calibration circuit. If the chip 114 only has the test interface 134 and no calibration interface, the first circuit inside the chip 114 is a test circuit. Accordingly, different preset operations are performed on the chip according to different types of the first circuit, for example, if the first circuit is a test circuit, the chip is tested, and if the first circuit is a calibration circuit, the chip needs to be calibrated. When the first circuit includes both the test circuit and the calibration circuit, the chip needs to be subjected to a test operation and a calibration operation.
The following is described with respect to a scenario in which the first circuit is a calibration circuit and a test circuit, respectively.
Fig. 2A illustrates a first circuit schematic when the first circuit provided according to an embodiment of the present disclosure is a calibration circuit.
The calibration circuit 200 of FIG. 2A is disposed within a chip, such as the chips 111-114 shown in FIG. 1, and may include the calibration circuit 200. Fig. 2A illustrates an example of the calibration circuit 200 disposed in the chip 112, wherein the calibration circuit 200 is connected to the pin 122 through the calibration interface 142 of the chip 112, and the pin 122 is connected to the calibration resistor 260.
The comparator 210 is connected to the adjustable resistor 220 and the calibration resistor 260, and is configured to compare a voltage value between the equivalent resistance value and the calibration resistor with a reference voltage signal. One input of the comparator 210 receives the reference voltage signal Vef, the other input is connected to the protector 230, and the output of the comparator 210 is connected to the controller 250.
The protector 230 is connected to the adjustable resistor 220 and then to the calibration interface 142 via the zener diode 250.
The zener diode 240 includes 2 diodes 241 and 242 connected in series, an anode of the diode 241 is grounded, a cathode of the diode 241 is connected to an anode of the diode 242, and a cathode of the diode 242 is connected to a positive dc voltage. Alternatively, the calibration resistor 260 has a resistance value of 50 ohms, 100 ohms, etc., and the resistance value thereof can be adjusted according to actual requirements, for example, 75 ohms, 150 ohms, etc.
The controller 250 is configured to obtain a comparison result when receiving an instruction signal for performing a calibration operation, and generate a control signal according to the comparison result. The indication signal may be sent by a processor of the chip 112, for example, when the controller 250 receives the indication signal from the processor, the controller sends a control signal to the adjustable resistor 220 according to the comparison result output by the comparator 210, so as to adjust the resistance value of the adjustable resistor 220.
In the present embodiment, the calibration circuit 200 combines the calibration resistor 260 to perform a calibration operation on the chip 112 to adjust the equivalent resistance value of the interface 142 of the chip 112. The controller 250 receives the comparison result of the comparator 210, which is high level and low level or corresponding "1" and "0", and when the output result is high level, the resistance value of the adjustable resistor 220 is increased, and when the comparison result is low level, the resistance value of the adjustable resistor 220 is decreased, until the comparison result received by the controller 250 continues to change directly between high level and low level, it is determined to stop adjusting the resistance value of the variable circuit 220.
Fig. 2B shows a schematic diagram of the calibration circuits in multiple chips connected to external devices through the same pin.
In FIG. 2B, chip 112 and chip 113 shown in FIG. 1 are shown connected to calibration resistor 260 shown in FIG. 2A via pin 122. Chip 112 includes a calibration circuit 200, chip 113 includes a calibration circuit 200', and calibration circuit 200' may be the same as or different from calibration circuit 200.
Optionally, the first pin time-divisionally connects at least two chips to the same calibration resistor. When the first interfaces of different chips in the plurality of chips have the same type, the plurality of chips are connected with the same calibration resistor in a time-sharing manner through only one first pin.
For example, pin 122 connects chip 112 and chip 113 to calibration resistor 260, chip 112 and chip 113 connect pin 122 through calibration interface 142 and calibration interface 143, respectively, and chip 112 and chip 113 connect to calibration resistor 260 at different times, respectively. For example, chip 112 and chip 113 are connected to calibration resistor 260 in a preset order, or chip 112 notifies chip 113 whether calibration resistor 260 is available, or chip 112 is responsible for scheduling its use of calibration resistor 260 by chip 112 and chip 113. It should be understood that, although fig. 2B only shows the case where 2 chips are connected to the same calibration resistor, more chips may be connected to the same calibration resistor, and the time-sharing operation is similar to that in the present embodiment.
Optionally, when the plurality of chips are connected to the same calibration resistor through only one first pin in a time-sharing manner, the plurality of first circuits corresponding to the plurality of chips are sequentially connected to the same calibration resistor according to a preset sequence and perform calibration operation according to the preset sequence. For example, the chip 113 is sequentially arranged before the chip 112, the calibration circuit in the chip 113 first combines with the calibration resistor 260 to complete the calibration operation on the chip 113, and after the calibration operation on the chip 113 is completed, the calibration circuit in the chip 112 combines with the calibration resistor 260 to complete the calibration operation on the chip 112.
Further optionally, interfaces of the same type in the plurality of chips may be connected to different calibration resistances through different first pins. For example, the calibration resistance required by the chip 111 and the chip 112 is 50 ohms, the calibration resistance required by the chip 113 and the chip 114 is 75 ohms, the chip 111 and the chip 112 may be connected to the same 50 ohms calibration resistance through the same time-division multiplexing pin, the chip 113 and the chip 114 may be connected to the same 75 ohms calibration resistance through the same time-division multiplexing pin, and then the chip 111 or 112 and the chip 113 or 114 may be simultaneously connected to the corresponding calibration resistance through different pins, so that the chip 111 and the chip 114 may perform calibration operations simultaneously, and when there are a large number of chips to be calibrated, the calibration efficiency may be improved by this way.
Fig. 3A illustrates a first circuit schematic when the first circuit provided according to an embodiment of the present disclosure is a test circuit.
In fig. 3A, the test circuit 300 includes a multiplexer 310 and optionally a zener diode 320.
The multiplexer 310 is connected to the first interface 30 and to a plurality of channels within the chip. The multiplexer 310 is configured to receive a plurality of test signals of a plurality of channels when receiving an indication signal for performing a test operation, and sequentially output the plurality of test signals to the first device 330. The first device 330 is a device external to the package structure. When at least one of the plurality of test signals cannot be received by the first device 330, it is determined that a chip corresponding to the test circuit 300 is in a fault state.
The multiplexer 310 is optionally connected to a first pin 31 through a zener diode 320, the first pin 31 being connected to a first device 330. The first device 330 in this embodiment may be any test device that can confirm whether a test signal is received, and is not limited herein.
Taking the example where the test circuit 300 is disposed in the chip 114, the test circuit 300 is capable of performing a test operation on the chip 114 in conjunction with the first device 330 to detect a fault condition of the chip 114. It is to be noted that each of the plurality of chips 110 shown in fig. 1 needs to be subjected to a test operation to determine whether a single chip has a failure, and thus a test circuit needs to be provided in each chip. This test operation is generally used to test whether signal paths inside the chip are normal and connections of the chip to the outside are normal.
For example, the multiplexer 310 is connected to 8 channels, each of which can transmit signals/data bidirectionally, i.e., each of which can input and output signals/data. In each test, the test signals of the channels of 8 channels need to be tested in sequence, for example, 8 state tests are performed, and as long as one test signal cannot be received by the first device 330, it is determined that the chip currently being tested is in a fault state.
FIG. 3B shows a schematic diagram of test circuits in multiple chips connected to a first device through the same pin provided in accordance with an embodiment of the present disclosure.
Fig. 3B illustrates the plurality of chips 110 in fig. 1, where the chips 111-114 are connected to the pins 121 through the test interfaces 131-134, respectively, and then connected to the first device 330 through the pins 121. Test circuits 350, 360, 370, and 380 in chips 111-114 may all be as shown in test circuit 300 in FIG. 3A, although other test circuits may be used.
Similar to the multiple calibration circuits in fig. 2B, the test circuits 350, 360, 370, and 380 are time-shared to the first device 330, which operates in a manner similar to the multiple calibration circuits. For example, test circuits 350-380 are connected to first device 330 in a predetermined order and perform test operations in sequence, and test circuits 350-380 in chip 111-chip 114 are responsible for test operations, for example, by chip 111.
It is to be understood that, when at least one of the plurality of chips includes a plurality of first circuits of different kinds, which are combinations of the plurality of first circuits, the related description and reference to the first circuit are descriptions of the calibration circuit and the test circuit, and are not repeated herein.
For all chips in embodiments of the present disclosure, a unified address space may be employed. This means that for each chip, the address of the chip is a part of the complete address space, so that by decoding the address its corresponding chip can be known. The test operations and calibration operations described herein may be implemented by the unified address space when executed. Optionally, a corresponding chip identifier may also be set for each chip, so that the chips performing the operation are distinguished by the chip identifiers.
The processes described above may also be implemented as computer software programs in accordance with embodiments of the present disclosure. For example, embodiments of the present disclosure include a computer program product comprising a computer program containing program code for performing the methods of the above-described processes.
The method flow diagrams and apparatus block diagrams referred to in this disclosure are only exemplary examples and are not intended to require or imply that the connections and arrangements must be made in the manner illustrated in the flow diagrams and block diagrams. These devices, apparatuses may be connected, arranged in any manner as long as the desired purpose is achieved, as will be appreciated by those skilled in the art.
The scope of the present disclosure is not to be limited to the specific embodiments of the present disclosure, and the scope of the present disclosure should be determined by the scope of the appended claims. The drawings of the embodiments of the disclosure only relate to the structures related to the embodiments of the disclosure, and other structures can refer to common designs. Without conflict, embodiments of the present disclosure and features of the embodiments may be combined with each other to arrive at new embodiments.
Claims (10)
1. A package structure for a multi-chip module, comprising:
a plurality of chips including a plurality of types of interfaces and each of the plurality of chips including at least one type of interface, at least two of the plurality of chips having one or more interfaces of the same type, wherein the plurality of types of interfaces include interfaces for testing and calibration; and
a plurality of pins for connecting the plurality of types of interfaces of the plurality of chips to devices external to the package structure, wherein a first pin of the plurality of pins corresponds to at least two chips of the plurality of chips and is for connecting the same type of interfaces included in the at least two chips to devices external to the package structure.
2. The package structure of claim 1, wherein the at least two chips are time-shared through the first pins to a device external to the package structure, the device external to the package structure being one or more devices.
3. The package structure of claim 2, wherein for each of at least a portion of the plurality of chips, the chip further comprises a first circuit for performing a predetermined operation on the chip in conjunction with a device external to the package structure.
4. The package structure of claim 3, wherein the first circuit is a calibration circuit and the device external to the package structure is a calibration resistor, the calibration circuit performing a calibration operation on the chip in conjunction with the calibration resistor to adjust an equivalent resistance value of an interface of the chip.
5. The package structure of claim 4,
the first pin connects the at least two chips to the same calibration resistor in a time-sharing manner;
when the first interfaces of different chips in the plurality of chips have the same type, the plurality of chips are respectively connected with different calibration resistors with the same value through one first pin at the same time, or the plurality of chips are connected with the same calibration resistor through only one first pin in a time-sharing manner.
6. The package structure of claim 5, wherein when the plurality of chips are time-division connected to the same calibration resistor through only one first pin, the plurality of first circuits corresponding to the plurality of chips are sequentially connected to the same calibration resistor according to a preset sequence and perform calibration operation according to the preset sequence.
7. The package structure of claim 4, wherein the calibration circuit comprises:
the adjustable resistor is used for adjusting the equivalent resistance value of the corresponding interface of the chip according to the control signal;
the comparator is connected with the adjustable resistor and the calibration resistor and used for comparing the voltage value between the equivalent resistance value and the calibration resistor with a reference voltage signal to obtain a comparison result; and
and the controller is used for acquiring the comparison result when receiving an indication signal for carrying out calibration operation and generating the control signal according to the comparison result.
8. The package structure of claim 3, wherein the first circuit is a test circuit that performs a test operation on the chip in conjunction with a device external to the package structure to detect a fault condition of the chip.
9. The package structure of claim 8, wherein the test circuit comprises:
the multiplexer is connected with the first interface and the plurality of channels in the chip and is used for receiving a plurality of test signals of the plurality of channels when receiving an indication signal for testing operation and sequentially outputting the plurality of test signals to the first device;
when at least one of the plurality of test signals cannot be received by the first device, determining that a chip corresponding to the test circuit is in a fault state.
10. The package structure of claim 1, wherein the first pin is a package ball.
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| CN202210853727.9A CN115168122A (en) | 2022-07-11 | 2022-07-11 | Packaging structure for multi-chip module |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116594817A (en) * | 2023-04-26 | 2023-08-15 | 深圳高铂科技有限公司 | Single chip calibration system and method |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116594817A (en) * | 2023-04-26 | 2023-08-15 | 深圳高铂科技有限公司 | Single chip calibration system and method |
| CN116594817B (en) * | 2023-04-26 | 2024-06-14 | 深圳高铂科技有限公司 | Single chip calibration system and method |
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