CN116594817A - Single chip calibration system and method - Google Patents

Single chip calibration system and method Download PDF

Info

Publication number
CN116594817A
CN116594817A CN202310472390.1A CN202310472390A CN116594817A CN 116594817 A CN116594817 A CN 116594817A CN 202310472390 A CN202310472390 A CN 202310472390A CN 116594817 A CN116594817 A CN 116594817A
Authority
CN
China
Prior art keywords
calibration
port
chip
signal
alpg
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN202310472390.1A
Other languages
Chinese (zh)
Other versions
CN116594817B (en
Inventor
薄会健
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shenzhen Gaobo Technology Co ltd
Original Assignee
Shenzhen Gaobo Technology Co ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shenzhen Gaobo Technology Co ltd filed Critical Shenzhen Gaobo Technology Co ltd
Priority to CN202310472390.1A priority Critical patent/CN116594817B/en
Publication of CN116594817A publication Critical patent/CN116594817A/en
Application granted granted Critical
Publication of CN116594817B publication Critical patent/CN116594817B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/2205—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/2273—Test methods
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Tests Of Electronic Circuits (AREA)

Abstract

The application discloses a single chip calibration system and a single chip calibration method, wherein the single chip calibration system comprises electronic equipment, ALPG and calibration equipment, the electronic equipment is connected with the ALPG, the ALPG is connected with chips, each chip comprises a plurality of IO ports, the plurality of IO ports comprise a plurality of groups of IO ports, the nth group of IO ports comprise 2n-1 IO ports, 2n IO ports, 2n+1 IO ports and 2n+2 IO ports, n is a positive integer, the 2n-1 IO ports, the 2n IO ports, 2n+1 IO ports and 2n+2 IO ports are adjacent to each other, and the calibration equipment comprises first calibration equipment and second calibration equipment.

Description

Single chip calibration system and method
Technical Field
The present application relates to the field of chip testing technologies, and in particular, to a system and a method for calibrating a single chip.
Background
Automated test equipment (Automatic Test Equipment, ATE) is a system for automated testing of integrated circuits by means of computers and specialized equipment.
In the field of semiconductor chip testing, during the testing process, each IO port in the chip needs to be calibrated synchronously due to the following reasons:
(1) Ensuring test precision and consistency: through synchronous calibration, each IO port in the chip can be ensured to be simultaneously tested, so that higher testing precision and consistency are obtained;
(2) The test efficiency and the test speed are improved: through synchronous calibration, the test time and cost can be reduced, and the test efficiency and speed are improved. Because the synchronous calibration can reduce the time sequence offset of the signal transmission in the chip, the test margin is improved;
(3) Ensuring the reliability of the test: by means of synchronous calibration, the reliability of the test can be ensured. Because the synchronous calibration can reduce the time sequence error of chip signal transmission, the test error and failure rate are reduced, and the test reliability is improved.
In the field of semiconductor chip testing, synchronous calibration of each IO port is very important, and the testing precision, consistency, efficiency, speed and reliability can be improved, so that better testing results and services are provided for chip manufacturers.
In the prior art, a phase-locked loop and a delay line are generally utilized, and clock signals in a chip are used for synchronously calibrating each IO port in the chip, however, in an actual application scene, due to interference of various environmental factors, the stability of the clock signals is poor, so that calibration errors are increased.
Disclosure of Invention
The invention mainly aims to provide a single-chip calibration system and a single-chip calibration method, which aim to solve the technical problem that in the prior art, in an actual application scene, due to interference of various environmental factors, clock signal stability is poor, and calibration errors are increased.
In order to achieve the above object, a first aspect of the present invention provides a single chip calibration system, including an electronic device, an ALPG and a calibration device, where the electronic device is connected to the ALPG, the ALPG is connected to a chip, the chip is connected to the calibration device, each chip includes a plurality of IO ports, a plurality of IO ports includes a plurality of groups of IO ports, an nth group of IO ports includes a 2n-1 th IO port, a 2n-th IO port, a 2n+1 th IO port and a 2n+2 th IO port, n is a positive integer, the 2n-1 th IO port, the 2n+1 th IO port and the 2n+2 th IO port are adjacent to each other, and the calibration device includes a first calibration device and a second calibration device, where:
the electronic device is used for sending a first control signal to the ALPG, the first control signal is used for sending a first calibration signal to the chip by the ALPG, and the first calibration signal is used for sending the first calibration signal to the first calibration device through the 2n-1 IO port by the chip;
the first calibration device is used for sending a first calibration signal to the chip through the 2 n-th IO port;
the electronic device is further configured to send a second control signal to the ALPG, where the second control signal is used for sending a second calibration signal to the chip by the ALPG, and the second calibration signal is used for sending the second calibration signal to the first calibration device by the chip through 2n+2nd IO ports;
The first calibration device is further configured to send a second calibration signal to the chip through the 2n+1st IO port;
the electronic equipment is also used for determining the first calibration time of the 2n-1 th IO port and the 2n+2 th IO port under the condition that the delay of the 2n-1 th IO port and the delay of the 2n+1 th IO port are the same;
the electronic device is further configured to send a third control signal to the ALPG, where the third control signal is used for the ALPG to send a third calibration signal to the chip, and the third calibration signal is used for the chip to send the third calibration signal to the first calibration device through 2n+3rd IO ports, where the 2n+3rd IO ports are adjacent to the 2n+2nd IO ports;
the first calibration device is further configured to send a third calibration signal to the chip through the 2nth IO port;
the electronic device is further configured to send a fourth control signal to the ALPG, where the fourth control signal is used for sending a fourth calibration signal to the chip by the ALPG, and the fourth calibration signal is used for sending a fourth calibration signal to the first calibration device by the chip through the 2n+2nd IO port;
the first calibration device is further configured to send a fourth calibration signal to the chip through the 2n+1st IO port;
the electronic device is further configured to determine a second calibration time of the 2n+2nd IO port and the 2n+1th IO port when the 2n+2nd IO port and the 2n+3rd IO port have the same delay;
The electronic device is further configured to send a fifth control signal to the ALPG, where the fifth control signal is used for sending a fifth calibration signal to the chip by the ALPG, and the fifth calibration signal is used for sending the fifth calibration signal to the second calibration device by the chip through the 2 n-th IO port;
the second calibration device is used for sending a fifth calibration signal to the chip through the 2n+1st IO port;
the electronic device is further configured to send a sixth control signal to the ALPG, where the sixth control signal is used for the ALPG to send a sixth calibration signal to the chip, and the sixth calibration signal is used for the chip to send the sixth calibration signal to the second calibration device through the 2n+3rd IO port;
the second calibration device is further configured to send a sixth calibration signal to the chip through the 2n+2nd IO port;
the electronic device is further configured to determine a third calibration time of the 2n+1th IO port and the 2n+3rd IO port when the 2n+2th IO port and the 2n+2nd IO port have the same delay;
the electronic device is further configured to send a seventh control signal to the ALPG, where the seventh control signal is used for sending a seventh calibration signal to the chip by the ALPG, and the seventh calibration signal is used for sending a seventh calibration signal to the first calibration device by the chip through the 2n+1th IO port;
the second calibration device is further configured to send a seventh calibration signal to the chip through the 2nth IO port;
The electronic device is further configured to send an eighth control signal to the ALPG, where the eighth control signal is used for the ALPG to send an eighth calibration signal to the chip, and the eighth calibration signal is used for the chip to send the eighth calibration signal to the second calibration device through the 2n+2io ports;
the second calibration device is further configured to send an eighth calibration signal to the chip through the 2n-1 st IO port;
the electronic device is further configured to determine a fourth calibration time of the 2n-1 st IO port and the 2n-th IO port when the 2n+1 th IO port and the 2n+2 nd IO port have the same delay.
The electronic device is further used for determining a fifth calibration time according to the first calibration time and the third calibration time;
the electronic device is further configured to determine a sixth calibration time according to the second calibration time and the fourth calibration time;
the electronic device is further configured to determine a calibration delay according to the fifth calibration time and the sixth calibration time;
and the electronic equipment is also used for calibrating the chip according to the calibration delay.
Optionally, the single chip calibration system further comprises an oscilloscope, wherein: the electronic equipment is also used for sending a ninth control signal to the ALPG, the ninth control signal is used for sending a test signal to the chip by the ALPG, the test signal is used for sending the test signal to the oscilloscope through the test IO port, and the test IO port is any IO port in a plurality of IO ports of the chip; the oscilloscope is used for receiving the test signal; the electronic equipment is also used for determining path delay according to the time of sending the test signal by the test IO port and the time of receiving the test signal by the oscilloscope; the electronic device is further configured to determine a calibration delay based on the fifth calibration time, the sixth calibration time, and the path delay.
Optionally, the single chip calibration system further comprises a connector connected with the chip and the calibration device, wherein: the first calibration signal is used for the chip to send the first calibration signal to the first calibration equipment through the 2n-1 IO port, and comprises the following steps: the first calibration signal is used for the chip to send the first calibration signal to the first calibration device through the 2n-1 IO port through the connector.
Optionally, the chip-to-connector length is equal to the connector-to-first calibration device length.
Optionally, the single chip calibration system further comprises a connector, the connector being connected with the chip and the calibration device, wherein; the fifth calibration signal is used for sending the fifth calibration signal to the second calibration device through the 2 n-th IO port by the chip, and comprises the following steps: the fifth calibration signal is used for the chip to send the fifth calibration signal to the second calibration device through the 2 n-th IO port through the connector.
Optionally, the chip-to-connector length is equal to the connector-to-second calibration device length.
The second aspect of the embodiment of the present application provides a single chip calibration method, where the method is applied to a single chip calibration system including an electronic device and a calibration device, the electronic device is connected to an ALPG, the ALPG is connected to a chip, the chip is connected to the calibration device, each chip includes a plurality of IO ports, a plurality of IO ports includes a plurality of groups of IO ports, an nth group of IO ports includes a 2n-1 th IO port, a 2n-th IO port, a 2n+1th IO port, and a 2n+2nd IO port, where n is a positive integer, and the 2n-1 th IO port, the 2n+1th IO port, and the 2n+2nd IO port are adjacent to each other, and the calibration device includes a first calibration device and a second calibration device, where:
The electronic device sends a first control signal to the ALPG, wherein the first control signal is used for sending a first calibration signal to the chip by the ALPG, and the first calibration signal is used for sending the first calibration signal to the first calibration device through the 2n-1 IO port by the chip;
the first calibration device sends a first calibration signal to the chip through the 2 n-th IO port;
the electronic device sends a second control signal to the ALPG, the second control signal is used for the ALPG to send a second calibration signal to the chip, and the second calibration signal is used for the chip to send the second calibration signal to the first calibration device through 2n+2IO ports;
the first calibration device sends a second calibration signal to the chip through the 2n+1th IO port;
under the condition that the delay of the 2n-1 th IO port and the 2n+1 th IO port is the same, the electronic equipment determines the first calibration time of the 2n-1 th IO port and the 2n+2 th IO port;
the electronic device sends a third control signal to the ALPG, the third control signal is used for the ALPG to send a third calibration signal to the chip, the third calibration signal is used for the chip to send the third calibration signal to the first calibration device through the 2n+3th IO port, and the 2n+3rd IO port is adjacent to the 2n+2nd IO port;
the first calibration device sends a third calibration signal to the chip through the 2 n-th IO port;
The electronic device sends a fourth control signal to the ALPG, wherein the fourth control signal is used for the ALPG to send a fourth calibration signal to the chip, and the fourth calibration signal is used for the chip to send the fourth calibration signal to the first calibration device through the 2n+2IO ports;
the first calibration device sends a fourth calibration signal to the chip through the 2n+1th IO port;
under the condition that the delay of the 2n+2th IO port and the 2n+3rd IO port is the same, the electronic equipment determines the second calibration time of the 2n-th IO port and the 2n+1th IO port;
the electronic device sends a fifth control signal to the ALPG, the fifth control signal is used for the ALPG to send a fifth calibration signal to the chip, and the fifth calibration signal is used for the chip to send the fifth calibration signal to the second calibration device through the 2 n-th IO port;
the second calibration device sends a fifth calibration signal to the chip through a 2n+1th IO port;
the electronic device sends a sixth control signal to the ALPG, wherein the sixth control signal is used for the ALPG to send a sixth calibration signal to the chip, and the sixth calibration signal is used for the chip to send the sixth calibration signal to the second calibration device through 2n+3IO ports;
the second calibration device sends a sixth calibration signal to the chip through a 2n+2th IO port;
under the condition that the delay of the 2n+1th IO port and the 2n+2nd IO port is the same, the electronic equipment determines the third calibration time of the 2n-th IO port and the 2n+3rd IO port;
The electronic device sends a seventh control signal to the ALPG, the seventh control signal is used for the ALPG to send a seventh calibration signal to the chip, and the seventh calibration signal is used for the chip to send the seventh calibration signal to the first calibration device through the 2n+1th IO port;
the second calibration device sends a seventh calibration signal to the chip through the 2 n-th IO port;
the electronic device sends an eighth control signal to the ALPG, the eighth control signal is used for the ALPG to send an eighth calibration signal to the chip, and the eighth calibration signal is used for the chip to send the eighth calibration signal to the second calibration device through the 2n+2IO ports;
the second calibration device sends an eighth calibration signal to the chip through the 2n-1 th IO port;
and the electronic equipment determines fourth calibration time of the 2n-1 th IO port and the 2n-th IO port under the condition that the 2n+1 th IO port and the 2n+2 th IO port have the same delay.
The electronic device determines a fifth calibration time according to the first calibration time and the third calibration time;
the electronic device determines a sixth calibration time according to the second calibration time and the fourth calibration time;
the electronic device determines a calibration delay according to the fifth calibration time and the sixth calibration time;
the electronic device calibrates the chip according to the calibration delay.
From the above, the application utilizes the principle that the delays of two adjacent IO ports are similar, and in the same calibration device, all IO ports of a control chip are used for receiving and transmitting calibration signals, delay time of different IO ports is recorded, the maximum delay is determined as the reference delay of the chip, other IO ports are controlled to calibrate according to the maximum delay, and the delay time of all IO ports is ensured to be in a controllable range, so that the accuracy of chip calibration is improved.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings used in the embodiments or the description of the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic diagram of an embodiment of a single chip calibration system according to an embodiment of the present application;
FIG. 2 is a schematic diagram of an embodiment of another single chip calibration system according to an embodiment of the present application;
FIG. 3 is a schematic diagram of an embodiment of a chip pin according to an embodiment of the present application;
FIG. 4 is a schematic diagram of another embodiment of a chip pin according to an embodiment of the present application;
fig. 5 is a schematic structural diagram of another embodiment of a single-chip calibration system according to an embodiment of the present application.
Detailed Description
In the following description, for purposes of explanation and not limitation, specific details are set forth such as the particular system architecture, techniques, etc., in order to provide a thorough understanding of the embodiments of the present application. It will be apparent, however, to one skilled in the art that the present application may be practiced in other embodiments that depart from these specific details. In other instances, detailed descriptions of well-known systems, devices, circuits, and methods are omitted so as not to obscure the description of the present application with unnecessary detail.
It should be understood that the terms "comprises" and/or "comprising," when used in this specification and the appended claims, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
It is also to be understood that the terminology used in the description of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used in this specification and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.
It should be further understood that the term "and/or" as used in the present specification and the appended claims refers to any and all possible combinations of one or more of the associated listed items, and includes such combinations.
As used in this specification and the appended claims, the term "if" may be interpreted in context as "when …" or "upon" or "in response to a determination" or "in response to detection. Similarly, the phrase "if a condition or event described is determined" or "if a condition or event described is detected" may be interpreted in the context of meaning "upon determination" or "in response to determination" or "upon detection of a condition or event described" or "in response to detection of a condition or event described".
The following description of the embodiments of the present invention will be made more fully hereinafter with reference to the accompanying drawings, in which embodiments of the invention are shown, it being evident that the embodiments described are only some, but not all embodiments of the invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention, but the present invention may be practiced in other ways other than those described herein, and persons skilled in the art will readily appreciate that the present invention is not limited to the specific embodiments disclosed below.
In order to solve the problems in the prior art, an embodiment of the present invention provides a single chip calibration system, as shown in fig. 1, including an electronic device, an ALPG algorithm pattern generator (Algorithmic Pattern Generator, ALPG) and a calibration device, where the electronic device is connected with an ALPG, the ALPG is connected with a chip, the chip is connected with the calibration device, each chip includes a plurality of IO ports, a plurality of IO ports includes a plurality of groups of IO ports, an nth group of IO ports includes a 2n-1 th IO port, a 2n+1th IO port and a 2n+2nd IO port, n is a positive integer, the 2n-1 th IO port, the 2n n_io port, 2n+1th IO port and 2n+2nd IO port are adjacent to each other, and the calibration device includes a first calibration device and a second calibration device, where:
The electronic device is used for sending a first control signal to the ALPG, the first control signal is used for sending a first calibration signal to the chip by the ALPG, and the first calibration signal is used for sending the first calibration signal to the first calibration device through the 2n-1 IO port by the chip;
the first calibration device is used for sending a first calibration signal to the chip through the 2 n-th IO port;
the electronic device is further configured to send a second control signal to the ALPG, where the second control signal is used for sending a second calibration signal to the chip by the ALPG, and the second calibration signal is used for sending the second calibration signal to the first calibration device by the chip through 2n+2nd IO ports;
the first calibration device is further configured to send a second calibration signal to the chip through the 2n+1st IO port;
the electronic equipment is also used for determining the first calibration time of the 2n-1 th IO port and the 2n+2 th IO port under the condition that the delay of the 2n-1 th IO port and the delay of the 2n+1 th IO port are the same;
the electronic device is further configured to send a third control signal to the ALPG, where the third control signal is used for the ALPG to send a third calibration signal to the chip, and the third calibration signal is used for the chip to send the third calibration signal to the first calibration device through 2n+3rd IO ports, where the 2n+3rd IO ports are adjacent to the 2n+2nd IO ports;
The first calibration device is further configured to send a third calibration signal to the chip through the 2nth IO port;
the electronic device is further configured to send a fourth control signal to the ALPG, where the fourth control signal is used for sending a fourth calibration signal to the chip by the ALPG, and the fourth calibration signal is used for sending a fourth calibration signal to the first calibration device by the chip through the 2n+2nd IO port;
the first calibration device is further configured to send a fourth calibration signal to the chip through the 2n+1st IO port;
the electronic device is further configured to determine a second calibration time of the 2n+2nd IO port and the 2n+1th IO port when the 2n+2nd IO port and the 2n+3rd IO port have the same delay;
the electronic device is further configured to send a fifth control signal to the ALPG, where the fifth control signal is used for sending a fifth calibration signal to the chip by the ALPG, and the fifth calibration signal is used for sending the fifth calibration signal to the second calibration device by the chip through the 2 n-th IO port;
the second calibration device is used for sending a fifth calibration signal to the chip through the 2n+1st IO port;
the electronic device is further configured to send a sixth control signal to the ALPG, where the sixth control signal is used for the ALPG to send a sixth calibration signal to the chip, and the sixth calibration signal is used for the chip to send the sixth calibration signal to the second calibration device through the 2n+3rd IO port;
The second calibration device is further configured to send a sixth calibration signal to the chip through the 2n+2nd IO port;
the electronic device is further configured to determine a third calibration time of the 2n+1th IO port and the 2n+3rd IO port when the 2n+2th IO port and the 2n+2nd IO port have the same delay;
the electronic device is further configured to send a seventh control signal to the ALPG, where the seventh control signal is used for sending a seventh calibration signal to the chip by the ALPG, and the seventh calibration signal is used for sending a seventh calibration signal to the first calibration device by the chip through the 2n+1th IO port;
the second calibration device is further configured to send a seventh calibration signal to the chip through the 2nth IO port;
the electronic device is further configured to send an eighth control signal to the ALPG, where the eighth control signal is used for the ALPG to send an eighth calibration signal to the chip, and the eighth calibration signal is used for the chip to send the eighth calibration signal to the second calibration device through the 2n+2io ports;
the second calibration device is further configured to send an eighth calibration signal to the chip through the 2n-1 st IO port;
the electronic device is further configured to determine a fourth calibration time of the 2n-1 st IO port and the 2n-th IO port when the 2n+1 th IO port and the 2n+2 nd IO port have the same delay.
The electronic device is further configured to determine a fifth calibration time according to the first calibration time and the third calibration time, determine a sixth calibration time according to the second calibration time and the fourth calibration time, determine a calibration delay according to the fifth calibration time and the sixth calibration time, and calibrate the chip according to the calibration delay.
In some embodiments, the maximum delay is determined from the first calibration time, the second calibration time, the third calibration time, and the first calibration time, the maximum delay is determined as a calibration delay, and the chip is calibrated according to the calibration delay.
According to the application, the characteristic that the internal delays of two adjacent IO port chips are similar is utilized, namely, when the chips are connected with first calibration equipment, the internal delays of the chips of the 2n-th IO port and the 2n+1st IO port are the same, the internal delays of the chips of the 2n+2nd IO port and the 2n+3rd IO port are the same, when the chips are connected with second calibration equipment, the internal delays of the chips of the 2n+1st IO port and the 2n+2nd IO port are the same, and in the same calibration equipment, all IO ports transmit and receive calibration signals through the control chip, delay time of different IO ports is recorded, the maximum delay is determined as the reference delay of the chip, and other IO ports are controlled to calibrate according to the maximum delay, so that the delay time of all IO ports is ensured to be in a controllable range, and the accuracy of chip calibration is improved.
In some embodiments, as shown in fig. 2 and 3, the chip (ASIC) includes 40 IO ports (0-39), and when the chip is connected to the first calibration device (TYPE a) through the connector, the first calibration signal is used by the chip to send the first calibration signal to the first calibration device through the 0 th IO port; the first calibration device sends a first calibration signal to the chip through the 1 st IO port; the second calibration signal is used for The chip sends a second calibration signal to the first calibration device through the 3 rd IO port; the first calibration device sends a second calibration signal to the chip through the 2 nd IO port; under the condition that the delay of the 1 st IO port and the 2 nd IO port is the same, the electronic equipment determines the first calibration time delta of the 0 th IO port and the 3 rd IO port 0-3 Similarly, delta can be obtained 2-5 、…、Δ 36-39 Wherein con is a connector.
When the chip is connected with the second calibration equipment (TYPE B) through the connector, the fifth calibration signal is used for sending the fifth calibration signal to the second calibration equipment through the 1 st IO port; the second calibration device sends a fifth calibration signal to the chip through the 2 nd IO port; the sixth calibration signal is used for the chip to send the sixth calibration signal to the second calibration device through the 4 th IO port; the second calibration device sends a sixth calibration signal to the chip through a 3 rd IO port; under the condition that the delay of the 2 nd IO port and the 3 rd IO port is the same, the electronic equipment determines the third calibration time delta of the 1 st IO port and the 4 th IO port 1-4 、…、Δ 35-38 。
As shown in fig. 4, when the chip is connected to the first calibration device (TYPE a) through the connector, the third calibration signal is used for the chip to send the third calibration signal to the first calibration device through the 4 th IO port, where the 4 th IO port is adjacent to the 3 rd IO port; the first calibration device sends a third calibration signal to the chip through the 1 st IO port; the fourth calibration signal is used for the chip to send the fourth calibration signal to the first calibration device through the 3 rd IO port; the first calibration device sends a fourth calibration signal to the chip through the 2 nd IO port; the electronic equipment determines a second calibration time delta of the 1 st IO port and the 2 nd IO port under the condition that the delay of the 3 rd IO port and the 4 th IO port is the same 1-2 。
When the chip is connected with second calibration equipment (TYPE B) through the connector, the seventh calibration signal is used for the chip to send the seventh calibration signal to the first calibration equipment through the 2 nd IO port, and the second calibration equipment sends the seventh calibration signal to the chip through the 1 st IO port; the eighth calibration signal is used for the chip to send the eighth calibration signal to the second calibration device through the 3 rd IO port; the second calibration device sends an eighth calibration to the chip through the 0 th IO portA quasi signal; under the condition that the delay of the 2 nd IO port and the 3 rd IO port is the same, the electronic equipment determines the fourth calibration time delta of the 0 th IO port and the 1 st IO port 0-1 。
X can be obtained from FIG. 3 0 、x 3 …、x 39 And x 1 、x 4 …、x 37 Further, by FIG. 4, x can be obtained 0 、x 1 And x 2 And further obtaining a delay relation of 40 pins, obtaining the maximum delay, and synchronously calibrating all pins of the chip according to the maximum delay.
In some embodiments, as shown in fig. 5, the single chip calibration system further comprises an oscilloscope, wherein: the electronic equipment is also used for sending a ninth control signal to the ALPG, the ninth control signal is used for sending a test signal to the chip by the ALPG, the test signal is used for sending the test signal to the oscilloscope through the test IO port, and the test IO port is any IO port in a plurality of IO ports of the chip; the oscilloscope is used for receiving the test signal; the electronic equipment is also used for determining path delay according to the time of sending the test signal by the test IO port and the time of receiving the test signal by the oscilloscope; the electronic device is further configured to determine a calibration delay based on the fifth calibration time, the sixth calibration time, and the path delay, where con is the connector.
The first calibration time, the second calibration time, the third calibration time, and the fourth calibration time all include test delays, and in order to reduce the influence of the path delays, the path delays in the first calibration time, the second calibration time, the third calibration time, and the fourth calibration time need to be subtracted, and then the determination of the calibration delays is performed.
Specifically, the single chip ASIC simultaneously transmits square waves, the phase difference Δps is tested two by two with a high speed oscilloscope, all IOs are simultaneously transmitted, and the oscilloscope decision level is consistent with the DUT decision level: test 0/1, yielding Δ0-1=x0-X1; test 1/2, resulting in Δ1-2=x1-X2; and so on, the rank sum delta value of all pins 0-39 is obtained.
In some embodiments, the single chip calibration system further comprises a connector connected with the chip and the calibration device, wherein: the first calibration signal is used for the chip to send the first calibration signal to the first calibration equipment through the 2n-1 IO port, and comprises the following steps: the first calibration signal is used for the chip to send the first calibration signal to the first calibration device through the 2n-1 IO port through the connector.
In some embodiments, the single chip calibration system further comprises a connector, the connector being connected to the chip and the calibration device, wherein; the fifth calibration signal is used for sending the fifth calibration signal to the second calibration device through the 2 n-th IO port by the chip, and comprises the following steps: the fifth calibration signal is used for the chip to send the fifth calibration signal to the second calibration device through the 2 n-th IO port through the connector.
In some embodiments, the chip-to-connector length is equal to the connector-to-second calibration device length.
Consistent with the foregoing, the method for calibrating a single chip provided in the embodiment of the present application is applied to a single chip calibration system including an electronic device and a calibration device, where the electronic device is connected to an ALPG, the ALPG is connected to a chip, the chip is connected to the calibration device, each chip includes a plurality of IO ports, a plurality of IO ports includes a plurality of groups of IO ports, an nth group of IO ports includes a 2n-1 th IO port, a 2n-th IO port, a 2n+1th IO port, and a 2n+2nd IO port, n is a positive integer, the 2n-1 th IO port, the 2n+1th IO port, and the 2n+2nd IO port are adjacent to each other, and the calibration device includes a first calibration device and a second calibration device, where:
the electronic device sends a first control signal to the ALPG, wherein the first control signal is used for sending a first calibration signal to the chip by the ALPG, and the first calibration signal is used for sending the first calibration signal to the first calibration device through the 2n-1 IO port by the chip;
the first calibration device sends a first calibration signal to the chip through the 2 n-th IO port;
the electronic device sends a second control signal to the ALPG, the second control signal is used for the ALPG to send a second calibration signal to the chip, and the second calibration signal is used for the chip to send the second calibration signal to the first calibration device through 2n+2IO ports;
The first calibration device sends a second calibration signal to the chip through the 2n+1th IO port;
under the condition that the delay of the 2n-1 th IO port and the 2n+1 th IO port is the same, the electronic equipment determines the first calibration time of the 2n-1 th IO port and the 2n+2 th IO port;
the electronic device sends a third control signal to the ALPG, the third control signal is used for the ALPG to send a third calibration signal to the chip, the third calibration signal is used for the chip to send the third calibration signal to the first calibration device through the 2n+3th IO port, and the 2n+3rd IO port is adjacent to the 2n+2nd IO port;
the first calibration device sends a third calibration signal to the chip through the 2 n-th IO port;
the electronic device sends a fourth control signal to the ALPG, wherein the fourth control signal is used for the ALPG to send a fourth calibration signal to the chip, and the fourth calibration signal is used for the chip to send the fourth calibration signal to the first calibration device through the 2n+2IO ports;
the first calibration device sends a fourth calibration signal to the chip through the 2n+1th IO port;
under the condition that the delay of the 2n+2th IO port and the 2n+3rd IO port is the same, the electronic equipment determines the second calibration time of the 2n-th IO port and the 2n+1th IO port;
the electronic device sends a fifth control signal to the ALPG, the fifth control signal is used for the ALPG to send a fifth calibration signal to the chip, and the fifth calibration signal is used for the chip to send the fifth calibration signal to the second calibration device through the 2 n-th IO port;
The second calibration device sends a fifth calibration signal to the chip through a 2n+1th IO port;
the electronic device sends a sixth control signal to the ALPG, wherein the sixth control signal is used for the ALPG to send a sixth calibration signal to the chip, and the sixth calibration signal is used for the chip to send the sixth calibration signal to the second calibration device through 2n+3IO ports;
the second calibration device sends a sixth calibration signal to the chip through a 2n+2th IO port;
under the condition that the delay of the 2n+1th IO port and the 2n+2nd IO port is the same, the electronic equipment determines the third calibration time of the 2n-th IO port and the 2n+3rd IO port;
the electronic device sends a seventh control signal to the ALPG, the seventh control signal is used for the ALPG to send a seventh calibration signal to the chip, and the seventh calibration signal is used for the chip to send the seventh calibration signal to the first calibration device through the 2n+1th IO port;
the second calibration device sends a seventh calibration signal to the chip through the 2 n-th IO port;
the electronic device sends an eighth control signal to the ALPG, the eighth control signal is used for the ALPG to send an eighth calibration signal to the chip, and the eighth calibration signal is used for the chip to send the eighth calibration signal to the second calibration device through the 2n+2IO ports;
the second calibration device sends an eighth calibration signal to the chip through the 2n-1 th IO port;
And the electronic equipment determines fourth calibration time of the 2n-1 th IO port and the 2n-th IO port under the condition that the 2n+1 th IO port and the 2n+2 th IO port have the same delay.
The electronic device determines a fifth calibration time according to the first calibration time and the third calibration time;
the electronic device determines a sixth calibration time according to the second calibration time and the fourth calibration time;
the electronic device determines a calibration delay according to the fifth calibration time and the sixth calibration time;
the electronic device calibrates the chip according to the calibration delay.
In some embodiments, the electronic device determines a maximum delay from the first calibration time, the second calibration time, the third calibration time, and the first calibration time, determines the maximum delay as a calibration delay, and calibrates the chip according to the calibration delay.
Although the application is described herein in connection with the embodiments, other variations to the disclosed embodiments can be understood and effected by those skilled in the art in practicing the claimed application, from a study of the drawings, the disclosure, and the appended claims. In the claims, the word "comprising" does not exclude other elements or steps, and the "a" or "an" does not exclude a plurality. A single processor or other unit may fulfill the functions of several items recited in the claims. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage.
It will be apparent to those skilled in the art that embodiments of the present application may be provided as a method, apparatus (device), or computer program product. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein. A computer program may be stored/distributed on a suitable medium supplied together with or as part of other hardware, but may also take other forms, such as via the Internet or other wired or wireless telecommunication systems.
The present application is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (devices) and computer program products according to embodiments of the application. It will be understood that each flow and/or block of the flowchart illustrations and/or block diagrams, and combinations of flows and/or blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable information prompting device to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable information prompting device, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks. These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable information reminder device to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable information-bearing device to cause a series of operational steps to be performed on the computer or other programmable device to produce a computer implemented process such that the instructions which execute on the computer or other programmable device provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
Although the application has been described in connection with specific features and embodiments thereof, it will be apparent that various modifications and combinations can be made without departing from the spirit and scope of the application. Accordingly, the specification and drawings are merely exemplary illustrations of the present application as defined in the appended claims and are considered to cover any and all modifications, variations, combinations, or equivalents that fall within the scope of the application. It will be apparent to those skilled in the art that various modifications and variations can be made to the present application without departing from the spirit or scope of the application. Thus, it is intended that the present application also include such modifications and alterations insofar as they come within the scope of the appended claims or the equivalents thereof.

Claims (7)

1. The utility model provides a single chip calibration system, its characterized in that includes electronic equipment, ALPG and calibration equipment, electronic equipment connects the ALPG, the ALPG is connected the chip, the chip with calibration equipment is connected, every the chip includes a plurality of IO mouth, including multiunit IO mouth in the plurality of IO mouths, including 2-1 IO mouth, 2 nd IO mouth, 2+1 IO mouth and 2+2 IO mouth in the nth group IO mouth in the multiunit IO mouth, n is positive integer, 2-1 IO mouth 2 nd IO mouth 2+1 IO mouth and 2+2 IO mouth are adjacent each other, calibration equipment includes first calibration equipment and second calibration equipment, wherein:
the electronic device is configured to send a first control signal to the ALPG, where the first control signal is used for the ALPG to send a first calibration signal to the chip, and the first calibration signal is used for the chip to send the first calibration signal to the first calibration device through a 2 nd-1 st IO port;
the first calibration device is configured to send the first calibration signal to the chip through the 2 nd IO port;
the electronic device is further configured to send a second control signal to the ALPG, where the second control signal is used for the ALPG to send a second calibration signal to the chip, and the second calibration signal is used for the chip to send the second calibration signal to the first calibration device through a 2+2th IO port;
The first calibration device is further configured to send the second calibration signal to the chip through the 2+1st IO port;
the electronic device is further configured to determine a first calibration time of the 2 nd-1 st IO port and the 2 nd+2 nd IO port when the delays of the 2 nd IO port and the 2 nd+1 st IO port are the same;
the electronic device is further configured to send a third control signal to the ALPG, where the third control signal is used for the ALPG to send a third calibration signal to the chip, where the third calibration signal is used for the chip to send the third calibration signal to the first calibration device through a 2+3rd IO port, where the 2+3rd IO port is adjacent to the 2+2nd IO port;
the first calibration device is further configured to send the third calibration signal to the chip through the 2 nd IO port;
the electronic device is further configured to send a fourth control signal to the ALPG, where the fourth control signal is used for the ALPG to send a fourth calibration signal to the chip, and the fourth calibration signal is used for the chip to send the fourth calibration signal to the first calibration device through a 2+2th IO port;
the first calibration device is further configured to send the fourth calibration signal to the chip through the 2+1st IO port;
The electronic device is further configured to determine a second calibration time of the 2 nd IO port and the 2+1 th IO port when delays of the 2+2 nd IO port and the 2+3 rd IO port are the same;
the electronic device is further configured to send a fifth control signal to the ALPG, where the fifth control signal is used for the ALPG to send a fifth calibration signal to the chip, and the fifth calibration signal is used for the chip to send the fifth calibration signal to the second calibration device through a 2 nd IO port;
the second calibration device is configured to send the fifth calibration signal to the chip through the 2+1st IO port;
the electronic device is further configured to send a sixth control signal to the ALPG, where the sixth control signal is used for the ALPG to send a sixth calibration signal to the chip, and the sixth calibration signal is used for the chip to send the sixth calibration signal to the second calibration device through a 2+3 th IO port;
the second calibration device is further configured to send the sixth calibration signal to the chip through the 2+2nd IO port;
the electronic device is further configured to determine a third calibration time of the 2 nd IO port and the 2+3 rd IO port when delays of the 2+1 th IO port and the 2+2 nd IO port are the same;
The electronic device is further configured to send a seventh control signal to the ALPG, where the seventh control signal is used for the ALPG to send a seventh calibration signal to the chip, and the seventh calibration signal is used for the chip to send the seventh calibration signal to the first calibration device through a 2+1st IO port;
the second calibration device is further configured to send the seventh calibration signal to the chip through the 2 nd IO port;
the electronic device is further configured to send an eighth control signal to the ALPG, where the eighth control signal is used for the ALPG to send an eighth calibration signal to the chip, and the eighth calibration signal is used for the chip to send the eighth calibration signal to the second calibration device through a 2+2th IO port;
the second calibration device is further configured to send the eighth calibration signal to the chip through the 2 nd-1 st IO port;
the electronic device is further configured to determine a fourth calibration time of the 2-1 st IO port and the 2 nd IO port when delays of the 2+1 st IO port and the 2+2 nd IO port are the same;
the electronic equipment is further used for determining a fifth calibration time according to the first calibration time and the third calibration time;
The electronic device is further configured to determine a sixth calibration time according to the second calibration time and the fourth calibration time;
the electronic device is further configured to determine a calibration delay according to the fifth calibration time and the sixth calibration time;
the electronic device is further configured to calibrate the chip according to the calibration delay.
2. The single chip calibration system of claim 1, further comprising an oscilloscope, wherein:
the electronic device is further configured to send a ninth control signal to the ALPG, where the ninth control signal is used for the ALPG to send a test signal to the chip, the test signal is used for the chip to send the test signal to the oscilloscope through a test IO port, and the test IO port is any one of a plurality of IO ports of the chip;
the oscilloscope is used for receiving the test signal;
the electronic equipment is also used for determining path delay according to the time of the test IO port for sending the test signal and the time of the oscilloscope for receiving the test signal;
the electronic device is further configured to determine the calibration delay based on the fifth calibration time, the sixth calibration time, and the path delay.
3. The single chip calibration system of claim 1, further comprising a connector connected with the chip and the calibration device, wherein:
the first calibration signal is used for the chip to send the first calibration signal to the first calibration device through the 2 nd-1 st IO port, and includes:
the first calibration signal is used for the chip to send the first calibration signal to the first calibration device through the connector through the 2 nd-1 st IO port.
4. A single chip calibration system according to claim 3, wherein the length of the chip to the connector is equal to the length of the connector to the first calibration device.
5. The single chip calibration system of claim 1, further comprising a connector connected to the chip and the calibration device, wherein;
the fifth calibration signal is used for the chip to send the fifth calibration signal to the second calibration device through the 2 nd IO port, and includes:
the fifth calibration signal is used for the chip to send the fifth calibration signal to the second calibration device through the connector via the 2 nd IO port.
6. The single chip calibration system of claim 5, wherein the length of the chip to the connector is equal to the length of the connector to the second calibration device.
7. The single chip calibration method is characterized in that the method is applied to a single chip calibration system comprising electronic equipment and calibration equipment, the electronic equipment is connected with ALPG, the ALPG is connected with the chips, the chips are connected with the calibration equipment, each chip comprises a plurality of IO ports, the plurality of IO ports comprise a plurality of groups of IO ports, the nth group of IO ports comprise 2-1 IO ports, 2 nd IO ports, 2+1 th IO ports and 2+2 nd IO ports, n is a positive integer, the 2-1 nd IO ports, the 2 nd IO ports, the 2+1 th IO ports and the 2+2 nd IO ports are adjacent to each other, and the calibration equipment comprises first calibration equipment and second calibration equipment, wherein:
the electronic device sends a first control signal to the ALPG, wherein the first control signal is used for sending a first calibration signal to the chip by the ALPG, and the first calibration signal is used for sending the first calibration signal to the first calibration device by the chip through a 2 nd-1 st IO port;
The first calibration device sends the first calibration signal to the chip through the 2 nd IO port;
the electronic device sends a second control signal to the ALPG, wherein the second control signal is used for sending a second calibration signal to the chip by the ALPG, and the second calibration signal is used for sending the second calibration signal to the first calibration device by the chip through a 2+2th IO port;
the first calibration device sends the second calibration signal to the chip through the 2+1st IO port;
the electronic equipment determines first calibration time of the 2 nd-1 st IO port and the 2+2 nd IO port under the condition that the delay of the 2 nd IO port and the delay of the 2+1 th IO port are the same;
the electronic device sends a third control signal to the ALPG, wherein the third control signal is used for sending a third calibration signal to the chip by the ALPG, the third calibration signal is used for sending the third calibration signal to the first calibration device by the chip through a 2+3rd IO port, and the 2+3rd IO port is adjacent to the 2+2nd IO port;
the first calibration device sends the third calibration signal to the chip through the 2 nd IO port;
The electronic device sends a fourth control signal to the ALPG, wherein the fourth control signal is used for sending a fourth calibration signal to the chip by the ALPG, and the fourth calibration signal is used for sending the fourth calibration signal to the first calibration device by the chip through a 2+2th IO port;
the first calibration device sends the fourth calibration signal to the chip through the 2+1st IO port;
the electronic device determines second calibration time of the 2 nd IO port and the 2+1 th IO port under the condition that delay of the 2+2 th IO port and delay of the 2+3 th IO port are the same;
the electronic device sends a fifth control signal to the ALPG, wherein the fifth control signal is used for sending a fifth calibration signal to the chip by the ALPG, and the fifth calibration signal is used for sending the fifth calibration signal to the second calibration device by the chip through a 2 nd IO port;
the second calibration device sends the fifth calibration signal to the chip through the 2+1st IO port;
the electronic device sends a sixth control signal to the ALPG, wherein the sixth control signal is used for sending a sixth calibration signal to the chip by the ALPG, and the sixth calibration signal is used for sending the sixth calibration signal to the second calibration device by the chip through a 2+3 IO port;
The second calibration device sends the sixth calibration signal to the chip through the 2+2nd IO port;
the electronic device determines a third calibration time of the 2 nd IO port and the 2+3 rd IO port under the condition that the delay of the 2+1 th IO port and the delay of the 2+2 nd IO port are the same;
the electronic device sends a seventh control signal to the ALPG, wherein the seventh control signal is used for sending a seventh calibration signal to the chip by the ALPG, and the seventh calibration signal is used for sending the seventh calibration signal to the first calibration device by the chip through a 2+1th IO port;
the second calibration device sends the seventh calibration signal to the chip through the 2 nd IO port;
the electronic device sends an eighth control signal to the ALPG, wherein the eighth control signal is used for sending an eighth calibration signal to the chip by the ALPG, and the eighth calibration signal is used for sending the eighth calibration signal to the second calibration device by the chip through a 2+2th IO port;
the second calibration device sends the eighth calibration signal to the chip through the 2 nd-1 st IO port;
the electronic equipment determines fourth calibration time of the 2-1 st IO port and the 2 nd IO port under the condition that the delay of the 2+1 st IO port and the delay of the 2+2 nd IO port are the same;
The electronic equipment determines a fifth calibration time according to the first calibration time and the third calibration time;
the electronic equipment determines a sixth calibration time according to the second calibration time and the fourth calibration time;
the electronic device determines a calibration delay according to the fifth calibration time and the sixth calibration time;
and the electronic equipment calibrates the chip according to the calibration delay.
CN202310472390.1A 2023-04-26 2023-04-26 Single chip calibration system and method Active CN116594817B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202310472390.1A CN116594817B (en) 2023-04-26 2023-04-26 Single chip calibration system and method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202310472390.1A CN116594817B (en) 2023-04-26 2023-04-26 Single chip calibration system and method

Publications (2)

Publication Number Publication Date
CN116594817A true CN116594817A (en) 2023-08-15
CN116594817B CN116594817B (en) 2024-06-14

Family

ID=87598333

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202310472390.1A Active CN116594817B (en) 2023-04-26 2023-04-26 Single chip calibration system and method

Country Status (1)

Country Link
CN (1) CN116594817B (en)

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20100034414A (en) * 2008-09-24 2010-04-01 주식회사 하이닉스반도체 Apparatus and method for testing setup/hold time
CN110716120A (en) * 2018-07-12 2020-01-21 澜起科技股份有限公司 Calibration method for channel delay deviation of automatic chip test equipment
CN115168122A (en) * 2022-07-11 2022-10-11 上海壁仞智能科技有限公司 Packaging structure for multi-chip module
CN115639458A (en) * 2022-11-02 2023-01-24 北京紫光芯能科技有限公司 Chip parameter calibration method, calibration interface controller and chip
CN115932541A (en) * 2022-12-01 2023-04-07 重庆物奇科技有限公司 Chip testing method and device, electronic equipment and computer readable storage medium

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20100034414A (en) * 2008-09-24 2010-04-01 주식회사 하이닉스반도체 Apparatus and method for testing setup/hold time
CN110716120A (en) * 2018-07-12 2020-01-21 澜起科技股份有限公司 Calibration method for channel delay deviation of automatic chip test equipment
CN115168122A (en) * 2022-07-11 2022-10-11 上海壁仞智能科技有限公司 Packaging structure for multi-chip module
CN115639458A (en) * 2022-11-02 2023-01-24 北京紫光芯能科技有限公司 Chip parameter calibration method, calibration interface controller and chip
CN115932541A (en) * 2022-12-01 2023-04-07 重庆物奇科技有限公司 Chip testing method and device, electronic equipment and computer readable storage medium

Also Published As

Publication number Publication date
CN116594817B (en) 2024-06-14

Similar Documents

Publication Publication Date Title
US6477674B1 (en) Method and apparatus for conducting input/output loop back tests using a local pattern generator and delay elements
CN106415293B (en) The timing margin adjustment based on duty ratio for I/O AC timing
US7574632B2 (en) Strobe technique for time stamping a digital signal
US7984369B2 (en) Concurrent code checker and hardware efficient high-speed I/O having built-in self-test and debug features
US7573957B2 (en) Strobe technique for recovering a clock in a digital signal
EP1715355B1 (en) Testing a device under test by sampling its clock and data signal
US10024906B2 (en) Timing skew characterization apparatus and method
US7447958B2 (en) Parallel input/output self-test circuit and method
WO2007038339A2 (en) Strobe technique for recovering a clock in a digital signal
JP4782271B2 (en) Semiconductor device testing method and semiconductor device testing equipment
US20080181047A1 (en) Semiconductor device
US9043662B2 (en) Double data rate memory physical interface high speed testing using self checking loopback
US5256964A (en) Tester calibration verification device
CN116594817B (en) Single chip calibration system and method
US9837170B2 (en) Systems and methods for testing performance of memory modules
US7532995B1 (en) Interpolator testing circuit
US7409308B2 (en) Method and device for verifying output signals of an integrated circuit
US6883127B2 (en) Comparison circuit and method for verification of scan data
CN116679186B (en) Multi-chip calibration system and method
US7401272B1 (en) Apparatus and method for high speed sampling or testing of data signals using automated testing equipment
US7830737B2 (en) SMI memory read data capture margin characterization circuits and methods
CN108155979B (en) Detection equipment
JPH0429991B2 (en)
CN116665747A (en) Internal data availability for system debugging
CN106526336A (en) Time string measuring method

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant