CN115150343B

CN115150343B - Exchange chip verification platform device and method based on UVM

Info

Publication number: CN115150343B
Application number: CN202211076121.5A
Authority: CN
Inventors: 朱珂; 黑建平; 杨晓龙; 钟丹; 徐庆阳; 刘颜鹏; 朱婧瑀; 曹睿
Original assignee: Jingxin Microelectronics Technology Tianjin Co Ltd
Current assignee: Jingxin Microelectronics Technology Tianjin Co Ltd
Priority date: 2022-09-05
Filing date: 2022-09-05
Publication date: 2023-01-03
Anticipated expiration: 2042-09-05
Also published as: CN115150343A

Abstract

The disclosure provides a switching chip verification platform device and method based on UVM. According to the method, a hardware description language such as system verilog is used for building a reference model, the iSLIP function is realized quickly, the reference model can simulate the function of a DUT easily, therefore, the DUT can be verified quickly, and therefore whether the performance of the DUT reaches the standard or not and whether the design meets the expectation or not can be judged efficiently.

Description

Exchange chip verification platform device and method based on UVM

Technical Field

The disclosure relates to the technical field of chip verification, in particular to a switching chip verification platform device and method based on UVM.

Background

The switch chip is one of the switch core chips. Some current switching chips, such as Crossbar (Crossbar) chips, are applied to the iSLIP algorithm. The purpose of the iSLIP (iterative round-robin matching with slot) algorithm is to match the input and output ports of an input queue scheduler efficiently, fairly and quickly. The method is an iteration algorithm, and in each scheduling period, a plurality of iterations are adopted to select the configuration of a cross switch, so that an input port and an output port are matched as much as possible. The iSLIP algorithm uses a Round-Robin Matching RRM (Round-Robin Matching) algorithm, which is a priority Round-Robin Matching algorithm, to arbitrate matches between input/output ports to schedule each active input port and output port in turn. All input ports and output ports are unmatched at the beginning of each iteration, and the unmatched input ports and output ports can participate in the next matching in the process of each iteration, namely, extra connections are added in each successful iteration. Each output port has a grant arbiter and each input port has an accept arbiter.

In the chip design stage, the prior art usually adopts a hardware description language such as verilog to implement the function of iSLIP. However, the prior art generally only considers the implementation of iSLIP function by verilog code, and does not consider whether the performance (e.g. throughput, transmission rate) is up to standard.

Disclosure of Invention

The disclosure provides a switching chip verification platform device and method based on UVM.

In a first aspect, the present disclosure provides a UVM-based switching chip verification platform apparatus, where a switching chip employs an iSLIP algorithm to schedule a plurality of input ports and a plurality of output ports, and the UVM-based switching chip verification platform apparatus includes: the device comprises a sending module, a receiving module and a reference model; the sending module configured to generate transaction-level data, drive the transaction-level data to a design under test, and send the transaction-level data to the reference model; the receiving module is configured to receive the output data of the design to be tested and send the output data of the design to be tested to the reference model; the reference model is configured to simulate the iSLIP function of the design to be tested, generate simulated output data according to the received transaction-level data, verify the output data of the design to be tested by using the generated simulated output data, and judge the performance of the design to be tested.

In some optional embodiments, the reference model uses system verilog code to realize simulation of iSLIP function of the design to be tested.

In some optional embodiments, the sending module comprises a sequencer and a driver; wherein the sequencer is configured to generate transaction level data by driving a sequence, the transaction level data being sent to the driver; the driver is configured to receive the transaction-level data, convert the transaction-level data into signal-level data, and drive the signal-level data to the design under test.

In some optional embodiments, the receiving module comprises: a monitor configured to monitor an output port of the design under test, convert output data of the design under test from a signal level to a transaction level, and then send to the reference model.

In some optional embodiments, the reference model comprises a scheduler and a checker; the scheduler is configured to simulate the iSLIP function of the design to be tested and generate simulated output data according to the transaction-level data received from the sending module; the checker is configured to verify the output data of the design to be tested received from the receiving module by using the simulation output data generated by the scheduler, and judge the performance of the design to be tested.

In some optional embodiments, the scheduler comprises a multi-level scheduling unit comprising a priority scheduling unit; the priority scheduling unit is configured to select a port with the highest priority for scheduling in the process of scheduling the input ports and the output ports by using the iLISP algorithm.

In a second aspect, the present disclosure provides a UVM-based switch chip verification method, where the switch chip employs an iSLIP algorithm to schedule a plurality of input ports and a plurality of output ports, and the method is applied to the UVM-based switch chip verification platform apparatus according to the first aspect, where the verification platform apparatus includes a sending module, a receiving module, and a reference model; the method comprises the following steps: the sending module generates transaction-level data, drives the transaction-level data to a design to be tested, and sends the transaction-level data to the reference model; the receiving module receives the output data of the design to be tested and sends the output data of the design to be tested to the reference model; the reference model simulates the iSIP function of the design to be tested, generates simulation output data according to the received transaction-level data, verifies the output data of the design to be tested by using the generated simulation output data, and judges the performance of the design to be tested.

In a third aspect, the present disclosure provides a computer device comprising: one or more processors; a storage device having one or more programs stored thereon that, when executed by the one or more processors, cause the one or more processors to implement the UVM-based switch chip authentication method as described above.

In a fourth aspect, the present disclosure provides a computer readable storage medium having stored thereon a computer program which, when executed by one or more processors, implements the UVM-based switch chip authentication method as described above.

In order to verify whether the performance of a Device Under Test (DUT) reaches the standard, the present disclosure provides a switching chip verification platform apparatus and method based on a Universal Verification Methodology (UVM). According to the method, a hardware description language such as system verilog (an upgraded version of the hardware description language verilog) is used for building a reference model, the system verilog can quickly realize the iSIP function, so that the reference model can simulate the function of a DUT easily, and therefore the DUT can be quickly verified, including simulation waveform analysis, so that whether the performance (including indexes such as throughput, transmission rate and the like) of the DUT reaches the standard or not and whether the design meets the expectation or not can be judged efficiently.

Here, the DUT may be a switch chip, for example, a cross bar (cross bar switch matrix) structured switch chip having 64 input ports and 64 output ports. For such a multi-port switching structure, the system verilog code is used for RTL (Register Transfer Level) modeling, the iSIP function is realized, and the system verilog code has the advantages of easiness in realization, high simulation speed and the like.

It is noted that the present disclosure is not limited to using system verilog to implement iSLIP functionality, and other hardware description languages or non-hardware description languages, such as C, may be used to build a reference model to implement iSLIP functionality.

Drawings

Other features, objects and advantages of the disclosure will become more apparent upon reading of the following detailed description of non-limiting embodiments thereof, made with reference to the accompanying drawings in which:

fig. 1 is a schematic diagram of an actual scheduling process of the iSLIP algorithm in one iteration;

fig. 2 is a schematic structural diagram of a UVM-based switch chip verification platform apparatus according to an embodiment of the present disclosure;

fig. 3 is a schematic flow diagram of a reference model implementing the iSLIP algorithm according to an embodiment of the present disclosure;

fig. 4 is a schematic flowchart of a UVM-based switch chip verification method according to an embodiment of the present disclosure;

fig. 5 is a schematic diagram of a hardware component structure of a computer device according to an embodiment of the present disclosure.

Detailed Description

The present disclosure is described in further detail below with reference to the accompanying drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not to be construed as limiting the invention. It should be noted that, for convenience of description, only the portions related to the related invention are shown in the drawings.

In the description of the present disclosure, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", and the like indicate orientations or positional relationships, and are only used for convenience in describing the present disclosure and for simplifying the description, but do not indicate or imply that the device or element referred to must have a particular orientation, be constructed in a particular orientation, and be operated, and thus, should not be construed as limiting the present disclosure. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.

In the description of the present disclosure, it is to be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and the like are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; can be mechanically or electrically connected; may be directly connected or indirectly connected through an intermediate. The specific meaning of the above terms in the present disclosure can be understood by those of ordinary skill in the art as appropriate.

In the description of the present disclosure, it should be noted that the embodiments and features of the embodiments in the present disclosure may be combined with each other without conflict.

To facilitate an understanding of the present disclosure, the iSLIP algorithm is first described below.

iSLIP is an efficient queue scheduling algorithm and is easy to implement in hardware. The present disclosure introduces the principle of scheduling algorithm ISLIP based on crossbar switching fabric, which structurally implements a 64x64 switching arbiter.

Each iteration of the iSLIP algorithm consists of three steps:

1) The first step is as follows: request (Request). The unmatched input queues send requests to each possible output.

2) The second step is that: allowed (Grant). If a non-matching output receives a request (possibly more than one), it selects the input closest to the highest priority on a round robin basis. The output informs each input whether its request is allowed or not. The grant pointer pointing to the highest priority will point to the next of the granted inputs if and only if the grant is accepted in the third step of the first iteration.

3) The third step: (Accetp). If an unmatched input receives an enable (possibly more than one), it selects the output closest to the highest priority on a round robin basis. The accept pointer pointing to the highest priority will point to the next of the accepted outputs if and only if the match is completed in the first iteration.

Note that to avoid starvation, the pointers are updated only after the first iteration, and only once per scheduling period.

Referring to fig. 1, the actual scheduling process of the iSLIP scheduling algorithm in one iteration is described with reference to fig. 1 as a scheduling example. Here, assuming there are 4 input ports and 4 output ports, initially all input ports 1-4 are not establishing a match with output ports 1-4. Wherein each input port has an accept arbiter and each output port has a grant arbiter. The pointers (i.e. enable pointers) of the grant arbiter (i.e. output port arbiter) of the 4 output ports are denoted as g1, g2, g3 and g4, respectively, and at the beginning the 4 enable pointers all point to input port 1. The pointers (i.e. acceptance pointers) of the acceptance arbiter (i.e. input port arbiter) of the 4 input ports are denoted as a1, a2, a3 and a4, respectively, and at the beginning the 4 acceptance pointers all point to output port 1.

In fig. 1, (a) indicates a request, (b) indicates a grant (i.e., permission), and (c) indicates an acceptance.

1) Request (Request). As shown in fig. 1 (a), it is assumed that more than one packet is sent from input port1 and input port 3 to

output ports

1, 2, and 4 having packet queue buffers, respectively, and that input port 4 sends a request signal to output port 4.

2) Allowed (Grant). As shown in fig. 1 (b), the output port1 is requested by the input port1, and issues a Grant signal to the input port 1.

Output ports

2 and 4 are both requested by both input ports and need to be assigned according to priority. Since the pointers g2=1, g4=1 (meaning that the priority is 1234) of the arbiters of the

output ports

2 and 4, the output port 2 issues a Grant signal to the input port1 (closer to the priority than the input port 2) (so that both the

output ports

1 and 2 issue a Grant signal to the input port 1), and the output port 4 issues a Grant signal to the input port 3 (closer to the priority than the input port 4). Note that after the Grant signal is sent, according to the RRM scheduling algorithm, only if the signal is allowed to be accepted by the input port in the third step, the pointers g1, g2, g4 pointing to the highest priority location at the output port can be updated and modulo-incremented to point to the next output port location to accept the Request signal.

3) Accept (Accetp). The input port that is not matched selects one from the Grant signals. As shown in fig. 1 (c), since the input port1 receives the grant signal of the output port1 (closer to the priority than the output port 2) at this time with a1=1, after the matching between the two ports is successful, the pointer a1 points to the output port 2 in modulo increase, and the priority order becomes 2341. Similarly, the input port 3 accepts the grant signal of the output port 4, and after the matching between the two ports is successful, the pointer a3 points to the next accepted output port, that is, the output port1 is still pointed. The output port pointers g1 and g4 that have been matched at this time are updated accordingly, pointing to the next position to issue a grant signal to the input port, i.e. pointer g1 points to input port 2 and pointer g4 points to input port 4. Note that the unsuccessfully matched pointer g2 is not updated.

In one iteration, if there are still unmatched requests, then there will be a match in the next iteration.

Referring to fig. 2, fig. 2 is a schematic structural diagram of an embodiment of a UVM-based switch chip verification platform apparatus 2a according to the present disclosure. The verification platform apparatus 2a of the present disclosure may be used to verify a DUT 24. The verification platform apparatus 2a drives data to the DUT24 and receives output data of the DUT24, thereby achieving verification of the DUT 24.

Here, the DUT24 may be a switch chip applying the iSLIP algorithm, such as a cross bar (cross bar) structured switch chip, which may have a plurality of input ports and a plurality of output ports (e.g., 64 input ports and 64 output ports). In the chip design stage, the design of the switch chip can be realized by using a hardware description language such as verilog, because verilog can easily realize the iSLIP function. For convenience of management, input/output ports (ports) may be managed in groups, for example, 64 source ports (i.e., input ports) are divided into 8 source port groups (gp), each group includes 8 source ports; the 64 destination ports (i.e., output ports) are divided into 8 destination port groups, each group including 8 destination ports.

Here, the DUT24 may include modules such as a shared cache (i.e., rx buffer), a routing module, a core switching module, and a transmit cache (tx buffer). The core exchange module further comprises a queue management module, a distribution arbitration module, a core arbitration module, a data gating module and the like.

The message (i.e. data packet) sent by the verification platform device 2a is forwarded to the corresponding port of the DUT24 through the routing information carried in the packet, and the data first goes through rx buffer, and then goes through the routing module to look up the routing table to obtain the routing information, and then goes into the queue management module of the core switching module. In the core switching module, a distribution arbitration module generates a scheduling request, the core arbitration module decides which source port and which destination port correspond to which destination port, the distribution arbitration module decides which source port is selected, and a data gating module selects tx buffer output or other outputs, so that the functions of mutually sending and receiving data are realized.

The verification platform device 2a of the present disclosure may be used to verify basic logic functions in the DUT24, including shared cache, routing module, core switching module, tx buffer, etc., to ensure normal communication and forwarding of data packets, and to determine whether the performance of the DUT24 meets the standard.

As shown in fig. 2, the verification platform apparatus 2a of the present disclosure includes: a Reference Model (RM) 21, a transmitting module 22 and a receiving module 23.

The sending module (tx Agent) 22 is configured to generate transaction-level data, such as FC (Fibre Channel, or mesh Channel) protocol packets (i.e., data packets), to be sent to the DUT24 for reception by its shared buffer, and the generated transaction-level data is also sent to the RM module 21. In some optional embodiments, the sending module 22 includes a sequencer (sqr) and a driver (driver), the sequencer is configured to generate transaction-level data through a driving sequence and send the transaction-level data to the driver, and the driver is configured to receive the transaction-level data and convert the transaction-level data into signal-level data to drive to the DUT24, so as to authenticate the DUT 24. Alternatively, transaction-level data driven in the drive may be sent out through a first-in-first-out (fifo) interface. Alternatively, 64 drivers may be configured for a DUT24 having 64 input ports.

And a reception module (tx Agent) 23 configured to receive output data (data at a signal level) of the DUT24, convert the received output data (convert the data into a data packet at a transaction level), and transmit the converted data to the RM module 21. The DUT24 outputs data in response to receiving transaction-level data from the driver. In some alternative embodiments, the receive module 23 includes a monitor (monitor) that monitors an output port of the DUT24 (or a receive port of the receive module 23), obtains output data of the DUT24, and converts the received output data from a signal level to a transaction level for transmission to the RM module 21. Alternatively, 64 monitors may be configured for a DUT24 having 64 output ports.

An RM module 21 configured to receive the transaction-level data transmitted by the transmission module 22; simulating an iSIP function of the DUT24, and generating simulated output data according to the received transaction-level data; and verifying the output data of the DUT24 by using the generated analog output data so as to finish the verification of the DUT24 and judge whether the performance of the DUT24 reaches the standard.

In some optional embodiments, the RM module 21 comprises a scheduler and a checker (Scoreboard), the scheduler. Wherein the scheduler is configured to simulate the functions of the DUT24, including iSLIP functions, i.e., functions for implementing the DUT24, generate simulated output data from the transaction-level data received from the transmitting module 22, and deliver the simulated output data to the checker; the checker is used for realizing a checking function, and is configured to verify the output data of the DUT24 received from the receiving module 23 by using the analog output data generated by the scheduler, and judge the performance of the DUT 24.

In some optional embodiments, the scheduler may include multiple stages of scheduling units that together implement the function of the iSLIP algorithm of the DUT24, where the first stage of scheduling unit is configured to obtain, in each iteration of the iSLIP algorithm, a corresponding source port group (port, pg) number and destination port group (port, pg) number; the second-stage scheduling unit is used for obtaining a corresponding source port number; the first-level scheduling unit is a priority scheduling unit and is used for selecting a port with the highest priority for scheduling in the process of scheduling the input ports and the output ports by using the iLISP algorithm.

Referring to the flow shown in fig. 3, the detailed implementation procedure of the iSILP algorithm in the scheduler includes:

firstly, according to a source port group (src _ pg) number, a source port (src _ port) number, a destination port group (dst _ pg) number and a destination port (dst _ port) number, a source port group and destination port group to port0 scheduling request (Req) and a source port group and destination port group to port1 scheduling request are obtained; up to the source port group and destination port group to port7 dispatch requests. Here, port0 to port7 refer to 8 destination ports in the destination port group, and are numbered from 0 to 7. Here, it is assumed that there are 64 source ports, which are divided into 8 source port groups, numbered from 0 to 7, each source port group comprising 8 source ports, numbered from 0 to 7;64 destination ports, divided into 8 destination port groups numbered from 0 to 7, each destination port group comprising 8 destination ports numbered from 0 to 7.

And in the first clock cycle, only the scheduling request source and the destination port num obtained in the previous steps are processed to the destination ports from port0 to port7, and the accept pointer and the grant pointer are updated according to the islip algorithm to obtain the hit source port num and the hit destination port num for the next clock cycle to use.

And in the second clock cycle, updating the accept pointer and the grant pointer in the cycle according to the obtained pointer of the previous cycle and the src _ pg (source port group) and dst _ pg (destination port group) hit in the previous cycle, so as to obtain the hit src _ pg and dst _ pg for the next cycle.

The same is true for the third clock cycle.

And performing 8 clock cycles in this way, realizing fair scheduling of the source port and the destination port and preventing starvation.

Wherein, each clock cycle is sealed into a task (task) to generate the result of the islip algorithm scheduling (grant), and the inputs of the task are the last hit source port group number and destination port group number, the updated scheduling request, and the updated source port accept pointer and destination port grant pointer.

In order to solve the technical problem that whether the performance (such as throughput and transmission rate) of the iSLIP function is up to the standard is not considered only by considering verilog codes, the disclosure provides a switching chip verification platform device and a switching chip verification method based on UVM. According to the method, a hardware description language such as system verilog (an upgraded version of the hardware description language verilog) is used for building a reference model, the system verilog can quickly realize the iSIP function, so that the reference model can simulate the function of a DUT easily, and therefore the DUT can be quickly verified, including simulation waveform analysis, so that whether the performance (including indexes such as throughput, transmission rate and the like) of the DUT reaches the standard or not and whether the design meets the expectation or not can be judged efficiently.

The DUT is verified by building a reference model (modeling) by using system verilog, because the hardware description language is closer to the hardware realization and has a periodic concept, the transaction-level modeling can be abstracted, various delay parameters can be added easily, and the hardware description language can be expanded into a functional model with accurate registers or a performance model with accurate time sequence. The reference model built by the system verilog can simulate concurrent behaviors among all modules by utilizing a process, and various complex model algorithms can be realized by utilizing the system verilog.

It should be understood, however, that the present disclosure is not limited to using system verilog to implement iSLIP functionality, and that other hardware description languages or non-hardware description languages, such as C, may be used to build a reference model to implement iSLIP functionality.

Referring to fig. 4, fig. 4 is a schematic flow chart diagram of an embodiment of a UVM-based switch chip verification method according to the present disclosure. The method of the present disclosure is applied to the UVM-based switch chip verification platform apparatus as described above, which includes a transmitting module, a receiving module and a reference model. The switching chip adopts an iSIP algorithm to schedule a plurality of input ports and a plurality of output ports.

As shown in fig. 4, the method of the present disclosure includes the steps of:

step 401, a sending module generates transaction-level data, drives the transaction-level data to a design to be tested, and sends the transaction-level data to a reference model;

step 402, a receiving module receives output data of a design to be tested and sends the output data of the design to be tested to a reference model;

step 403, simulating an iSLIP function of the design to be tested by the reference model, generating simulated output data according to the received transaction-level data, verifying the output data of the design to be tested by using the generated simulated output data, and judging the performance of the design to be tested.

Optionally, the reference model adopts system verilog code to simulate iSLIP function of the design to be tested.

Referring to fig. 5, fig. 5 is a schematic block diagram of one embodiment of a computer device according to the present disclosure. As shown in fig. 5, a computer device 500 of the present disclosure may include:

one or more processors 501;

a memory 502 having one or more programs 503 stored thereon;

components such as processor 501 and memory 502 may be coupled together by a bus system 504; the bus system 504 is used to enable connection communications between these components;

the one or more programs 503, when executed by the one or more processors 501, cause the one or more processors 501 to implement the UVM-based switch chip verification method as disclosed in the above method embodiments.

The bus system 504 may include a power bus, a control bus, and a status signal bus, in addition to a data bus. The memory 502 may be either volatile memory or nonvolatile memory, and may include both volatile and nonvolatile memory. The Processor 501 may be an integrated circuit chip with Signal processing capabilities, and may be a general purpose Processor, a Digital Signal Processor (DSP), or other programmable logic device, discrete gate or transistor logic device, discrete hardware components, or the like.

The disclosed embodiments also provide a computer-readable storage medium having stored thereon a computer program that, when executed by one or more processors, implements the UVM-based switch chip verification method as disclosed in the above method embodiments.

The present disclosure is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems) and computer program products according to embodiments of the disclosure. It will be understood that each flow and/or block of the flowchart illustrations and/or block diagrams, and combinations of flows and/or blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

It should be understood that the terms "system" and "network" are often used interchangeably herein in this disclosure. The term "and/or" in the present disclosure is only one kind of association relationship describing the association object, and means that there may be three kinds of relationships, for example, a and/or B, and may mean: a exists alone, A and B exist simultaneously, and B exists alone. In addition, the character "/" in the present disclosure generally indicates that the former and latter associated objects are in an "or" relationship.

The technical solutions of the present disclosure have been described in detail through specific embodiments. In the foregoing embodiments, the descriptions of the respective embodiments have respective emphasis, and for parts that are not described in detail in a certain embodiment, reference may be made to the related descriptions of other embodiments.

The foregoing description is only exemplary of the preferred embodiments of the disclosure and is illustrative of the principles of the technology employed. It will be appreciated by those skilled in the art that the scope of the invention in the present disclosure is not limited to the specific combination of the above-mentioned features, but also encompasses other embodiments in which any combination of the above-mentioned features or their equivalents is made without departing from the spirit of the invention. For example, the above features and the technical features disclosed in the present disclosure (but not limited to) having similar functions are replaced with each other to form the technical solution.

Claims

1. A UVM-based switching chip verification platform apparatus, wherein the switching chip employs an iSLIP algorithm to schedule a plurality of input ports and a plurality of output ports, the UVM-based switching chip verification platform apparatus comprising: the device comprises a sending module, a receiving module and a reference model;

the sending module configured to generate transaction-level data, drive the transaction-level data to a design under test, and send the transaction-level data to the reference model;

the receiving module is configured to receive the output data of the design to be tested and send the output data of the design to be tested to the reference model;

the reference model is configured to simulate the iSLIP function of the design to be tested, generate simulation output data according to the received transaction-level data, verify the output data of the design to be tested by using the generated simulation output data, and judge the performance of the design to be tested; the reference model adopts system verilog codes to realize the simulation of the iSIP function of the design to be tested;

the reference model comprises a scheduler and a checker;

the scheduler is configured to simulate the iSLIP function of the design to be tested and generate simulated output data according to the transaction-level data received from the sending module;

the checker is configured to verify the output data of the design to be tested received from the receiving module by using the analog output data generated by the scheduler, and judge the performance of the design to be tested;

the design to be tested is a switching chip applying an iSIP algorithm and is provided with a plurality of source ports and a plurality of destination ports; the source ports are grouped and managed and are divided into a plurality of source port groups; the plurality of destination ports are managed in groups and divided into a plurality of destination port groups;

the implementation process of the iSILP algorithm in the scheduler includes: firstly, obtaining a scheduling request, processing the scheduling request in a first clock cycle, and updating a pointer to obtain a hit source port group number and a hit destination port group number; updating the pointer of the period in each subsequent clock period according to the obtained pointer of the previous period and the source port group number and the destination port group number hit in the previous period to obtain a hit source port group number and a hit destination port group number; until all clock cycles are completed; each clock cycle is sealed into a task, a result of the iSILP algorithm scheduling is generated, and the input of the task is a source port group number and a destination port group number hit in the last cycle, an updated scheduling request and an updated pointer;

the scheduler comprises a multi-level scheduling unit, wherein the multi-level scheduling unit comprises a first-level scheduling unit, a second-level scheduling unit and a priority scheduling unit;

the first-stage scheduling unit is configured to obtain a corresponding source port group number and a corresponding destination port group number in each iteration of the iSLIP algorithm;

the second-level scheduling unit configured to obtain a corresponding source port number;

the priority scheduling unit is configured to select a port with the highest priority for scheduling in the process of scheduling the input ports and the output ports by using the iLISP algorithm.

2. The UVM-based switch chip verification platform apparatus of claim 1, wherein the transmitting module includes a sequencer and a driver; wherein, the first and the second end of the pipe are connected with each other,

the sequencer configured to generate transaction level data by driving a sequence, the transaction level data being sent to the driver;

the driver is configured to receive the transaction-level data, convert the transaction-level data into signal-level data, and drive the signal-level data to the design under test.

3. The UVM-based switch chip authentication platform assembly of claim 1, wherein the receiving module comprises:

a monitor configured to monitor an output port of the design under test, convert output data of the design under test from a signal level to a transaction level, and then send to the reference model.

4. A UVM-based switch chip verification method, the switch chip employing an iSLIP algorithm to schedule a plurality of input ports and a plurality of output ports, the method being applied to the UVM-based switch chip verification platform apparatus according to claim 1, the verification platform apparatus comprising a transmitting module, a receiving module and a reference model; the method comprises the following steps:

the sending module generates transaction-level data, drives the transaction-level data to a design to be tested, and sends the transaction-level data to the reference model;

the receiving module receives the output data of the design to be tested and sends the output data of the design to be tested to the reference model;

the reference model simulates the iSIP function of the design to be tested, generates simulation output data according to the received transaction-level data, verifies the output data of the design to be tested by using the generated simulation output data, and judges the performance of the design to be tested; the reference model adopts system verilog codes to realize the simulation of the iSIP function of the design to be tested;

the reference model comprises a scheduler and a checker;

the checker is configured to verify the output data of the design to be tested received from the receiving module by using the simulation output data generated by the scheduler, and judge the performance of the design to be tested;

the design to be tested is a switching chip applying an iSIP algorithm and provided with a plurality of source ports and a plurality of destination ports; the source ports are grouped and managed and are divided into a plurality of source port groups; the plurality of destination ports are managed in groups and divided into a plurality of destination port groups;

the implementation process of the iSILP algorithm in the scheduler includes: firstly, obtaining a scheduling request, processing the scheduling request in a first clock cycle, and updating a pointer to obtain a hit source port group number and a hit destination port group number; updating the pointer of the period according to the obtained pointer of the previous period and the source port group number and the destination port group number which are hit in the previous period in each subsequent clock period to obtain a hit source port group number and a hit destination port group number; until all clock cycles are completed; each clock cycle is sealed into a task, a result of the iSIP algorithm scheduling is generated, and the input of the task is a source port group number and a destination port group number which are hit in the last cycle, an updated scheduling request and an updated pointer;

the scheduler comprises a multi-level scheduling unit, and the multi-level scheduling unit comprises a first-level scheduling unit, a second-level scheduling unit and a priority scheduling unit;

5. A computer device, comprising:

one or more processors;

a storage device having one or more programs stored thereon,

the one or more programs, when executed by the one or more processors, cause the one or more processors to implement the UVM-based switch chip verification method of claim 4.

6. A computer-readable storage medium, having stored thereon a computer program which, when executed by one or more processors, implements the UVM-based switch chip authentication method of claim 4.