CN115149787A

CN115149787A - Voltage regulating circuit and electronic device

Info

Publication number: CN115149787A
Application number: CN202210874187.2A
Authority: CN
Inventors: 陈志刚; 童庆
Original assignee: Vivo Mobile Communication Co Ltd
Current assignee: Vivo Mobile Communication Co Ltd
Priority date: 2022-07-20
Filing date: 2022-07-20
Publication date: 2022-10-04

Abstract

The application discloses voltage regulation circuit and electronic equipment, voltage regulation circuit includes: a first power supply; the input end of the boosting module is connected with the first power supply; the input end of the voltage reduction module is connected with the output end of the voltage boosting module, and the output end of the voltage reduction module is used for outputting voltage to the power load; the output end of the time sequence control module is respectively connected with the voltage boosting module and the voltage reducing module; and the protection circuit is connected with the first power supply and is used for protecting the boosting module when the time sequence control module is powered off. This application is through setting up protection circuit when the chronogenesis control module is electrified, protects the module that steps up, avoids leading to the partial switch device damage of the module that steps up because of the conductance under the chronogenesis control module, guarantees this voltage regulation circuit's normal work, improves this voltage regulation circuit's use reliability.

Description

Voltage regulating circuit and electronic device

Technical Field

The application belongs to the technical field of electronics, concretely relates to voltage regulating circuit and electronic equipment.

Background

With the development of technologies, the power consumption problem of electronic devices such as mobile terminals is more and more prominent due to higher functions and integration, and the power amplifier is a main consumer in the mobile terminal, so that reducing the power consumption of the power amplifier has become a key technology for prolonging the life of the mobile device.

In the related art, in order to reduce the Power consumption of the Power amplifier, the mobile terminal generally employs an Average Power Tracking (APT) technique, where the APT technique automatically adjusts the operating voltage of the Power amplifier according to the pre-output Power of the Power amplifier and by combining with the parameters of the Power amplifier, so as to improve the efficiency of the Power amplifier and save energy. A voltage regulating circuit exists in a realization circuit framework of the APT technology, the voltage output by a system power supply of the electronic equipment is regulated by the voltage regulating circuit, and the regulated voltage supplies power to an electric load. However, when the mobile terminal is turned off or restarted, a part of switching devices of the conventional voltage regulating circuit may be directly turned on due to disorder of the control logic, and further, a system power supply of the mobile terminal may be directly shorted to the ground, which may generate a large current to cause a short circuit between the system power supply and the ground, and burn out a part of the switching devices of the voltage regulating circuit, thereby causing the voltage regulating circuit to fail.

Disclosure of Invention

The application aims at providing a voltage regulation circuit and electronic equipment, solves the problem that when the mobile terminal is shut down or restarted, partial switch devices of the voltage regulation circuit can be directly conducted due to control logic disorder, realizes protection of the switch devices of the voltage regulation circuit, and improves the use reliability of the voltage regulation circuit.

In order to solve the technical problem, the present application is implemented as follows:

in a first aspect, an embodiment of the present application provides a voltage regulation circuit, which includes:

a first power supply;

the input end of the boosting module is connected with the first power supply;

the input end of the voltage reduction module is connected with the output end of the voltage boost module, and the output end of the voltage reduction module is used for outputting voltage to an electric load;

the output end of the time sequence control module is respectively connected with the voltage boosting module and the voltage reducing module;

and the protection circuit is connected with the first power supply and used for protecting the boosting module when the time sequence control module is powered off.

In a second aspect, an embodiment of the present application provides an electronic device, which includes:

the voltage regulation circuit of the first aspect.

In an embodiment of the present invention, the voltage regulating circuit includes a first power supply, a voltage boosting module, a voltage dropping module, a timing control module, and a protection circuit, and specifically, the protection circuit is configured to protect the voltage boosting module when the timing control module is powered off, so as to prevent a part of switching devices of the voltage boosting module from being damaged due to logic disorder caused by the power off of the timing control module, ensure normal operation of the voltage regulating circuit, and improve reliability of the voltage regulating circuit.

Additional aspects and advantages of the invention will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the invention.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description, serve to explain the principles of the invention.

Fig. 1 is a circuit block diagram of a voltage regulating circuit according to an embodiment of the present invention.

Fig. 2 is a schematic structural diagram of a first voltage regulating circuit according to an embodiment of the present invention.

Fig. 3 is a schematic structural diagram of a second voltage regulating circuit according to an embodiment of the present invention.

Fig. 4 is a schematic structural diagram of a third voltage regulating circuit according to an embodiment of the present invention.

Detailed Description

Reference will now be made in detail to embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are illustrative only for the purpose of explaining the present invention and are not to be construed as limiting the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

The terms first, second and the like in the description and in the claims of the present application are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It will be appreciated that the data so used may be interchanged under appropriate circumstances such that embodiments of the application may be practiced in sequences other than those illustrated or described herein, and that the terms "first," "second," and the like are generally used herein in a generic sense and do not limit the number of terms, e.g., the first term can be one or more than one.

In the description of the present invention, it is to be noted that, unless otherwise explicitly specified or limited, the term "connected" is to be interpreted broadly, e.g. as a fixed connection, a detachable connection, or an integral connection; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meanings of the above terms in the present invention can be understood in specific cases to those skilled in the art.

The following describes the control circuit provided in the embodiments of the present application in detail through specific embodiments and application scenarios thereof with reference to the accompanying drawings.

The embodiment of the invention provides a voltage regulating circuit which is applied to an electronic equipment product, wherein the electronic equipment can be mobile phones, tablet computers, notebook computers, palm computers and other electronic equipment.

Referring to fig. 1, an embodiment of the invention discloses a circuit block diagram of a voltage regulating circuit, where the voltage regulating circuit includes a first power supply B1, a voltage boosting module U1, a voltage reducing module U2, a timing control module U3, and a protection circuit U4; the input end of the boosting module U1 is connected with a first power supply B1; the input end of the voltage reduction module U2 is connected with the output end of the voltage boosting module U1, and the output end of the voltage reduction module U2 is used for outputting voltage to the electric load EL; the output end of the time sequence control module U3 is respectively connected with the boosting module U1 and the voltage reducing module U2; the protection circuit is connected with the first power supply, and the protection circuit U4 is used for protecting the boosting module U1 when the time sequence control module U3 is powered off.

In this embodiment, after the battery of the electronic device is installed, the first power supply B1 is in a power-on state, and no matter the electronic device is in a power-on state or a power-off state, as long as the first power supply is not damaged, the first power supply B1 can output a voltage, the output voltage of the first power supply B1 is VCC, and the output voltage VCC of the first power supply B1 can supply power to the electrical load EL through the voltage boosting module U1 and the voltage reducing module U2; the output voltage VCC of the first power supply B1 may also supply the protection circuit U4.

In this embodiment, as shown in fig. 2, 3 and 4, the boost module U1 includes a switch group and a boost capacitor C1, the switch group is respectively connected to the first power supply B1, the buck module U2 and the timing control module U3, and the boost capacitor C1 is connected to the switch group.

In this embodiment, the switch group includes a first NMOS transistor Q1, a second NMOS transistor Q2, a third NMOS transistor Q3, and a fourth NMOS transistor Q4; the grid electrode of the first NMOS tube Q1, the grid electrode of the second NMOS tube Q2, the grid electrode of the third NMOS tube Q3 and the grid electrode of the fourth NMOS tube Q4 are respectively connected with the output end of the time sequence control module U3; the drain electrode of the first NMOS tube Q1 is connected with a first power supply B1, and the source electrode of the first NMOS tube Q1 is connected with the drain electrode of the second NMOS tube Q2; the source electrode of the second NMOS tube Q2 is connected with the voltage reduction module U2; the drain electrode of the third NMOS tube Q3 is connected with the drain electrode of the first NMOS tube Q1, and the source electrode of the third NMOS tube Q3 is connected with the drain electrode of the fourth NMOS tube Q4; the source electrode of the fourth NMOS tube Q4 is connected with a ground end GND; the first end of the boosting capacitor C1 is connected with the source electrode of the first NMOS tube Q1; the second end of the boost capacitor C1 is connected to the source of the third NMOS transistor Q3.

In this embodiment, the voltage boost module U1 is configured to boost the output voltage VCC of the first power supply B1, and the voltage output by the voltage boost module U1 supplies power to the voltage step-down module U2.

In this embodiment, the first NMOS transistor Q1, the second NMOS transistor Q2, the third NMOS transistor Q3, and the fourth NMOS transistor Q4 are field effect transistor switches, respectively, and the first NMOS transistor Q1, the second NMOS transistor Q2, the third NMOS transistor Q3, and the fourth NMOS transistor Q4 can be selected as enhancement-mode N-channel MOS transistors, respectively. By utilizing the working principle of the field effect transistor, the first NMOS transistor Q1, the second NMOS transistor Q2, the third NMOS transistor Q3 and the fourth NMOS transistor Q4 can be controlled to be switched on and off through the time sequence control module U3, so that the output voltage of the boosting module U1 is controlled, and the circuit structure is simple.

In this embodiment, the operating principle of the boost module U1 is: firstly, a first NMOS tube Q1 and a fourth NMOS tube Q4 are controlled to be respectively conducted through a time sequence control module U3, and a second NMOS tube Q2 and a third NMOS tube Q3 are controlled to be respectively turned off through the time sequence control module U3, when the first NMOS tube Q1 and the fourth NMOS tube Q4 are respectively conducted, and the second NMOS tube Q2 and the third NMOS tube Q3 are respectively turned off, a first power supply B1 charges a boost capacitor C1 through the first NMOS tube Q1, at the moment, the potential of a first end of the boost capacitor C1 is equal to the output voltage VCC of the first power supply B1, the potential of a second end of the boost capacitor C1 is zero, and the voltages at two ends of the boost capacitor C1 are equal to the output voltage VCC of the first power supply B1;

then, the timing control module U3 controls the first NMOS tube Q1 and the fourth NMOS tube Q4 to be turned off respectively, and controls the second NMOS tube Q2 and the third NMOS tube Q3 to be turned on respectively, when the second NMOS tube Q2 and the third NMOS tube Q3 are turned on respectively, and the first NMOS tube Q1 and the fourth NMOS tube Q4 are turned off respectively, the first power supply B1 charges the boost capacitor C1 through the third NMOS tube Q3, at this time, the potential of the second end of the boost capacitor C1 is equal to the output voltage VCC of the first power supply B1, and since the voltages at the two ends of the boost capacitor C1 cannot be suddenly changed, the potential of the first end of the boost capacitor C1 rises to 2VCC, so that the output voltage of the boost module U1 is 2VCC, and boosting of the boost module U1 is realized.

In this embodiment, the output voltage of the boost module U1 is VCC to 2VCC.

For example, when the output voltage VCC =48V of the first power supply B1, the input voltage of the boost block U1 is 48V, and the output voltage of the boost block U1 is 48V to 96V.

In this embodiment, as shown in fig. 2, 3 and 4, the voltage dropping module U2 includes a fifth NMOS transistor Q5, an inductor L and a voltage dropping capacitor C2.

In this embodiment, the gate of the fifth NMOS transistor Q5 is connected to the output terminal of the timing control module U3, the drain of the first NMOS transistor Q1 is connected to the source of the second NMOS transistor Q2, and the source of the fifth NMOS transistor Q5 is connected to the ground GND; the first end of the inductor L is connected with the source electrode of the second NMOS tube Q2, and the second end of the inductor L is connected with one end of the voltage reduction capacitor C2; the other end of the voltage reduction capacitor C2 is connected with a ground end GND; and the two ends of the voltage reduction capacitor C2 are output ends of the voltage reduction module U2.

In this embodiment, the voltage-reducing module U2 is configured to reduce the voltage output by the voltage-increasing module U1, and the voltage output by the voltage-reducing module U2 supplies power to the electrical load EL.

In this embodiment, the fifth NMOS transistor Q5 is a fet switch, and the fifth NMOS transistor Q5 can be selected as an enhancement-mode N-channel MOS transistor. By utilizing the working principle of the field effect transistor, the switching frequency or duty ratio of the second NMOS transistor Q2 and the fifth NMOS transistor Q5 can be controlled through the time sequence control module U3, the output voltage of the voltage reduction module U2 is controlled, and the circuit structure is simple.

In this embodiment, the operation principle of the voltage reduction module U2 is as follows: the second NMOS tube Q2 is controlled to be conducted through the time sequence control module U3, the fifth NMOS tube Q5 is controlled to be turned off through the time sequence control module U3, the fifth NMOS tube Q5 is turned off, the voltage output by the boosting module U1 cannot be transmitted to the fifth NMOS tube Q5, therefore, the voltage output by the boosting module U1 is transmitted to the inductor L, the inductor L converts electric energy into magnetic energy and stores the magnetic energy, the voltage stored by the inductor L charges the voltage reduction capacitor C2, meanwhile, the voltage stored by the inductor L supplies power to the electric load EL, and the current of the inductor L cannot change suddenly, so that the load voltage at two ends of the electric load EL is increased gradually;

when the load voltage reaches the preset load voltage, the time sequence control module U3 controls the second NMOS tube Q2 to be turned off, the time sequence control module U3 controls the fifth NMOS tube Q5 to be turned on, the boosting module U1 does not supply power to the electric load EL any more, the magnetic energy stored in the inductor L is converted into electric energy to be released, the inductor L serves as a power supply in the voltage reduction module U2 to supply power to the electric load EL, and the voltage output by the inductor L is gradually reduced;

when the output voltage of the inductor L is smaller than the preset load voltage, the second NMOS tube Q2 is controlled to be switched on again through the time sequence control module U3, the fifth NMOS tube Q5 is controlled to be switched off through the time sequence control module U3, the boosting module U1 supplies power to the electric load EL again, the inductor L is charged simultaneously, the process is circulated and reciprocated, the second NMOS tube Q2 is controlled, the fifth NMOS tube Q5 is switched on and switched off, the energy storage and release of the inductor L are controlled, and the voltage reduction of the voltage reduction module U2 is achieved.

In the present embodiment, the preset load voltage is a voltage required for operating the electrical load EL.

In this embodiment, when the inductor L performs energy conversion between storage and release, the positive and negative poles of the inductor L change; when the inductor L stores energy, the first end of the inductor L is a positive electrode, and the second end of the inductor L is a negative electrode; when the inductor L releases energy, the first end of the inductor L is a negative electrode, and the second end of the inductor L is a positive electrode.

In this embodiment, when the second NMOS transistor Q2 is turned off, the inductor L cannot supply power to the electrical load EL at this moment due to the polarity inversion of the inductor L, and the electrical load EL is supplied power by the voltage-reducing capacitor C2.

In the present embodiment, one end of the electrical load EL is connected to one end of the voltage-reducing capacitor C2, and the other end of the electrical load EL is connected to the ground GND.

In this embodiment, the electrical load EL may be each electrical module in the electronic device, and different electrical modules have different operating frequency bands and require different input voltages and input currents.

In this embodiment, the timing control module U3 is configured to control turn-on and turn-off of the first NMOS transistor Q1, the second NMOS transistor Q2, the third NMOS transistor Q3, the fourth NMOS transistor Q4, and the fifth NMOS transistor Q5, and simultaneously, the timing control module U3 is further configured to control turn-on and turn-off sequence of the first NMOS transistor Q1, the second NMOS transistor Q2, the third NMOS transistor Q3, the fourth NMOS transistor Q4, and the fifth NMOS transistor Q5, respectively.

In this embodiment, if the protection circuit U4 is not provided, the power supply voltage required by the timing control module U3 is much smaller than the first power supply B1, the first power supply B1 cannot be directly used to supply power to the timing control module U3, an additional power supply needs to be provided to supply power to the timing control module U3, when the electronic device is turned off or restarted, the additional power supply may be powered down, the first power supply B1 is not powered down, the first power supply B1 continues to supply power to the voltage boosting module U1, the additional power supply is powered down to power down the timing control module U3, when the timing control module U3 is powered down, the first NMOS tube Q1, the second NMOS tube Q2, the third NMOS tube Q3, and the fourth NMOS tube Q4 of the timing control module U3 may be controlled by a disordered logic, the third NMOS tube Q3 and the fourth NMOS tube Q4 are turned on at the same time, so that the first power supply B1 is directly short-circuited to the ground to generate a large current, and the large current may burn the third NMOS tube Q3 and the fourth NMOS tube Q4, resulting in failure of the voltage regulation circuit; when the time sequence control module U3 is powered off, the protection circuit U4 is arranged to protect the third NMOS tube Q3 of the boosting module U1 and the fourth NMOS tube Q4 of the boosting module U1, the situation that the third NMOS tube Q3 and the fourth NMOS tube Q4 are controlled to be disordered and are all conducted due to the fact that the power is supplied to the time sequence control module U3 is avoided, and the use reliability of the voltage regulating circuit is guaranteed.

In this embodiment, the voltage regulating circuit is configured to perform a boosting process on the output voltage VCC of the first power supply B1 by providing the boosting module U1, perform a voltage reduction process on the voltage output by the boosting module U1 by providing the voltage reduction module U2, and is substantially a boosting circuit when the boosting amount of the boosting module U1 is greater than the voltage reduction amount of the voltage reduction module U2; when the boost quantity of the boost module U1 is smaller than the buck quantity of the buck module U2, the voltage regulating circuit is a buck circuit in essence, so that the output voltage of the buck module U2 is dynamically regulated according to the power demand of the power load EL, the power supply of the power load EL is provided, and the energy consumption is saved.

For example, when the output voltage VCC of the first power supply B1 =48V, 48V of the voltage output by the first power supply B1 is boosted by the voltage boosting module U1, the output voltage of the voltage boosting module U1 is 60V, and the voltage of 60V is then stepped down by the voltage lowering module U2, the output voltage of the voltage lowering module U2 is 50V, the voltage boosting amount of the voltage boosting module U1 is 12V, the voltage lowering amount of the voltage lowering module U2 is 10V, the voltage boosting amount of the voltage boosting module U1 is larger than the voltage lowering amount of the voltage lowering module U2, the output voltage of the voltage lowering module U2 is larger than the output voltage VCC of the first power supply B1, and the voltage regulating circuit is substantially a voltage boosting circuit.

For example, when the output voltage VCC =48V of the first power supply B1 is set, the voltage of 48V is boosted by the boosting module U1, the output voltage of the boosting module U1 is set to 60V, and the voltage of 60V is further reduced by the reducing module U2, the output voltage of the reducing module U2 is set to 24V, the boosting amount of the boosting module U1 is set to 12V, the reducing amount of the reducing module U2 is set to 36V, the boosting amount of the boosting module U1 is smaller than the reducing amount of the reducing module U2, the output voltage of the reducing module U2 is smaller than the output voltage VCC of the first power supply B1, and the voltage regulator circuit is substantially a reducing circuit.

In one embodiment, as shown in fig. 2 and 3, the protection circuit U4 includes a voltage conversion circuit, an input terminal of the voltage conversion circuit is connected to the first power supply B1, and an output terminal of the voltage conversion circuit is connected to a power supply terminal of the timing control module U3.

In this embodiment, the voltage conversion circuit can step down the output voltage VCC of the first power supply B1, and supply power to the timing control module U3 by using the output voltage of the voltage conversion circuit.

In this embodiment, the voltage conversion circuit may be various voltage reduction circuits with voltage reduction functions, such as an LDO module and a DC-DC conversion module.

In this embodiment, the output voltage of the voltage conversion circuit is much smaller than the output voltage VCC of the first power supply B1.

For example, the output voltage VCC =48V of the first power supply B1, the voltage conversion circuit steps down the output voltage of the first power supply B1, and the output voltage of the voltage conversion circuit is 3.3V.

In one embodiment, as shown in FIG. 2, the voltage conversion circuit includes an LDO module.

The input end of LDO module and the enable end of LDO module are connected with first power B1 respectively, and the output of LDO module is connected with sequential control module U3's power end.

In this embodiment, the LDO module is a low dropout linear regulator module, an input end of the LDO module and an enable end of the LDO module are respectively connected with the first power supply B1, an output end of the LDO module is connected with a power supply end of the timing control module U3, the first power supply B1 supplies power to the timing control module U3 through the LDO module, because the first power supply B1 is always in a power-on state, no matter the electronic device is in a power-on state or a power-off state, the timing control module U3 is in the power-on state, power-off of the timing control module U3 due to power-off or restart of the electronic device is effectively avoided, and further, the third NMOS tube Q3 and the fourth NMOS tube Q4 are prevented from being turned on simultaneously, and the use reliability of the voltage regulating circuit is improved.

In one embodiment, as shown in FIG. 3, the voltage conversion circuit includes a DC-DC conversion module.

The input end of the DC-DC conversion module is connected with the first power supply B1, and the output end of the DC-DC conversion module is connected with the power supply end of the time sequence control module U3.

In this embodiment, the DC-DC conversion module is a DC-DC voltage reduction module, an input end of the DC-DC conversion module is connected to the first power supply B1, an output end of the DC-DC conversion module is connected to a power supply end of the timing control module U3, the first power supply B1 supplies power to the timing control module U3 through the DC-DC conversion module, and since the first power supply B1 is always in a power-on state, the timing control module U3 is in a power-on state regardless of whether the electronic device is in a power-on state or a power-off state, thereby effectively avoiding the power-off of the timing control module U3 caused by the power-off or the restart of the electronic device, further avoiding the simultaneous conduction of the third NMOS transistor Q3 and the fourth NMOS transistor Q4, and improving the use reliability of the voltage regulation circuit.

In one embodiment, as shown in fig. 4, a second power supply B2 is also included.

The second power supply B2 is connected with a power supply end of the time sequence control module U3.

The protection circuit U4 is connected between the first power supply B1 and the input end of the boosting module U1, and the control end of the protection circuit U4 is connected with the second power supply B2.

The protection circuit U4 is configured to disconnect the connection relationship between the first power supply B1 and the input of the boost module U1 when the second power supply B2 is powered down.

In this embodiment, the timing control module U3 is supplied with power by the second power supply B2, the output voltage of the second power supply B2 is much smaller than the output voltage of the first power supply B1, and when the electronic device is in a power-on state, the second power supply B2 is in a power-on state; when the electronic device is in the power-off state, the second power supply B2 is in the power-off state.

In this embodiment, when the second power supply B2 is powered down, the protection circuit U4 is arranged, the connection between the first power supply B1 and the input end of the boost module U1 is disconnected, so that the first power supply B1 stops supplying power to the boost module U1, in the power down process of the second power supply B2, if the third NMOS transistor Q3 and the fourth NMOS transistor Q4 are simultaneously turned on due to the disorder of the control time sequence of the time sequence control module U3, because the boost module U1 has no input voltage, the third NMOS transistor Q3 and the fourth NMOS transistor Q4 cannot be damaged, and the use reliability of the voltage regulation circuit is improved.

In one embodiment, as shown in fig. 4, the protection circuit U4 includes a voltage comparison circuit;

the voltage comparison circuit is connected between the first power supply B1 and the input end of the boosting module U1, and the control end of the voltage comparison circuit is connected with the second power supply B2;

the voltage comparison circuit is used for disconnecting the connection relation between the first power supply B1 and the input of the boosting module U1 when the second power supply B2 is powered down.

In this embodiment, when the second power supply B2 is powered down, the voltage comparison circuit is arranged, the connection between the first power supply B1 and the input end of the boost module U1 is disconnected, so that the first power supply B1 stops supplying power to the boost module U1, in the power down process of the second power supply B2, if the third NMOS transistor Q3 and the fourth NMOS transistor Q4 are simultaneously turned on due to the disorder of the control time sequence of the time sequence control module U3, because the boost module U1 has no input voltage, the third NMOS transistor Q3 and the fourth NMOS transistor Q4 cannot be damaged, and the use reliability of the voltage regulation circuit is improved.

In one embodiment, as shown in fig. 4, the voltage comparison circuit includes a voltage regulation module, a switching element, and a voltage comparator U5.

One end of the voltage regulating module is connected with a first power supply B1.

The switching element is connected between the input terminal of the boost module U1 and the first power supply B1.

A first input of the voltage comparator U5 is connected to a second power supply B2.

And a second input end of the voltage comparator U5 is connected with the voltage regulating module.

The output terminal of the voltage comparator U5 is connected to the control terminal of the switching element.

The voltage comparator U5 is used to control the switching element to disconnect the connection relationship between the first power supply B1 and the input of the boost module U1 when the second power supply B2 is powered down.

In the present embodiment, the power terminal of the voltage comparator U5 is connected to the first power supply B1, and the ground terminal of the voltage comparator U5 is connected to the ground terminal GND.

In this embodiment, the input voltage of the first input terminal of the voltage comparator U5 is equal to the output voltage of the second power supply B2, the input voltage of the second input terminal of the voltage comparator U5 is smaller than the output voltage of the second power supply B2 after power-on, and the input voltage of the second input terminal of the voltage comparator U5 is larger than the output voltage of the second power supply B2 after power-off.

For example, if the output voltage of the second power supply B2 is 3.3V, the input voltage of the first input terminal of the voltage comparator U5 is 3.3V, and the input voltage of the second input terminal of the voltage comparator U5 may be set to 2 to 3V.

In this embodiment, when the input voltage of the first input end of the voltage comparator U5 is greater than the input voltage of the second input end of the voltage comparator U5, it indicates that the second power supply B2 is in the power-on state, that is, the timing control module U3 is in the power-on state, the output end of the voltage comparator U5 outputs a first level signal, the voltage comparator U5 outputs the first level signal to control the conduction of the sixth NMOS transistor Q6, the first power supply B1 supplies power to the voltage boost module U1, and the voltage regulating circuit operates normally;

when the input voltage of the first input end of the voltage comparator U5 is not greater than the input voltage of the second input end of the voltage comparator U5, it is described that the second power supply B2 starts to power down, the timing control module U3 starts to power down, the output end of the voltage comparator U5 outputs a second level signal, the voltage comparator U5 outputs the second level signal to control the sixth NMOS transistor Q6 to turn off, the first power supply B1 cannot continue to supply power to the voltage boost module U1, the voltage regulating circuit stops working, and the situation that the third NMOS transistor Q3 and the fourth NMOS transistor Q4 may be all turned on when the timing control module U3 is powered down is effectively avoided, the first power supply B1 continues to supply power to the voltage boost module U1, and the use reliability of the voltage regulating circuit is ensured.

In the present embodiment, the signals of the first level signal and the second level signal are opposite.

For example, the first level signal is a high level signal, and at this time, the second level signal is a low level signal.

For another example, the first level signal is a low level signal, and the second level signal is a high level signal.

In one embodiment, as shown in fig. 4, the voltage regulating module includes a first resistor R1 and a second resistor R2.

A first end of the first resistor R1 is connected to the first power supply B1, a second end of the first resistor R1 is connected to a first end of the second resistor R2, and a second end of the second resistor R2 is connected to the ground GND.

A second input terminal of the voltage comparator U5 is connected to a second terminal of the first resistor R1.

In this embodiment, the voltage regulating module is arranged to regulate the input voltage of the second input end of the voltage comparator U5, because the output voltage of the second power supply B2 is far smaller than the output voltage of the first power supply B1, the input voltage of the second input end of the voltage comparator U5 is smaller than the output voltage of the second power supply B2 after power-on, that is, the input voltage of the second input end of the voltage comparator U5 is far smaller than the output voltage of the first power supply B1, the voltage division effect of the first resistor R1 and the second resistor R2 is considered, and the resistance value of the first resistor R1 is larger than the resistance value of the second resistor R2.

In one embodiment, as shown in fig. 4, the switching element includes a sixth NMOS transistor Q6.

The output end of the voltage comparator U5 is connected with the grid electrode of the sixth NMOS tube Q6.

The drain of the sixth NMOS transistor Q6 is connected to the first power supply B1.

And the source electrode of the sixth NMOS tube Q6 is connected with the input end of the boosting module U1.

In this embodiment, the sixth NMOS transistor Q6 is a fet switch, and the sixth NMOS transistor Q6 may be an enhancement-mode N-channel MOS transistor.

The embodiment of the invention also provides electronic equipment which comprises any one of the voltage regulating circuits provided in the circuit embodiment part.

In this embodiment, the electronic device may be a mobile phone, a tablet computer, a notebook computer, a palm computer, or the like.

In this embodiment, since the electronic device provided in the embodiment of the present invention includes any one of the protection circuits provided in the embodiment of the voltage regulating circuit, the electronic device provided in the embodiment of the present invention can implement the same function as any one of the voltage regulating circuits provided in the embodiment of the voltage regulating circuit.

It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one.. Said.", it is not intended to exclude that an additional identical element is present in a process, method, article or apparatus that comprises the same element.

While embodiments of the invention have been shown and described, it will be understood by those of ordinary skill in the art that: various changes, modifications, substitutions and alterations can be made to the embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the claims and their equivalents.

Claims

1. A voltage regulation circuit, comprising:

a first power supply;

the input end of the boosting module is connected with the first power supply;

the input end of the voltage reduction module is connected with the output end of the voltage boosting module, and the output end of the voltage reduction module is used for outputting voltage to an electric load;

2. The voltage regulating circuit of claim 1, wherein the protection circuit comprises a voltage conversion circuit, an input terminal of the voltage conversion circuit is connected to the first power supply, and an output terminal of the voltage conversion circuit is connected to a power supply terminal of the timing control module.

3. The voltage regulation circuit of claim 2, wherein the voltage conversion circuit comprises an LDO module;

the input end of the LDO module and the enabling end of the LDO module are respectively connected with the first power supply, and the output end of the LDO module is connected with the power supply end of the time sequence control module.

4. The voltage regulation circuit of claim 2, wherein the voltage conversion circuit comprises a DC-DC conversion module;

the input end of the DC-DC conversion module is connected with the first power supply, and the output end of the DC-DC conversion module is connected with the power supply end of the time sequence control module.

5. The voltage regulation circuit of claim 1, further comprising a second power supply;

the second power supply is connected with a power supply end of the time sequence control module;

the protection circuit is connected between the first power supply and the input end of the boosting module, and the control end of the protection circuit is connected with the second power supply;

the protection circuit is used for disconnecting the connection relation between the first power supply and the input of the boosting module when the second power supply is powered off.

6. The voltage regulation circuit of claim 5, wherein the protection circuit comprises a voltage comparison circuit;

the voltage comparison circuit is connected between the first power supply and the input end of the boosting module, and the control end of the voltage comparison circuit is connected with the second power supply;

the voltage comparison circuit is used for disconnecting the connection relation between the first power supply and the input of the boosting module when the second power supply is powered off.

7. The voltage regulating circuit of claim 6, wherein the voltage comparison circuit comprises a voltage regulating module, a switching element, and a voltage comparator;

one end of the voltage regulating module is connected with the first power supply;

the switching element is connected between the input end of the boost module and the first power supply;

the first input end of the voltage comparator is connected with the second power supply;

the second input end of the voltage comparator is connected with the voltage regulating module;

the output end of the voltage comparator is connected with the control end of the switching element;

the voltage comparator is used for controlling the switch element to disconnect the connection relation between the first power supply and the input of the boosting module when the second power supply is powered off.

8. The voltage regulation circuit of claim 7, wherein the voltage regulation module comprises a first resistor and a second resistor;

the first end of the first resistor is connected with the first power supply, the second end of the first resistor is connected with the first end of the second resistor, and the second end of the second resistor is connected with the ground terminal;

and the second input end of the voltage comparator is connected with the second end of the first resistor.

9. The voltage regulating circuit according to claim 8, wherein the switching element comprises a sixth NMOS transistor;

the output end of the voltage comparator is connected with the grid electrode of the sixth NMOS tube;

the drain electrode of the sixth NMOS tube is connected with the first power supply;

and the source electrode of the sixth NMOS tube is connected with the input end of the boosting module.

10. An electronic device, comprising: a voltage regulation circuit as claimed in any one of claims 1 to 9.