CN115148272A

CN115148272A - Memory address determination method and electronic equipment

Info

Publication number: CN115148272A
Application number: CN202210769193.1A
Authority: CN
Inventors: 蒋国兵
Original assignee: Changxin Memory Technologies Inc
Current assignee: Changxin Memory Technologies Inc
Priority date: 2022-06-30
Filing date: 2022-06-30
Publication date: 2022-10-04

Abstract

The disclosure provides a memory address determination method and an electronic device. The method comprises the following steps: determining a first physical address set corresponding to each memory bank of a memory to be tested; sequentially using a plurality of first feature functions in a first preset feature function set and a plurality of physical addresses in each first physical address set to carry out bitwise AND operation so as to determine an array mapping function corresponding to the memory to be tested; determining a second physical address set corresponding to each memory bank according to the array mapping function; determining a third physical address set corresponding to each memory bank row in a second physical address set corresponding to each memory bank; and sequentially using a plurality of second characteristic functions in the second preset characteristic function set and each physical address in the third physical address set to carry out bitwise AND operation so as to determine a row address mapping function corresponding to the third physical address set. The embodiment of the disclosure can measure the mapping relation between the physical address of the memory and the position of the storage unit of the memory.

Description

Memory address determination method and electronic equipment

Technical Field

The present disclosure relates to the field of integrated circuit testing technologies, and in particular, to a method for determining a memory address and an electronic device.

Background

In a modern computer system, in order to improve memory access efficiency and protect memory data, a memory controller manufacturer may intentionally hide a mapping relationship between a system physical address and a memory address, and may not determine where a storage unit corresponding to a memory access event is located in a memory according to the physical address, or may not know an association relationship between the physical addresses.

However, in the manufacturing of integrated circuits, there are some scenarios that it is urgently necessary to know the mapping relationship between the system physical address and the memory address, such as location analysis of a failed memory cell (a memory cell corresponding to a certain physical address is found to be failed in a test, a backend technician is required to perform technical analysis on the failed memory cell, and at this time, a specific location of the failed cell needs to be found) or a Rowhammer (Rowhammer) test of the system, and in the related art, instruments such as an oscilloscope and a logic analyzer are usually used to assist in performing the test of the corresponding relationship between the physical address and the memory address of the memory cell, which is inefficient.

It is to be noted that the information disclosed in the above background section is only for enhancement of understanding of the background of the present disclosure, and thus may include information that does not constitute prior art known to those of ordinary skill in the art.

Disclosure of Invention

The present disclosure is directed to a method for determining a memory address and an electronic device, which are used to overcome, at least to some extent, the problem of inefficiency in a process of determining a correspondence between a physical address and a memory address.

According to a first aspect of the embodiments of the present disclosure, there is provided a memory address determination method, including: determining a first physical address set corresponding to each memory bank of a memory to be tested according to whether the access time for continuously accessing two physical addresses exceeds a preset time length, wherein the first physical address set comprises a plurality of physical addresses belonging to the same memory bank; sequentially using a plurality of first feature functions in a first preset feature function set and a plurality of physical addresses in each first physical address set to carry out bitwise AND operation so as to determine a mapping function set corresponding to the memory to be tested; determining an array mapping function corresponding to the memory to be tested according to the mapping function set; determining a second physical address set corresponding to each memory bank according to the array mapping function, wherein the second physical address set comprises a plurality of physical addresses belonging to the same memory bank; and determining a third physical address set corresponding to each memory bank row in a second physical address set corresponding to each memory bank according to whether the access time for continuously accessing the two physical addresses exceeds the preset time length, wherein the third physical address set comprises a plurality of physical addresses belonging to the same memory unit row.

In an exemplary embodiment of the present disclosure, according to whether an access time for continuously accessing two physical addresses exceeds a preset time period, the determining a first physical address set corresponding to each memory bank of a memory to be tested includes: randomly determining a first physical address, and recording the first physical address into a first physical address set corresponding to a first memory bank; randomly determining a second physical address, and carrying out continuous access test on the first physical address and the second physical address; and when the access time of the continuous access test exceeds a preset time length, recording the second physical address into a first physical address set corresponding to the first memory bank, and when the access time does not exceed the preset time length, recording the second physical address into a first physical address set corresponding to a second memory bank.

In an exemplary embodiment of the present disclosure, according to whether an access time for continuously accessing two physical addresses exceeds a preset time period, the determining a first physical address set corresponding to each memory bank of a memory to be tested further includes: when a first physical address set corresponding to a plurality of memory banks is not an empty set, randomly determining a third physical address, and respectively performing the continuous access test on the third physical address and one physical address in each first physical address set; when the access time of any one continuous access test exceeds the preset time length, the third physical address is counted into a first physical address set corresponding to another physical address in the continuous access test; when the access time of all the continuous access tests does not exceed the preset time length, recording the third physical address into a first physical address set corresponding to a new memory bank; and repeating the steps until the physical addresses in the first physical address set corresponding to each memory bank all reach a first preset value.

In an exemplary embodiment of the disclosure, the counting, when the access time of any one continuous access exceeds the preset time length, the third physical address into the first physical address set corresponding to another physical address in the continuous access test includes: and when the number of the physical addresses in the first physical address set corresponding to the other physical address does not reach a first preset value, the third physical address is added into the first physical address set corresponding to the other physical address, otherwise, the third physical address is discarded.

In an exemplary embodiment of the disclosure, the counting the third physical address into a first physical address set corresponding to a new memory bank when the access time of all the consecutive accesses does not exceed the preset time duration includes: when all the access time of the continuous access does not exceed the preset time length, selecting the physical address continuously accessed with the third physical address in each first physical address set again, and performing continuous access test again; when the second time judges that the access time of all the continuous accesses does not exceed the preset time length, whether the number of the memory banks of which the first physical address set is not empty is equal to the number of all the memory banks corresponding to the memory to be tested is judged; if yes, selecting the physical address which is continuously accessed with the third physical address from each first physical address set again, and performing continuous access test again; and if not, the third physical address is added into the first physical address set corresponding to a new memory bank.

In an exemplary embodiment of the disclosure, the sequentially using a plurality of first feature functions in a first preset feature function set to perform a bitwise and operation with a plurality of physical addresses in each first physical address set to determine a mapping function set corresponding to the memory to be tested includes: performing bitwise AND operation on one first characteristic function and one physical address, determining the number of bits equal to 1 in a calculation result, recording the first characteristic function and the physical address as a first type of mapping when the number of bits is an odd number, and recording the first characteristic function and the physical address as a second type of mapping when the number of bits is an even number; when each physical address in one of the first feature function and the first physical address set is the first type of mapping or the second type of mapping, determining that the first feature function and the first physical address set have mapping consistency; and when the mapping consistency exists between one first characteristic function and the first physical address set corresponding to each memory bank, recording the first characteristic function into the mapping function set corresponding to the memory to be tested.

In an exemplary embodiment of the disclosure, the physical addresses and the first feature functions are M-bit binary numbers, any two of the first feature functions are completely different, and performing bitwise and operation on a plurality of first feature functions in a first preset feature function set and a plurality of physical addresses in each first physical address set in sequence to determine a mapping function set corresponding to the memory to be tested includes: determining a plurality of feature function sets in the first preset feature function set, wherein the first feature functions in the same feature function set have the same digits equal to 1, and the first feature functions in different feature function sets have different digits equal to 1; setting a feature function group with the minimum digit number equal to 1 as a feature function group to be tested in a feature function group which is not tested currently; determining a first feature function to be detected in the feature function group to be detected, performing bitwise AND operation on the first feature function to be detected and a plurality of physical addresses in each first physical address set, and determining another first feature function to be detected in the feature function group to be detected again for operation until all first feature functions corresponding to the feature function group to be detected complete operation; and re-determining the feature function groups to be detected until each feature function group finishes operation.

In an exemplary embodiment of the disclosure, the determining, according to the mapping function set, an array mapping function corresponding to the memory to be tested includes: and operating the mapping function set by using a Gaussian elimination method to obtain the array mapping function, wherein the array mapping function comprises a plurality of linearly independent first characteristic functions.

In the disclosureIn an exemplary embodiment, the array mapping function includes X first feature functions, 2 ^X M, where m is the number of memory banks in the memory to be tested, and the determining, according to the array mapping function, the second physical address set corresponding to each memory bank includes: randomly determining a plurality of target physical addresses; carrying out bitwise AND operation on the ith first characteristic function in the array mapping function and the target physical address, recording the ith bit of the array address of the target physical address as 1 when the number of bits of 1 in the operation result is an odd number, and recording the ith bit of the array address of the target physical address as 0 when the number of bits of 1 in the operation result is an even number, wherein i is more than or equal to 1 and is less than or equal to X; performing bitwise AND operation on each first characteristic function in the array mapping function and the target physical address to determine an array address of the target physical address; determining array addresses corresponding to the target physical addresses, and recording the target physical addresses with the same array addresses as the second physical address set corresponding to one memory bank.

In an exemplary embodiment of the disclosure, the determining, in accordance with whether an access time for consecutively accessing two physical addresses exceeds a preset time period, a third physical address set corresponding to each memory bank row in the second physical address set corresponding to each memory bank includes: randomly selecting a fourth physical address in the second physical address set corresponding to the memory bank to be tested, and recording the fourth physical address into the third physical address set corresponding to the first memory cell row in the memory bank to be tested; randomly determining a fifth physical address in the second physical address set corresponding to the memory bank to be tested, and performing continuous access test on the fourth physical address and the fifth physical address; when the access time does not exceed the preset time length, recording the fifth physical address into a third physical address set corresponding to the first memory cell row; when the access time of the continuous access test exceeds a preset time length, recording the fifth physical address into a third physical address set corresponding to a second storage unit row; and performing the continuous access test on each physical address in the second physical address set corresponding to the memory bank to be tested to determine a third physical address set corresponding to each memory cell row in the memory bank.

In an exemplary embodiment of the disclosure, the performing a bit and operation sequentially using a plurality of second feature functions in a second preset feature function set and each physical address in the third physical address set to determine a row address mapping function corresponding to the third physical address set includes: performing bitwise AND operation on one second characteristic function and each physical address in one third physical address set to obtain a plurality of operation results; determining the second characteristic function as a row address mapping function corresponding to the third physical address set when the operation results of the second characteristic function and each physical address in the third physical address set are the same; and when any one operation result is different from other operation results, another second characteristic function is determined again for operation.

In an exemplary embodiment of the disclosure, the physical address and the second feature function are both M-bit binary numbers, a bit width of the row address of the memory to be tested is P, and P bits of the second feature function except for the lowest six bits are 1.

In an exemplary embodiment of the present disclosure, further comprising: randomly determining a plurality of groups of physical addresses, wherein each group of physical addresses comprises two different physical addresses; performing multiple continuous access tests on each group of physical addresses, and recording the median or average value of access time of the multiple continuous access tests as continuous access duration corresponding to each group of physical addresses; obtaining statistical distribution of a plurality of continuous access durations corresponding to the plurality of groups of physical addresses; and determining the preset duration according to the statistical distribution.

In an exemplary embodiment of the disclosure, the performing a plurality of consecutive access tests on each group of the physical addresses includes: after each of the sequential access tests, a cache line flush instruction is executed.

In an exemplary embodiment of the present disclosure, the determining a memory address corresponding to an access event according to an array mapping function and a row address mapping function includes: determining a physical address corresponding to the access event; determining a target array address corresponding to the physical address according to the physical address and the array mapping function; determining a target row address in the target array address corresponding to the physical address according to the physical address and the row address mapping function; and setting the target array address and the target row address as a memory address corresponding to the access event.

According to a second aspect of the present disclosure, there is provided an electronic device comprising: a memory to be tested; and a processor coupled to the memory under test, the processor configured to perform the memory address determination method as described in any one of the above based on instructions stored in the memory to determine an array mapping function and a row address mapping function between physical addresses of the processor and memory cells of the memory under test.

According to the embodiment of the disclosure, whether two physical addresses are located in the same array and in the same row of the same array is determined according to whether the access time for continuously accessing the two physical addresses exceeds the preset time length, the physical address sets corresponding to each row in each memory bank and each memory can be respectively determined, the array mapping function and the row address mapping function of the memory to be tested are further determined according to the relation between the physical address sets and the characteristic function, and the memory address corresponding to each access event (including a failure access event) is further determined according to the array mapping function and the row address mapping function.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present disclosure and together with the description, serve to explain the principles of the disclosure. It is to be understood that the drawings in the following description are merely exemplary of the disclosure, and that other drawings may be derived from those drawings by one of ordinary skill in the art without the exercise of inventive faculty.

Fig. 1 is a flow chart of a memory address determination method in an exemplary embodiment of the disclosure.

FIG. 2 is a diagram illustrating a row conflict during a memory access.

Fig. 3 is a schematic diagram of determining a judgment row conflict occurrence condition in one embodiment of the present disclosure.

FIG. 4 is a diagram illustrating a statistical distribution of a number of physical addresses versus access time in one embodiment of the present disclosure.

Fig. 5A and 5B are a flowchart of step S1 in one embodiment of the present disclosure.

FIG. 6 is a sub-flowchart of step S2 in one embodiment of the present disclosure.

FIG. 7 is a schematic diagram of Gaussian elimination in one embodiment of the disclosure.

Fig. 8 is a sub-flowchart of step S5 in one embodiment of the present disclosure.

Detailed Description

Example embodiments will now be described more fully with reference to the accompanying drawings. Example embodiments may, however, be embodied in many different forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art. The described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided to give a thorough understanding of embodiments of the disclosure. One skilled in the relevant art will recognize, however, that the subject matter of the present disclosure can be practiced without one or more of the specific details, or with other methods, components, devices, steps, and the like. In other instances, well-known technical solutions have not been shown or described in detail to avoid obscuring aspects of the present disclosure.

Further, the drawings are merely schematic illustrations of the present disclosure, in which the same reference numerals denote the same or similar parts, and thus, a repetitive description thereof will be omitted. Some of the block diagrams shown in the figures are functional entities and do not necessarily correspond to physically or logically separate entities. These functional entities may be implemented in the form of software, or in one or more hardware modules or integrated circuits, or in different networks and/or processor devices and/or microcontroller devices.

The following detailed description of exemplary embodiments of the disclosure refers to the accompanying drawings.

Fig. 1 is a flow chart of a memory address determination method in an exemplary embodiment of the present disclosure.

Referring to fig. 1, a memory address determination method 100 may include:

the method comprises the steps that S1, a first physical address set corresponding to each memory bank of a memory to be tested is determined according to whether the access time for continuously accessing two physical addresses exceeds a preset time length, wherein the first physical address set comprises a plurality of physical addresses belonging to the same memory bank;

s2, sequentially using a plurality of first feature functions in a first preset feature function set and a plurality of physical addresses in each first physical address set to carry out bitwise AND operation so as to determine a mapping function set corresponding to the memory to be tested;

s3, determining an array mapping function corresponding to the memory to be tested according to the mapping function set;

s4, determining a second physical address set corresponding to each memory bank according to the array mapping function, wherein the second physical address set comprises a plurality of physical addresses belonging to the same memory bank;

step S5, according to whether the access time for continuously accessing two physical addresses exceeds the preset time length, determining a third physical address set corresponding to each memory bank row in a second physical address set corresponding to each memory bank, wherein the third physical address set comprises a plurality of physical addresses belonging to the same memory cell row;

step S6, sequentially using a plurality of second feature functions in a second preset feature function set and each physical address in the third physical address set to carry out bitwise AND operation so as to determine a line address mapping function corresponding to the third physical address set;

and S7, determining a memory address corresponding to the access event according to the array mapping function and the row address mapping function.

The steps of the memory address determination method 100 are explained in detail below.

In step S1, a first physical address set corresponding to each memory bank of the memory to be tested is determined according to whether access time for continuously accessing two physical addresses exceeds a preset time period, where the first physical address set includes multiple physical addresses belonging to the same memory bank.

A Memory array of a DRAM (Dynamic Random Access Memory) is composed of a plurality of banks (banks), each of which includes a plurality of rows (rows) and a plurality of columns (columns) of Memory cells (cells). Each memory bank corresponds to a row buffer (row buffer), and the row buffer is used for performing signal amplification and data buffering on the memory cell. When a memory master (memory controller) accesses a certain memory cell or cells in a certain row of the DRAM, the row of memory cells is fully opened (activated), and the amplified signals in the memory cells are stored in a row buffer, so as to read the data in the row buffer and to re-write the data in the row memory back to the memory cells after reading. When the memory controller accesses different lines of the same memory bank, firstly, data of a previous access line is read through a line memory, then the data of the previous access line is written back to a memory cell of the previous access line, a line to be accessed later is opened, and the data in the memory cell of the later access line is amplified and then temporarily stored in a line buffer to realize reading. This access procedure increases the memory access time by additionally involving a process of waiting for the contents of the line buffer to be written back to the memory location of the previously accessed line, and is therefore called a line conflict (row conflict).

FIG. 2 is a diagram illustrating a row conflict during a memory access.

Referring to FIG. 2, when accessing a pair of memory addresses, e.g., { addr _0, addr \u1 } in succession, after accessing the first address and starting the access to the second address, the following 3 cases occur:

201. the second address and the first address belong to the same row of the same memory bank 21, the same row buffer 21A is used, and the corresponding data accessed for the second time is just in the row buffer 21A, no row conflict (row conflict) occurs, and the access speed is very high;

202. the second address and the first address belong to

different memory banks

21 and 22,

different line buffers

21A and 22A are used for access, no line conflict occurs, and the access speed is high;

203. the second address and the first address belong to different lines of the same memory bank 21, the same line buffer 21A is used, the data in the line buffer needs to be written back to the memory cell of the line corresponding to the first address first, then the line memory cell corresponding to the second address is opened, the content is read into the line buffer 21A, the access speed is slow, and line conflict occurs.

The inventor of the present application proposes a method for determining a memory address in the present application according to the above DRAM access characteristics.

First, before the actual test is performed, a condition for judging the occurrence of a line conflict may be determined.

Referring to fig. 3, in one embodiment, the method 100 further comprises:

step S01, randomly determining a plurality of groups of physical addresses, wherein each group of physical addresses comprises two different physical addresses;

s02, performing multiple continuous access tests on each group of physical addresses, and recording the median or average value of access time of the multiple continuous access tests as continuous access duration corresponding to each group of physical addresses;

s03, acquiring statistical distribution of a plurality of continuous access durations corresponding to a plurality of groups of physical addresses;

and S04, determining a preset time length according to the statistical distribution.

In the embodiment shown in step S02, a pair of physical addresses (in this disclosure, a physical address is a system physical address used by a processor to access a storage/memory) may be randomly accessed first, and r times of consecutive accesses are performed, and the access time of the pair of physical addresses is obtained by taking a median or an average. Then repeating the step p times to obtain m pairs of address access time distribution. To ensure that the results are accurate, the values of r and p may be suitably larger, such as r =40000 and p =100000. To ensure that memory accesses operate successfully to DRAM, rather than cache operations within the system, each physical address is accessed followed by a cache line flush (clflush) instruction. The access time measurement may be implemented by an rdtscp or like instruction.

By plotting the obtained statistics of access times into a graph, a statistical distribution of access times over a large number of physical addresses can be obtained, as shown in fig. 4.

As can be seen from fig. 4, the access time interval for a large number of physical address pairs can be divided into 2 clusters: the cluster on the right represents that row conflict (row conflict) occurs during continuous access, so that the access time is longer, and the cluster on the left represents that no row conflict occurs in the continuous access device, so that the access time is shorter. A value, such as the value 260ms in fig. 3, may be selected as an access time determination threshold for determining whether a line collision occurs in consecutive accesses according to the statistical distribution, i.e., the preset time duration in steps S1 and S5.

According to the condition for determining the occurrence of the row conflict obtained in the embodiment shown in fig. 3, a large number of physical addresses of different rows corresponding to the same bank can be determined.

Fig. 5A and 5B are flowcharts of step S1 in one embodiment of the present disclosure.

Fig. 5A shows a sub-flow of step S1 corresponding to a case where all first physical address sets are empty sets, fig. 5B shows a sub-flow of step S1 corresponding to a case where at least one first physical address set is not an empty set, and the flows shown in fig. 5A and 5B cooperate together to form a specific operation of step S1.

Referring to fig. 5A, in an embodiment, when all the first physical address sets are empty, step S1 may include:

s11, randomly determining a first physical address, and recording the first physical address into a first physical address set corresponding to a first memory bank;

step S12, randomly determining a second physical address, and carrying out continuous access test on the first physical address and the second physical address;

step S13, judging whether the access time of the continuous access test exceeds a preset time length, if so, entering step S14 to record a second physical address into a first physical address set corresponding to the first memory bank; if not, step S15 is entered to record the second physical address into the first physical address set corresponding to the second memory bank.

Referring to fig. 5B, in an embodiment, when the first set of physical addresses corresponding to the plurality of memory banks is not an empty set, step S1 may include:

step S16, randomly determining a third physical address, and respectively carrying out continuous access tests on the third physical address and one physical address in each first physical address set;

and S17, judging whether the access time of any one time of continuous access test exceeds a preset time length, if so, entering a step S18 to count the third physical address into the first physical address set corresponding to another physical address in the time of continuous access test, and if not, entering a step S19 to count the third physical address into the first physical address set corresponding to a new memory bank.

And repeating the steps until the physical addresses in the first physical address set corresponding to each memory bank all reach a first preset value.

Wherein, step S18 further includes:

step S181, determining whether the number of physical addresses in the first physical address set corresponding to another physical address reaches a first preset value, if yes, entering step S182 to add a third physical address into the first physical address set corresponding to another physical address, otherwise, entering step S183 to discard the third physical address.

Step S19 again includes:

step S191, selecting the physical address which is continuously accessed with the third physical address in each first physical address set again, and performing continuous access test again;

step S192, judging whether the access time of any one continuous access test exceeds the preset time length for the second time, and if so, entering step S18; otherwise, go to step S193;

step S193, judging whether the number of the memory banks of which the first physical address set is not empty is equal to the number of all the memory banks corresponding to the memory to be tested, if so, returning to the step S191 to select the physical address which is continuously accessed with the third physical address in each first physical address set again, and performing continuous access test again; otherwise, step S194 is executed to count the third physical address into the first physical address set corresponding to the new memory bank.

The reason why the number of addresses in each first physical address set is limited in step S18 is to reduce the amount of computation in the subsequent calculation of the feature function.

In step S19, a physical address that is continuously accessed with the third physical address is selected again in each first physical address set, and a continuous access test is performed again, because the access time of the continuous access does not exceed the preset time length, there are two situations, one is that the third physical address is not an address corresponding to a memory bank whose first physical address set is not empty, that is, the third physical address set corresponds to another new memory bank; in another case, the physical address in the first set of physical addresses selected currently has a physical address in the same bank and the same row as the third physical address. In order to avoid the second situation, when the access time of all the continuous accesses does not exceed the preset time length, a batch of addresses can be selected from the first physical address set again, and the test is performed again.

If the access time of all the continuous accesses for the second time does not exceed the preset time length and the first physical address set corresponding to the memory bank is empty, it can be determined that the third physical address set corresponds to the new memory bank at a high probability. In the embodiment shown in fig. 5B, it is determined that the third physical address set corresponds to the new memory bank only by determining that the access time of two consecutive accesses does not exceed the preset time length.

If the number of the first physical address sets which are not empty is equal to the number of the memory banks, it is indicated that the third physical address does not correspond to a new memory bank, and a batch of physical addresses which are in the same row as the memory bank of the third physical address still exist in the batch of physical addresses compared this time, and a batch of physical addresses need to be selected again for testing until the physical addresses in the different row from the memory bank of the third physical address are determined, and the memory bank corresponding to the third physical address set is determined.

It should be noted that, although the setting in step S191 may prevent the third physical address and the physical address in the same bank and the same row thereof from being located in different first physical address sets to some extent, in order to further ensure that each first physical address set corresponds to different banks, and prevent multiple first physical address sets from being generated by using the physical addresses in the same bank and the same row, when the continuous access test is performed on the third physical address and one physical address in each first physical address set in step S16 and step S191, respectively (assuming that the number of the first physical address sets is x), it may be determined whether the access time of any one continuous access test exceeds the preset time after the test time of x continuous access tests is acquired.

In the x access times, if one and only one access time exceeds a preset time length, determining that the third physical address corresponds to a memory bank of another physical address in the access time; if two or more access times exceed the preset time length, the third physical address simultaneously corresponds to a plurality of first physical address sets, and the plurality of first physical address sets belong to the same memory bank and need to be merged; if none of the access times exceeds the preset time length, it can be determined that all of the access times of the consecutive accesses do not exceed the preset time length, and then the process can proceed to step S19 or step S193 for the next step.

Similarly, in step S14 of fig. 5A, before the second physical address is recorded in the first physical address set corresponding to the second memory bank, one physical address may be selected again from the first physical address set to perform the continuous access test, so as to prevent the physical address in the first continuous access test and the second physical address from corresponding to the same memory bank and the same row.

Through the process shown in fig. 5A and 5B, a certain number of physical addresses can be found for each memory bank, a first physical address set (set) corresponding to each memory bank is generated, and it is convenient to generalize the rule of the physical address corresponding to the memory bank in the following, so as to obtain the physical address characteristic function of the memory bank. The number of banks in the memory module granule can refer to JEDEC specifications, for example, there are 16 banks in an 8GbX8 memory.

Assuming that the number of memory banks in the memory to be tested is m, when step S1 ends, m first physical address sets can be obtained, including:

m＝Channels*(DIMMs/Channel)*(Ranks/DIMM)*(Banks/rank) (1)

wherein, banks/rank is the number of Banks In each rank (bank) In the Memory to be tested, ranks/DIMM is the number of Ranks In each DIMM (Dual In-line Memory Module), DIMMs/Channels is the number of DIMMs In each Channel, and Channels is the number of Channels In the Memory to be tested.

The above-mentioned m value can be used in step S193 as a judgment basis.

In step S2, a plurality of first feature functions in a first preset feature function set and a plurality of physical addresses in each first physical address set are sequentially used to perform bitwise and operation, so as to determine a mapping function set corresponding to the memory to be tested.

After determining a plurality of physical addresses (i.e., the first set of physical addresses) corresponding to a memory bank, features may be extracted for the plurality of physical addresses.

In the art, a mapping function (Func-mask) is generally used to map a memory address with a physical address, and for a memory address, the memory address is calculated with the mapping function, and the obtained calculation result is the physical address corresponding to the memory address. The objective of the disclosed embodiment is to find the unknown mapping function.

It can be determined that there is a commonality in the influence of the mapping function on the memory addresses having a common point (e.g. the same bank, the same row), and after the analysis, it is found that the plurality of memory addresses having a common point are calculated by the mapping function, the obtained plurality of physical addresses have parity consistency, that is, the number of bits of 1 in the physical addresses is odd or even. In addition, the mapping function and the physical address are binary numbers with the same number of bits.

Based on the above analysis, the inventor of the present application sets a method for finding a mapping function set corresponding to a first physical address set in step S2.

In the embodiment of the present disclosure, in step S2, a first preset feature function set may be obtained first. The first preset characteristic function comprises a plurality of different first characteristic functions, each first characteristic function and the physical address are M-bit binary numbers, and M is a positive integer greater than or equal to 1. Each first feature function may be a mapping function of a set of mapping functions corresponding to a memory bank.

And after carrying out bitwise AND operation on a first characteristic function and a physical address, determining the number of bits which is equal to 1 in a calculation result, recording the first characteristic function and the physical address as a first type of mapping when the number of bits is an odd number, and recording the first characteristic function and the physical address as a second type of mapping when the number of bits is an even number. For example, the calculation result "10011010" of the 8-bit first characteristic function and the 8-bit physical address has an even number of 1 s, the corresponding first characteristic function and the corresponding physical address are recorded as the second type mapping, the calculation result "00011000" has an odd number of 1 s, and the corresponding first characteristic function and the corresponding physical address are recorded as the first type mapping.

According to the above arrangement, a first characteristic function may be selected and calculated with each physical address in a first set of physical addresses. If the first characteristic function and each physical address in the first set of physical addresses are both a first type of mapping or both a second type of mapping, it may be determined that the first characteristic function has mapping consistency with the first set of physical addresses (i.e., the memory bank), i.e., the first characteristic function has characteristics of a mapping function of the memory bank.

Then, the first physical address set may be replaced to perform calculation, and when the first feature function and the first physical address set corresponding to each memory bank have mapping consistency, it is described that the first feature function has the feature of the mapping function of each memory bank and is one of the mapping function sets of the memory to be tested, and at this time, the first feature function may be recorded in the mapping function set corresponding to the memory to be tested.

It should be noted that the mapping consistency between the same first feature function and different memory banks (the number of bits of the calculation result equal to 1 is odd or even) is not necessarily the same. For example, the number of bits of the calculation result of each physical address in the first set of physical addresses of one first characteristic function and the first memory bank equal to 1 is odd, the number of bits of the calculation result of each physical address in the first set of physical addresses of the first characteristic function and the second memory bank equal to 1 is even, the first characteristic function and the first memory bank have mapping consistency, and the first characteristic function and the second memory bank also have mapping consistency.

Of course, if a first feature function does not have mapping consistency with each physical address in any first physical address set, the first feature function is not necessarily a mapping function of the memory to be tested, and a first feature function may be reselected from the first preset feature function set to perform calculation until a plurality of first feature functions meeting the above requirements are obtained, so as to form a mapping function set corresponding to the memory to be tested.

In an embodiment of the present disclosure, since other features of the mapping function are not known in advance, only the number of bits of the mapping function is known to be equal to M, and the number of first feature functions in the first preset feature function set is huge as the number of binary bits of the physical address, at this time, the order of participation in calculation of the first feature functions may be set according to the features of the first feature functions themselves.

In one embodiment, a plurality of feature function sets in the first preset feature function set may be determined first, the number of bits of the first feature function equal to 1 in the same feature function set is the same, and the number of bits of the first feature function equal to 1 in different feature function sets is different. Then, in the feature function set which is not currently tested, the feature function set with the least number of bits and equal to 1 is set as the feature function set to be tested. And then, determining a first characteristic function to be detected in the characteristic function group to be detected, performing bitwise AND operation on the first characteristic function to be detected and a plurality of physical addresses in each first physical address set, then re-determining another first characteristic function to be detected in the characteristic function group to be detected for operation until all the first characteristic functions corresponding to the characteristic function group to be detected finish operation, and re-determining the characteristic function group to be detected until all the characteristic function groups finish operation.

When the above process is described as a flowchart, the number of bits of the first feature function equal to 1 in one feature function group Gi may be set to be i.

Referring to fig. 6, in one embodiment, step S2 may include:

step S21, determining a plurality of feature function groups G1 to GN in a first preset feature function set, where N is a preset value, N may be equal to the significant digit W of the physical address of the memory, and N may also be smaller than W, and the significant digit W of the physical address of the memory is generally smaller than the bit width M of the physical address of the memory.

Step S22, set i =0.

In step S23, i = i +1 is controlled.

And step S24, selecting a first characteristic function in Gi to participate in calculation, and calculating the mapping consistency with the physical addresses in each first physical address set, wherein the calculation result comprises adding the first characteristic function into the mapping function set or discarding the first characteristic function. After one first feature function is calculated, the process proceeds to step S25.

And step S25, judging whether all the first feature functions in the feature function group Gi participate in calculation, if not, returning to the step S24 to select one first feature function in the Gi to participate in calculation again, and if so, entering the step S26.

And S26, judging whether i is equal to N, namely judging whether all the first feature functions in all the feature function groups are calculated, if not, returning to the step S23 to add 1 to i and selecting the next feature function group. If so, step S2 ends.

For example, the physical addresses in a first set of physical addresses are:

1100 0001 1011 1001 1100 1100 0111 1011，

when i =16, the first feature functions in G16 each have 16 bits as 1, where one of the first feature functions is:

1111 1111 1111 1111 0000 0000 0000 0000，

and carrying out bitwise AND operation on the first characteristic function and the physical address to obtain a calculation result:

1100 0001 1011 1001 0000 0000 0000 0000，

the calculation result has 8 bits as 1, the number of bits as 1 is an even number, and the first characteristic function and the physical address are mapped into a second type.

If the number of bits 1 in the calculation results of the first characteristic function and all the physical addresses in the first physical address set is even, that is, the first characteristic function and the first physical address set are both mapped in the second type, it is indicated that mapping consistency exists between the first characteristic function and the first physical address set. Otherwise, the first feature function is discarded.

And if the first characteristic function and each first physical address set have mapping consistency, adding the first characteristic function into the mapping function set, and otherwise, discarding the first characteristic function.

In the embodiment shown in fig. 5, a 64-bit binary physical address (M = 64) is taken as an example for description, generally, 33-34 bits (W) of the 64-bit (M) physical address correspond to address bits, and at this time, the value of N is set to be less than 33, for example, 30 (N), so that a mapping function set meeting the requirement of the next calculation can be obtained.

And S3, determining an array mapping function corresponding to the memory to be tested according to the mapping function set.

In the combination of the mapping functions obtained in step S2, there may be a plurality of linearly related first feature functions, and therefore, in step S3, the mapping function set may be operated by using a gaussian elimination method to obtain an array mapping function, where the array mapping function includes a plurality of linearly independent first feature functions.

Referring to fig. 7, the mapping function set 71 has 13 first feature functions 711 determined in step S2, and an array mapping function 72 is obtained through a gaussian elimination method, where the array mapping function 72 includes 4 linearly independent first feature functions 711.

The array mapping function 72 is an array mapping function of the memory to be tested, and a plurality of physical addresses having common characteristics can be obtained by calculating a plurality of memory addresses having common points in the memory to be tested using the array mapping function. Similarly, the array mapping function is used to calculate the physical addresses of the same memory bank, and the obtained memory addresses also have the same characteristics, namely the memory address characteristics of the memory bank, which is also called array address coding.

In step S4, a second physical address set corresponding to each memory bank is determined according to the array mapping function, where the second physical address set includes a plurality of physical addresses belonging to the same memory bank.

In step S4, a plurality of target physical addresses can be randomly determined, then the ith first characteristic function in the array mapping function and the target physical addresses are subjected to bitwise AND operation, when the bit number of 1 in the operation result is an odd number, the ith bit of the array address code of the target physical addresses is marked as 1, when the bit number of 1 in the operation result is an even number, the ith bit of the array address code of the target physical addresses is marked as 0, i is more than or equal to 1 and is less than or equal to X, wherein X is the number of the first characteristic functions in the array mapping function, and has 2 ^X And = m, m being the number of banks in the memory under test.

Assume a target physical address is: 1100 0001 1011 1001 1100 0111, the 1 st first characteristic function in the array mapping function is: 1111 1111 1111 1111 1111 1111 0000 0000 0000 0000, 8 bits of the result of the bitwise and operation are 1, and 1 st bit of the array address code of the target physical address is 0.

Next, performing bitwise and operation on each first characteristic function in the array mapping function and the target physical address to determine an array address code of the target physical address. And determining the ith bit of the array address coding Adbank of the target physical address according to the calculation result of the target physical address and the ith first characteristic function Func-mask-i.

For example, assuming that X =4, the array mapping function includes 4 first feature functions, and the bitwise and operation results of the target physical address and the 1 st, 2 nd, 3 rd, and 4 th first feature functions are even 1, odd 1, and odd 1, respectively, the array address of the target physical address is encoded as (0, 1).

According to the above process, the array address codes corresponding to a plurality of target physical addresses are determined, and the target physical addresses with the same array address code are recorded as a second physical address set corresponding to one memory bank. Each second set of physical addresses includes a plurality of target physical addresses corresponding to the same memory bank.

In this step, the plurality of target physical addresses in the second physical address set may include physical addresses in the first physical address set corresponding to the memory bank, but in order to enable the number of target physical addresses corresponding to each memory bank to meet the subsequent calculation requirement on the address mapping function of all rows of each memory bank, the selection range of the target physical addresses may be expanded, that is, a large number of target physical addresses are randomly generated, so that the number of target physical addresses in the second physical address set corresponding to the same memory bank is much greater than the number of physical addresses in the first physical address set.

In step S5, according to whether the access time for continuously accessing the two physical addresses exceeds the preset time length, a third physical address set corresponding to each memory bank row is determined in the second physical address set corresponding to each memory bank, where the third physical address set includes a plurality of physical addresses belonging to the same memory cell row.

For each memory bank, it may be set as a memory bank to be tested at the time of calculation. Then, a fourth physical address (also called a base address) can be randomly selected from the second physical address set corresponding to the memory bank to be tested, and the fourth physical address is recorded into a third physical address set corresponding to the first memory cell row in the memory bank to be tested; randomly determining a fifth physical address in a second physical address set corresponding to the memory to be tested, and carrying out continuous access test on the fourth physical address and the fifth physical address; when the access time does not exceed the preset time length, recording a fifth physical address into a third physical address set corresponding to the first storage unit row; and when the access time of the continuous access test exceeds the preset time length, recording the fifth physical address into a third physical address set corresponding to the second memory cell row. And performing the continuous access test on each physical address in the second physical address set corresponding to the memory bank to be tested according to the logic to determine a third physical address set corresponding to each memory cell row in the memory bank.

The above logic is converted into a flowchart, and the total number of the memory banks is set to m, one memory bank Bi with sequence number i corresponds to the second physical address set Adi, the number of the target physical addresses in the second physical address set Adi is Qi, and the sequence number of the target physical addresses is j.

Referring to fig. 8, in one embodiment, step S5 may include:

in step S501, i =1 is set.

Step S502, set j =1.

Step S503, setting the ith memory bank Bi as a memory bank Bi to be tested, and setting a value Qi according to the physical address number in the second physical address set ADi corresponding to the memory bank Bi to be tested.

Step S504, judge j equal to 1, if yes, go to step S505, otherwise, go to step S506.

Step S505, randomly selecting a physical address A1 from ADi and recording the selected physical address A1 into a third physical address set corresponding to the first memory cell row in the memory bank to be tested.

Step S506, randomly determining a fifth physical address Aj in ADi, selecting a fourth physical address in each third physical address set that is not an empty set, and performing a continuous access test on the fifth physical address Aj and each fourth physical address respectively.

Step S507, determining whether the access time exceeds a preset time, if not, going to step S508, and if so, going to step S509.

In step S508, the fifth physical address Aj is recorded into the third physical address set corresponding to a new memory cell row.

In step S509, the fifth physical address Aj is recorded in the third physical address set of the memory cell row in which the fourth physical address corresponding to the access time is located.

Step S510, judging whether j is equal to Qi, if so, entering step S511, otherwise, entering step S512, adding 1 to j and returning to step S506.

Step S511, judging whether i is equal to m, if not, going to step S513, adding 1 to i, returning to step S502, if yes, ending step S5.

In the embodiment shown in fig. 8, because each physical address in the second physical address set corresponding to the same memory bank to be tested corresponds to the same memory bank, if the continuous access time of two physical addresses exceeds the preset time duration, it indicates that the two physical addresses are located in different rows, and if the continuous access time of two physical addresses does not exceed the preset time duration, it indicates that the two physical addresses are located in the same row.

Therefore, through the embodiment shown in fig. 8, a physical address set corresponding to each row of each memory bank, that is, a third physical address set, can be obtained, and then a row address mapping function is extracted for each memory bank.

In step S6, a bitwise and operation is performed sequentially using a plurality of second feature functions in the second preset feature function set and each physical address in the third physical address set to determine a row address mapping function corresponding to the third physical address set.

Since some of the bits in the physical address in combination may be indicative of the row address of the DRAM grain, in this step, a second set of predetermined characterization functions may be first determined. The second preset feature function set comprises a plurality of second feature functions, and each second feature function meets the condition of becoming a row address mapping function of the memory to be tested. Firstly, each second characteristic function is an M-bit binary number, and secondly, when the bit width of the row address of the memory to be tested is P, P bits are 1 in the second characteristic functions except for the lowest six bits (the lowest six bits are used as codes of cache line addresses). According to the JEDEC specification, one specification of memory particles has a fixed number of rows, such as an 8Gb XB specification DDR4 DRAM particle, which has a number of rows of 65536 (216), thus occupying a width of 16 bits in the physical address to indicate the particle row address, P =16.

Next, each second characteristic function and the physical address in the third physical address set corresponding to a row of memory cells in one memory bank may be used to perform a calculation to determine whether the second characteristic function is a row mapping function corresponding to the third physical address set.

The row mapping function corresponding to the third set of physical addresses has the same effect on the physical addresses in the third set of physical addresses, and thus, in one embodiment, a second characteristic function may be bitwise anded with each physical address in a third set of physical addresses, determining the second characteristic function as a row address mapping function corresponding to the third physical address set when the second characteristic function is the same as the operation result of each physical address in the third physical address set; and when any one operation result is different from other operation results, another second characteristic function is determined again for operation.

According to the above process, the array mapping function and the row mapping function corresponding to each memory bank and each memory bank row can be determined, and further the physical address and the memory address are matched.

In step S7, a memory address corresponding to the access event is determined according to the array mapping function and the row address mapping function.

The access time includes a read event and a write event, and each memory access event executed by the processor corresponds to one or more physical addresses.

In one embodiment, a physical address corresponding to an access event may be determined first, and then a target array address corresponding to the physical address may be determined according to the physical address and an array mapping function, where the determination is performed by performing a bitwise and operation; and then, determining a target row address in the target array address corresponding to the physical address according to the physical address and the row address mapping function, wherein the determination method is the same as that of bitwise AND operation. And finally, setting the target array address and the target row address as the memory address corresponding to the access event.

By the method provided by the embodiment of the disclosure, the memory address corresponding to each physical address, that is, which memory bank and which row of memory cells are currently accessed, can be quickly determined, and then when an access fault occurs, the faulty memory cell is quickly located. Meanwhile, in memory production tests such as a row hammer test and the like, the method provided by the embodiment of the disclosure can also greatly improve the test efficiency.

In an exemplary embodiment of the present disclosure, there is also provided an electronic device capable of implementing the above method, the electronic device including: a memory to be tested; and a processor coupled to the memory under test, the processor configured to perform the memory address determination method of any one of the above based on instructions stored in the memory to determine an array mapping function and a row address mapping function between physical addresses of the processor and memory cells of the memory under test.

Through the above description of the embodiments, those skilled in the art will readily understand that the exemplary embodiments described herein may be implemented by software, and may also be implemented by software in combination with necessary hardware. Therefore, the technical solution according to the embodiments of the present disclosure may be embodied in the form of a software product, which may be stored in a non-volatile storage medium (which may be a CD-ROM, a usb disk, a removable hard disk, etc.) or on a network, and includes several instructions to enable a computing device (which may be a personal computer, a server, a terminal device, or a network device, etc.) to execute the method according to the embodiments of the present disclosure.

In an exemplary embodiment of the present disclosure, there is also provided a computer-readable storage medium having stored thereon a program product capable of implementing the above-described method of the present specification. In some possible embodiments, the various aspects of the invention may also be implemented in the form of a program product comprising program code means for causing a terminal device to carry out the steps according to various exemplary embodiments of the invention described in the above section "exemplary method" of this description, when said program product is run on said terminal device.

Furthermore, the above-described drawings are only schematic illustrations of processes involved in methods according to exemplary embodiments of the invention, and are not intended to be limiting. It will be readily understood that the processes shown in the above figures are not intended to indicate or limit the chronological order of the processes. In addition, it is also readily understood that these processes may be performed synchronously or asynchronously, e.g., in multiple modules.

Other embodiments of the disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the disclosure disclosed herein. This application is intended to cover any variations, uses, or adaptations of the disclosure following, in general, the principles of the disclosure and including such departures from the present disclosure as come within known or customary practice within the art to which the disclosure pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the disclosure being indicated by the following claims.

Claims

1. A memory address determination method, comprising:

determining a first physical address set corresponding to each memory bank of a memory to be tested according to whether the access time for continuously accessing two physical addresses exceeds a preset time length, wherein the first physical address set comprises a plurality of physical addresses belonging to the same memory bank;

sequentially using a plurality of first feature functions in a first preset feature function set and a plurality of physical addresses in each first physical address set to carry out bitwise AND operation so as to determine a mapping function set corresponding to the memory to be tested;

determining an array mapping function corresponding to the memory to be tested according to the mapping function set;

determining a second physical address set corresponding to each memory bank according to the array mapping function, wherein the second physical address set comprises a plurality of physical addresses belonging to the same memory bank;

determining a third physical address set corresponding to each memory bank row in a second physical address set corresponding to each memory bank according to whether the access time for continuously accessing the two physical addresses exceeds the preset time length, wherein the third physical address set comprises a plurality of physical addresses belonging to the same memory cell row;

performing bitwise AND operation by sequentially using a plurality of second feature functions in a second preset feature function set and each physical address in the third physical address set, determining a row address mapping function corresponding to the third physical address set;

and determining a memory address corresponding to an access event according to the array mapping function and the row address mapping function.

2. The method for determining the memory address according to claim 1, wherein the determining the first set of physical addresses corresponding to each bank of the memory to be tested according to whether the access time for accessing two physical addresses continuously exceeds a preset time period comprises:

randomly determining a first physical address, and recording the first physical address into a first physical address set corresponding to a first memory bank;

randomly determining a second physical address, and carrying out continuous access test on the first physical address and the second physical address;

and when the access time of the continuous access test exceeds a preset time length, recording the second physical address into a first physical address set corresponding to the first memory bank, and when the access time does not exceed the preset time length, recording the second physical address into a first physical address set corresponding to the second memory bank.

3. The method as claimed in claim 2, wherein the determining the first physical address set corresponding to each bank of the memory to be tested according to whether the access time for accessing two physical addresses continuously exceeds a preset time period further comprises:

when a first physical address set corresponding to a plurality of memory banks is not an empty set, randomly determining a third physical address, and respectively performing the continuous access test on the third physical address and one physical address in each first physical address set;

when the access time of any one continuous access test exceeds the preset time length, the third physical address is counted into a first physical address set corresponding to another physical address in the continuous access test;

when the access time of all the continuous access tests does not exceed the preset time length, the third physical address is counted into a first physical address set corresponding to a new memory bank;

4. The method for determining the address of the memory according to claim 3, wherein the step of counting the third physical address into the first physical address set corresponding to another physical address in the test of the consecutive access when the access time of any one of the consecutive accesses exceeds the preset time comprises:

and when the number of the physical addresses in the first physical address set corresponding to the other physical address does not reach a first preset value, the third physical address is counted in the first physical address set corresponding to the other physical address, otherwise, the third physical address is discarded.

5. The method for determining a memory address according to claim 3, wherein the step of counting the third physical address into the first physical address set corresponding to a new memory bank when the access time of all the consecutive accesses does not exceed the preset time comprises:

when all the access time of the continuous access does not exceed the preset time length, selecting the physical address continuously accessed with the third physical address in each first physical address set again, and performing continuous access test again;

when the second time of judging that all the access time of the continuous access does not exceed the preset time length, judging whether the number of the memory banks of which the first physical address set is not empty is equal to the number of all the memory banks corresponding to the memory to be tested;

if so, selecting the physical address which is continuously accessed with the third physical address in each first physical address set again, and performing continuous access test again;

and if not, the third physical address is added into the first physical address set corresponding to a new memory bank.

6. The method as claimed in claim 1, wherein the performing a bitwise and operation using a plurality of first feature functions in a first preset feature function set and a plurality of physical addresses in each of the first physical address sets in sequence to determine the mapping function set corresponding to the memory under test comprises:

performing bitwise AND operation on one first characteristic function and one physical address, determining the number of bits equal to 1 in a calculation result, recording the first characteristic function and the physical address as a first type of mapping when the number of bits is an odd number, and recording the first characteristic function and the physical address as a second type of mapping when the number of bits is an even number;

when each physical address in one of the first characteristic function and one of the first physical address set is the first type of mapping or the second type of mapping, determining that the first characteristic function and the first physical address set have mapping consistency;

and when the mapping consistency exists between one first characteristic function and the first physical address set corresponding to each memory bank, recording the first characteristic function into the mapping function set corresponding to the memory to be tested.

7. The method as claimed in claim 1 or 6, wherein the physical address and the first feature function are both M-bit binary numbers, any two first feature functions are completely different, and performing a bitwise and operation using a plurality of first feature functions in a first preset feature function set and a plurality of physical addresses in each first physical address set in sequence to determine the mapping function set corresponding to the memory to be tested includes:

determining a plurality of feature function sets in the first preset feature function set, wherein the first feature functions in the same feature function set have the same digits equal to 1, and the first feature functions in different feature function sets have different digits equal to 1;

setting a feature function group with the least digits equal to 1 as a feature function group to be tested in a feature function group which is not tested currently;

determining a first characteristic function to be tested in the characteristic function group to be tested, performing bitwise AND operation on the first characteristic function to be tested and a plurality of physical addresses in each first physical address set, and determining another first characteristic function to be tested in the characteristic function group to be tested again until all first characteristic functions corresponding to the characteristic function group to be tested are operated;

and re-determining the feature function groups to be detected until each feature function group finishes operation.

8. The method for determining the memory address according to claim 1, wherein the determining the array mapping function corresponding to the memory to be tested according to the mapping function set comprises:

and operating the mapping function set by using a Gaussian elimination method to obtain the array mapping function, wherein the array mapping function comprises a plurality of linearly independent first characteristic functions.

9. The memory address determination method of claim 1, wherein the array mapping function includes X first characterization functions, 2 ^X M, where m is the number of memory banks in the memory to be tested, and the determining, according to the array mapping function, the second physical address set corresponding to each memory bank includes:

randomly determining a plurality of target physical addresses;

carrying out bitwise AND operation on the ith first characteristic function in the array mapping function and the target physical address, recording the ith bit of the array address of the target physical address as 1 when the number of bits of 1 in the operation result is an odd number, and recording the ith bit of the array address of the target physical address as 0 when the number of bits of 1 in the operation result is an even number, wherein i is more than or equal to 1 and is less than or equal to X;

performing bitwise AND operation on each first characteristic function in the array mapping function and the target physical address to determine an array address of the target physical address;

determining array addresses corresponding to the target physical addresses, and recording the target physical addresses with the same array addresses as the second physical address set corresponding to one memory bank.

10. The method for determining the memory address according to claim 1, wherein the determining, in the second physical address set corresponding to each of the memory banks, a third physical address set corresponding to each of the memory bank rows according to whether the access time for accessing two physical addresses consecutively exceeds a preset time period comprises:

randomly selecting a fourth physical address in the second physical address set corresponding to the memory bank to be tested, and recording the fourth physical address into the third physical address set corresponding to the first memory cell row in the memory bank to be tested;

randomly determining a fifth physical address in the second physical address set corresponding to the memory bank to be tested, and performing continuous access test on the fourth physical address and the fifth physical address;

when the access time does not exceed the preset time length, recording the fifth physical address into a third physical address set corresponding to the first storage unit row;

when the access time of the continuous access test exceeds a preset time length, recording the fifth physical address into a third physical address set corresponding to a second memory cell row;

and performing the continuous access test on each physical address in the second physical address set corresponding to the memory bank to be tested to determine a third physical address set corresponding to each memory cell row in the memory bank.

11. The memory address determination method of claim 1, wherein the performing a bit and operation using a plurality of second feature functions in a second set of predetermined feature functions in sequence with each physical address in the third set of physical addresses to determine the row address mapping function corresponding to the third set of physical addresses comprises:

performing bitwise AND operation on one second characteristic function and each physical address in one third physical address set to obtain a plurality of operation results;

when the operation results of the second characteristic function and each physical address in the third physical address set are the same, determining that the second characteristic function is a row address mapping function corresponding to the third physical address set;

and when any one of the operation results is different from other operation results, another second characteristic function is determined again for operation.

12. The method according to claim 1 or 11, wherein the physical address and the second characteristic function are both M-bit binary numbers, the bit width of the row address of the memory to be tested is P, and P bits in the second characteristic function except the lowest six bits are 1.

13. The memory address determination method of claim 1, further comprising:

randomly determining a plurality of groups of physical addresses, wherein each group of physical addresses comprises two different physical addresses;

performing multiple continuous access tests on each group of physical addresses, and recording the median or average value of the access time of the multiple continuous access tests as the continuous access duration corresponding to each group of physical addresses;

obtaining the statistical distribution of a plurality of continuous access durations corresponding to the plurality of groups of physical addresses;

and determining the preset duration according to the statistical distribution.

14. The memory address determination method of claim 13, wherein the performing a plurality of consecutive access tests on each group of the physical addresses comprises:

after each of the sequential access tests, a cache line flush instruction is executed.

15. The memory address determination method of claim 1, wherein determining the memory address corresponding to the access event according to the array mapping function and the row address mapping function comprises:

determining a physical address corresponding to the access event;

determining a target array address corresponding to the physical address according to the physical address and the array mapping function;

determining a target row address in the target array address corresponding to the physical address according to the physical address and the row address mapping function;

and setting the target array address and the target row address as a memory address corresponding to the access event.

16. An electronic device, comprising:

a memory to be tested; and

a processor coupled to the memory under test, the processor configured to perform the memory address determination method of any of claims 1-15 based on instructions stored in the memory to determine an array mapping function and a row address mapping function between physical addresses of the processor and memory cells of the memory under test.