CN115148238A

CN115148238A - Sense amplifier and semiconductor memory

Info

Publication number: CN115148238A
Application number: CN202210760106.6A
Authority: CN
Inventors: 苏信政; 李中和
Original assignee: Changxin Memory Technologies Inc
Current assignee: Changxin Memory Technologies Inc
Priority date: 2022-06-30
Filing date: 2022-06-30
Publication date: 2022-10-04
Also published as: WO2024000640A1

Abstract

The present disclosure provides a sense amplifier and a semiconductor memory including: the control module is provided with an input end and an output end and is used for acquiring the temperature data of the amplification module, carrying out pulse width adjustment on the first offset cancellation signal received by the input end of the control module according to the temperature data of the amplification module, and generating and outputting a second offset cancellation signal; and the control end of the amplifying module is connected with the output end of the control module and is used for eliminating the noise signal of the amplifying module under the control of the second offset eliminating signal. Through the arrangement, the condition that the transistor in the compensation amplification module changes along with the temperature change is realized, the compensation voltage with proper magnitude is generated on the bit line and the complementary bit line, the noise signal in the amplification module is accurately eliminated, and the accuracy of the sensitive amplifier is improved.

Description

Sense amplifier and semiconductor memory

Technical Field

The present disclosure relates to, but is not limited to, a sense amplifier and a semiconductor memory.

Background

With the shrinking line width of the semiconductor memory, the capacitance of the memory cell in the semiconductor memory decreases, so that the noise has a greater influence on the normal operation of the semiconductor memory.

The sense amplifier can eliminate noise caused by manufacturing variations of transistors in the semiconductor memory, so that the semiconductor memory can accurately store data. When the sense amplifier operates in the offset cancellation stage, compensation voltages are formed on the sense bit lines and the complementary sense bit lines, and the noise cancellation effect is affected by the magnitude of the compensation voltages.

Therefore, how to generate a properly sized compensation voltage on the bit line and complementary bit line is critical to semi-eliminating noise in the semiconductor memory.

Disclosure of Invention

The present disclosure provides a sense amplifier comprising:

the control module is provided with an input end and an output end and is used for acquiring the temperature data of the amplification module, carrying out pulse width adjustment on the first offset cancellation signal received by the input end of the control module according to the temperature data of the amplification module, and generating and outputting a second offset cancellation signal;

and the control end of the amplifying module is connected with the output end of the control module and is used for eliminating the noise signal of the amplifying module under the control of the second offset eliminating signal.

In some embodiments, the control module comprises:

the pulse width parameter unit is provided with an output end and is used for generating a pulse width adjusting signal according to the temperature data of the amplifying module;

and the regulating unit is provided with an input end, an output end and a control end, the control end of the regulating unit is connected with the output end of the pulse width parameter unit, the input end of the regulating unit receives the first offset eliminating signal, carries out pulse width regulating processing on the first offset eliminating signal according to the pulse width regulating signal and outputs a second offset eliminating signal.

In some embodiments, the pulse width parameter unit includes three outputs, the pulse width adjustment signal includes three strobe signals, and the adjustment unit includes:

the output end of the first adjusting subunit is connected with the first input end of the selecting unit and is used for performing pulse width adjustment on the first offset eliminating signal and outputting a third offset eliminating signal;

a second regulator subunit, the output end of which is connected with the second input end of the selection unit, the fourth offset cancellation signal is output by performing pulse width adjustment on the first offset cancellation signal;

the output end of the third adjusting subunit is connected with the third input end of the selecting unit and is used for performing pulse width adjustment on the first offset eliminating signal and outputting a fifth offset eliminating signal; wherein a pulse width of the third offset cancellation signal, a pulse width of the fourth offset cancellation signal, and a pulse width of the fifth offset cancellation signal are different;

the selection unit is provided with three control ends, and each control end is connected with the corresponding output end of the pulse width parameter unit and receives the corresponding gating signal; the signal processing unit is used for selecting one of the third offset cancellation signal, the fourth offset cancellation signal and the fifth offset cancellation signal to be output under the control of three gating signals, and the output signal of the selection unit is used for controlling and eliminating the noise signal of the amplification module.

In some embodiments, the adjusting unit further comprises:

and the input end of the phase inverter is connected with the output end of the selection unit, and the output signal of the phase inverter is used for controlling and eliminating the noise signal of the amplification module.

In some embodiments, the first regulating subunit comprises:

a first delay circuit, the input end of which receives the first offset cancellation signal, and is used for delaying the first offset cancellation signal and outputting a first delay signal;

and the first input end of the first AND gate receives the first offset cancellation signal, the second input end of the first AND gate is connected with the output end of the first delay circuit, receives the first delay signal, and the output end of the first AND gate outputs a third offset cancellation signal.

In some embodiments, the first delay circuit comprises:

a first access line, one end of which is used as the output end of the first delay circuit, and the other end of which receives the first offset cancellation signal;

the grid electrode of the first P-type transistor is connected with the first access line, and the drain electrode of the first P-type transistor is connected with the source electrode of the first P-type transistor and then connected with a first power supply end;

and the grid electrode of the first N-type transistor is connected with the first access line, and the drain electrode of the first N-type transistor is connected with the source electrode of the first N-type transistor and then connected with the second power supply end.

In some embodiments, the second regulating subunit comprises:

a second delay circuit, the input end of which receives the first offset cancellation signal and is used for delaying the first offset cancellation signal and outputting a second delay signal; the delay amount of the second delay circuit for delay processing is larger than that of the first delay circuit for delay processing;

and a second and gate, a first input terminal of which receives the first offset canceling signal, a second input terminal of which is connected to the output terminal of the second delay circuit, receives the second delay signal, and an output terminal of which outputs a fourth offset canceling signal.

In some embodiments, the second delay circuit comprises:

a second access line, one end of which is used as the output end of the second delay circuit, and the other end of which receives the first offset cancellation signal;

the grid electrode of the second P-type transistor is connected with the second access line, and the drain electrode of the second P-type transistor is connected with the source electrode of the second P-type transistor and then connected with the first power supply end;

the grid electrode of the second N-type transistor is connected with the second access line, and the drain electrode of the second N-type transistor is connected with the source electrode of the second N-type transistor and then connected with a second power supply end;

the grid electrode of the third P-type transistor is connected with the second access line, and the drain electrode of the third P-type transistor is connected with the first power supply end after being connected with the source electrode of the third P-type transistor;

and the grid electrode of the third N-type transistor is connected with the second access line, and the drain electrode of the third N-type transistor is connected with the second power supply end after being connected with the source electrode of the third N-type transistor.

In some embodiments, the third regulating subunit comprises:

a third delay circuit, the input end of which receives the first offset cancellation signal, and is used for delaying the first offset cancellation signal and outputting a third delay signal; the delay amount of the delay processing performed by the third delay circuit is larger than that of the delay processing performed by the second delay circuit;

and a third and gate having a first input terminal receiving the first offset canceling signal, a second input terminal connected to the output terminal of the third delay circuit, receiving the third delay signal, and an output terminal outputting a fifth offset canceling signal.

In some embodiments, the third delay circuit comprises:

a third access line, one end of which is used as the output end of the third delay circuit, and the other end of which receives the first offset cancellation signal;

a fourth P-type transistor, the grid of which is connected with the third access line, and the drain of which is connected with the source and then connected with the first power supply end;

a grid electrode of the fourth N-type transistor is connected with the third access line, and a drain electrode of the fourth N-type transistor is connected with the second power supply end after being connected with a source electrode of the fourth N-type transistor;

a fifth P-type transistor, a gate of which is connected to the third access line, and a drain of which is connected to the source of the fifth P-type transistor and then connected to the first power terminal;

a fifth N-type transistor, the grid of which is connected with the third access line, and the drain of which is connected with the source and then connected with the second power supply end;

a sixth P-type transistor, a gate of which is connected to the third access line, and a drain of which is connected to the source and then to the first power supply terminal;

and the grid electrode of the sixth N-type transistor is connected with the third access line, and the drain electrode of the sixth N-type transistor is connected with the second power supply end after being connected with the source electrode of the sixth N-type transistor.

In some embodiments, the pulse width parameter unit comprises:

the temperature sensor is used for detecting the temperature data of the amplifying module and generating temperature coding data according to the temperature data;

and the input end of the temperature decoder is connected with the output end of the temperature sensor, and the temperature decoder is used for generating a pulse width adjusting signal according to the temperature encoding data.

In some embodiments, the pulse width parameter unit is to:

when the temperature data is in a first temperature range, the output first gating signal is an effective value, and the output second gating signal and the output third gating signal are invalid values; control the selection unit to select outputting a three-offset cancellation signal;

when the temperature data is in the second temperature range, the output second strobe signal is a valid value, the output first strobe signal and the third strobe signal are invalid values; the control selection unit selects the fourth offset cancellation signal to output;

when the temperature data is in a third temperature range, the output third gating signal is an effective value, and the output first gating signal and the output second gating signal are invalid values; the control selection unit selects the fifth offset cancellation signal to output;

the upper limit value of the first temperature range is less than or equal to the lower limit value of a second temperature range, and the upper limit value of the second temperature range is less than or equal to the lower limit value of a third temperature range; the pulse width of the third offset canceling signal is smaller than the pulse width of the fourth offset canceling signal, and the pulse width of the fourth offset canceling signal is smaller than the pulse width of the fifth offset canceling signal.

In some embodiments, the amplification module comprises:

a seventh P-type transistor having a source connected to the source of the eighth P-type transistor and a gate connected to the drain of the eighth P-type transistor;

an eighth P-type transistor having a first transistor, the grid electrode of the second P-type transistor is connected with the drain electrode of the seventh P-type transistor;

a seventh N-type transistor having a drain connected to the drain of the seventh P-type transistor, a source connected to the source of the eighth N-type transistor, and a gate connected to the bit line;

an eighth N-type transistor having a drain connected to the drain of the eighth P-type transistor and a gate connected to the complementary bit line;

a ninth N-type transistor, a first end of which is connected with the bit line, a second end of which is connected with the drain electrode of the seventh N-type transistor, and a grid electrode of which is used as the control end of the amplifying module;

and a tenth N-type transistor, wherein the second end of the tenth N-type transistor is connected with the complementary bit line, the first end of the tenth N-type transistor is connected with the drain electrode of the eighth N-type transistor, and the grid electrode of the tenth N-type transistor is used as the control end of the amplifying module.

In some embodiments, the amplification module comprises:

an eleventh N-type transistor, a first end of which is connected to the bit line, a second end of which is connected to the drain of the eighth N-type transistor, and a gate of which receives the isolation control signal;

and a twelfth N-type transistor having a second end connected to the complementary bit line, a first end connected to the drain of the seventh N-type transistor, and a gate receiving the isolation control signal.

In some embodiments, the amplification module comprises:

a ninth P-type transistor having a source connected to the third power supply terminal and a drain connected to the source of the seventh P-type transistor;

and a thirteenth N-type transistor having a source connected to the fourth power supply terminal and a drain connected to the source of the seventh N-type transistor.

An embodiment of the present disclosure provides a semiconductor memory including the sense amplifier according to the above embodiment.

The utility model provides a sensitive amplifier and semiconductor memory, sensitive amplifier includes control module and amplification module, and control module is used for adjusting the pulse width of first skew elimination signal according to the temperature data of amplification module to the condition that the transistor changes along with the temperature change in the compensation amplification module, makes to produce the compensation voltage of suitable size on bit line and the complementary bit line, and the mismatch error of accurate elimination transistor improves sensitive amplifier's accuracy.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present disclosure and together with the description, serve to explain the principles of the disclosure.

FIG. 1 is a circuit schematic of a sense amplifier;

FIG. 2A is a schematic diagram of the sense amplifier of FIG. 1 during an offset cancellation phase;

FIG. 2B is another schematic diagram of the sense amplifier of FIG. 1 during an offset cancellation phase;

FIG. 2C is a schematic diagram of another operation of the sense amplifier of FIG. 1 during an offset cancellation phase;

FIG. 3 is a circuit diagram of a sense amplifier according to an embodiment of the disclosure;

FIG. 4 is a circuit diagram of a control module according to another embodiment of the present disclosure;

FIG. 5 is a schematic circuit diagram of a first conditioning subunit provided in yet another embodiment of the present disclosure;

FIG. 6 shows a first embodiment of the FIG. 5 the working principle of the regulating subunit is shown schematically;

FIG. 7 is a circuit schematic of a second conditioning subunit provided by yet another embodiment of the present disclosure;

FIG. 8 is a schematic diagram of the operation of the second conditioning subunit of the embodiment of FIG. 7;

FIG. 9 is a circuit schematic of a third conditioning subunit provided by yet another embodiment of the present disclosure;

FIG. 10 is a schematic diagram of the operation of the third conditioning subunit of the embodiment of FIG. 9;

fig. 11 is a timing diagram of a sense amplifier according to an embodiment of the disclosure.

Reference numerals:

200. a control module; 100. an amplifying module; 220. a pulse width parameter unit; 210. an adjustment unit; 211. a first regulator subunit; 212. a second regulator subunit; 213. a third regulator subunit; 214. a selection unit; 215. an inverter; 221. a temperature sensor; 222. a temperature decoder; 311. a first AND gate; 321. a first delay circuit; 331. a first access line; 312. a second AND gate; 322. a second delay circuit; 332. a second access line; 313. a third AND gate; 323. a third delay circuit; 333. and a third access line.

With the foregoing drawings in mind, certain embodiments of the disclosure have been shown and described in more detail below. These drawings and written description are not intended to limit the scope of the disclosed concepts in any way, but rather to illustrate the concepts of the disclosure to those skilled in the art by reference to specific embodiments.

Detailed Description

Reference will now be made in detail to the exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, like numbers in different drawings represent the same or similar elements unless otherwise indicated. The implementations described in the exemplary embodiments below are not intended to represent all implementations consistent with the present disclosure. Rather, they are merely examples of apparatus and methods consistent with certain aspects of the present disclosure, as detailed in the appended claims.

As shown in fig. 1, a sense amplifier includes an amplifying module 100, and the amplifying module 100 includes a seventh P-type transistor P7, an eighth P-type transistor P8, a seventh N-type transistor N7, and an eighth N-type transistor N8.

The source of the seventh P-type transistor P7 is connected to the source of the eighth P-type transistor P8 to serve as the first terminal LA of the amplification module 100, and the source of the seventh N-type transistor N7 is connected to the source of the eighth N-type transistor N8 to serve as the second terminal LAB of the amplification module 100. The gate of the seventh P-type transistor P7 is connected to the drain of the eighth P-type transistor P8, and the gate of the eighth P-type transistor P8 is connected to the drain of the seventh P-type transistor P7. The drain of the seventh P-type transistor P7 is connected to the drain of the seventh N-type transistor N7, and then to the complementary sense bit line SABLB. After the drain of the eighth P-type transistor P8 is connected to the drain of the eighth N-type transistor N8, the gate of the seventh N-type transistor N7 connected to the read bit line SABL is connected to the bit line BL, and the gate of the eighth N-type transistor N8 is connected to the complementary bit line BLB.

The amplification block 100 further includes a ninth N-type transistor N9 and a tenth N-type transistor N10. A first terminal of the ninth N-type transistor N9 is connected to the bit line, and a second terminal of the ninth N-type transistor N9 is connected to the drain of the seventh N-type transistor N7. A second terminal of the tenth N-type transistor N10 is connected to the complementary bit line BLB, and a first terminal of the tenth N-type transistor N10 is connected to the drain of the eighth N-type transistor N8.

The amplification block 100 further includes an eleventh N-type transistor N11 and a twelfth N-type transistor N12. A first end of the eleventh N-type transistor N11 is connected to the bit line BL, and a second end of the eleventh N-type transistor N11 is connected to the drain of the eighth N-type transistor N8. A first terminal of the twelfth N-type transistor N12 is connected to the drain of the seventh N-type transistor N7, and a second terminal of the twelfth N-type transistor N12 is connected to the complementary bit line BLB.

During the offset canceling phase T2, the ninth N-type transistor N9 and the tenth N-type transistor N10 are both turned on, and the seventh N-type transistor N7 and the eighth N-type transistor N8 are both operated in a diode state, generating a compensation voltage Vos on the bit line BL and the complementary bit line BLB, and also generating a compensation voltage Vos on the sense bit line SABL and the complementary sense bit line SABLB.

Since the compensation voltage Vos is already stored on the sensing bit line SABL and the complementary sensing bit line SABLB, the compensation voltage Vos can cancel the noise signal of the amplifying block 100 during the sensing amplifying stage, so that the data can be accurately represented on the bit line BL and the complementary bit line BLB.

In the recovery phase, the eleventh N-type transistor N11 and the twelfth N-type transistor N12 are both turned on, the bit line BL is connected to the sense bit line SABL, and the complementary bit line BLB is connected to the complementary sense bit line SABLB, so that data recovery in the memory cell is achieved.

The magnitude of the compensation voltage Vos affects the noise cancellation effect, and the noise signal of the amplification module 100 cannot be accurately cancelled when the compensation voltage Vos is too large or too small. The magnitude of the compensation voltage Vos is related to the pulse width of the offset cancellation signal. When the pulse width of the offset canceling signal of the amplifying block 100 is larger, a larger compensation voltage Vos may be formed on the sensing bit line SABL and the complementary sensing bit line SABLB. As the pulse width of the offset canceling signal of the amplifying block 100 is smaller, the compensation voltage Vos formed on the sensing bit line SABL and the complementary sensing bit line SABLB is smaller. Therefore, in the design stage of the sense amplifier, it is necessary to design a proper pulse width of the offset cancellation signal to achieve a proper compensation voltage Vos formed on the bit line BL and the complementary bit line BLB.

However, the driving capability of the sense amplifier also varies when the temperature of the sense amplifier varies. As shown in fig. 2A, when the temperature of the sense amplifier is moderate, the voltage driving capability of the sense amplifier is moderate, and the compensation voltage Vos of a proper magnitude can be generated on the bit line BL and the complementary bit line BLB. As shown in fig. 2B, when the temperature of the sense amplifier becomes high, the voltage driving capability of the transistors in the amplification block 100 becomes weak, the offset voltage Vos formed at the offset canceling stage T2 becomes small, and the noise signal of the amplification block 100 cannot be canceled. As shown in fig. 2C, when the temperature of the sense amplifier is relatively low, the voltage driving capability of the transistor in the amplifying module 100 is relatively strong, and the offset voltage Vos formed in the offset canceling stage T2 becomes large, so that new noise is introduced.

In order to more accurately form a compensation voltage Vos of an appropriate magnitude on a sense bit line SABL and a complementary sense bit line SABLB, the present disclosure provides a sense amplifier and a semiconductor memory including an amplification block 100 and a control block 200, the control block 200 adjusting a pulse width of an offset canceling signal based on temperature data of the amplification block 100 to compensate for a variation in voltage driving capability of transistors within the amplification block 100, achieving generation of the compensation voltage Vos of an appropriate magnitude on the bit line BL and the complementary bit line BLB, accurately canceling a noise signal of the amplification block 100, and improving accuracy of the sense amplifier.

As shown in fig. 3, an embodiment of the present disclosure provides a sense amplifier, which includes a control module 200 and an amplification module 100, where the amplification module 100 has a control terminal, and the control module 200 has an input terminal and an output terminal. The control terminal of the amplification module 100 is connected to the output terminal of the control module 200.

The input end of the control module 200 receives the first offset cancellation signal OC1, and the control module 200 is configured to obtain temperature data of the amplifying module 100, perform pulse width modulation on the first offset cancellation signal OC1 according to the temperature data of the amplifying module 100 to generate a second offset cancellation signal OC2, and output the second offset cancellation signal OC2 from the output end thereof. The amplifying module 100 is used for canceling the noise signal of the amplifying module 100 under the control of the second offset canceling signal OC2.

When the temperature data of the amplifying module 100 becomes larger, the pulse width of the second offset cancellation signal OC2 outputted by the control module 200 is larger to compensate the situation that the voltage driving capability of the amplifying module 100 becomes weaker with the temperature rise thereof, so as to generate the compensation voltage Vos with proper magnitude on the bit line BL and the complementary bit line BLB.

When the temperature data of the amplifying module 100 becomes smaller, the pulse width of the second offset canceling signal OC2 outputted by the control module 200 is smaller to compensate for the situation that the voltage driving capability of the amplifying module 100 becomes stronger as the temperature thereof decreases, so as to generate the compensating voltage Vos of a proper magnitude on the bit line BL and the complementary bit line BLB.

In the above technical solution, the sense amplifier includes a control module 200 and an amplification module 100, where the control module 200 is configured to adjust a pulse width of the first offset cancellation signal OC1 according to temperature data of the amplification module 100 to compensate a situation that a voltage driving capability of the amplification module 100 changes with a temperature change, so that a compensation voltage Vos with a proper magnitude is generated on the bit line BL and the complementary bit line BLB, a noise signal of the amplification module 100 is accurately cancelled, and accuracy of the sense amplifier is improved.

In some embodiments, as shown in fig. 4, the control module 200 includes a pulse width parameter unit 220 and an adjusting unit 210, the pulse width parameter unit 220 has an output terminal, the adjusting unit 210 has an input terminal, an output terminal and a control terminal, and the output terminal of the pulse width parameter unit 220 is connected to the control terminal of the adjusting unit 210. The pulse width parameter unit 220 is used for generating a pulse width adjusting signal according to the temperature data of the amplifying module 100. The input terminal of the adjusting unit 210 receives the first offset cancellation signal OC1, and the adjusting unit 210 performs a pulse width adjustment process on the first offset cancellation signal OC1 according to the pulse width adjustment signal to output a second offset cancellation signal OC2.

In some embodiments, the pulse width parameter unit 220 compares the temperature data of the amplifying module 100 with each temperature gear range to obtain gear information, and generates a pulse width adjusting signal according to the gear information. When the gear information corresponding to the temperature data is different, the pulse width adjusting signals are different.

In the above technical solution, the control module 200 is provided with a pulse width parameter unit 220 and an adjusting unit 210, the pulse width parameter unit 220 generates a pulse width adjusting signal according to the temperature data of the amplifying module 100, so that the adjusting unit 210 performs pulse width adjustment on the first offset cancellation signal OC1 under the control of the pulse width adjusting signal, and the adjustment of the pulse width of the first offset cancellation signal OC1 based on the temperature data of the amplifying module 100 is realized.

In some embodiments, as shown in fig. 4, the pulse width parameter unit 220 includes a temperature sensor 221 and a temperature decoder 222, the temperature sensor 221 having an output, and the temperature decoder 222 having an input and an output. The output of the temperature sensor 221 is connected to the input of the temperature decoder 222. The temperature sensor 221 is configured to detect temperature data of the amplifying module 100 and generate temperature-encoded data according to the temperature data. The temperature decoder 222 is configured to generate a pulse width adjustment signal based on the temperature encoded data.

In some embodiments, the temperature decoder 222 is configured to decode the temperature-coded data, compare the decoded result with each temperature range to obtain gear information, and generate a pulse width adjustment signal according to the gear information.

In some embodiments, as shown in fig. 4, the pulse width parameter unit 220 includes three outputs, the pulse width adjustment signal includes three strobe signals, and each output of the pulse width parameter unit 220 outputs one strobe signal. The adjusting unit 210 includes a first adjusting subunit 211, a second adjusting subunit 212, a third adjusting subunit 213, and a selecting unit 214. The first, second and

third regulating subunits

211, 212, 213 are provided with input and output terminals. The selection unit 214 has three inputs, which are sequentially labeled as a first input, a second input, and a third input. The selection unit 214 is also provided with three control terminals.

The input terminal of the first adjusting subunit 211 receives the first offset cancellation signal OC1, the output terminal of the first adjusting subunit 211 is connected to the first input terminal of the selecting unit 214, and the first adjusting subunit 211 is configured to perform pulse width adjustment on the first offset cancellation signal OC1 to output a third offset cancellation signal OC3. An input terminal of the second adjusting subunit 212 receives the first offset cancellation signal OC1, an output terminal of the second adjusting subunit 212 is connected to a second input terminal of the selecting unit 214, and the second adjusting subunit 212 is configured to perform pulse width adjustment on the first offset cancellation signal OC1 and output a fourth offset cancellation signal OC4. An input terminal of the third adjusting subunit 213 receives the first offset cancellation signal OC1, an output terminal of the third adjusting subunit 213 is connected to a third input terminal of the selecting unit 214, and the third adjusting subunit 213 is configured to perform pulse width adjustment on the first offset cancellation signal OC1 and output a fifth offset cancellation signal OC5.

The first, second and

third adjusting subunits

211, 212 and 213 have different pulse width adjustment amounts, and the pulse width of the fifth offset cancellation signal OC5, the pulse width of the fourth offset cancellation signal OC4 and the pulse width of the third offset cancellation signal OC3 are different.

Each control terminal of the selection unit 214 is connected to the output terminal of the corresponding pulse width parameter unit 220, such that each control terminal of the selection unit 214 receives the corresponding gate signal, the selection unit 214 is configured to select one of the third offset cancellation signal OC3, the fourth offset cancellation signal OC4, and the fifth offset cancellation signal OC5 for output under the control of three gate signals, and the output signal of the selection unit 214 is configured to control and cancel the noise signal of the amplification module 100.

In some embodiments, the output terminal of the selection unit 214 is connected to the control terminal of the amplification module 100, and the amplification module 100 eliminates the internal noise signal under the control of the output signal of the selection unit 214.

The three strobe signals output by the pulse width parameter unit 220 are labeled as a first strobe signal, a second strobe signal, and a third strobe signal. The first gate signal is used to control whether the selection unit 214 selects the output of the third offset cancellation signal OC3 output by the first adjustment sub-unit 211, the second gate signal is used to control whether the selection unit 214 selects the output of the fourth offset cancellation signal OC4 output by the second adjustment sub-unit 212, and the third gate signal is used to control whether the selection unit 214 selects the output of the fifth offset cancellation signal OC5 output by the third adjustment sub-unit 213.

In some embodiments, the upper value of the first temperature range is less than or equal to the lower value of the second temperature range, and the upper value of the second temperature range is less than or equal to the lower value of the third temperature range. For example: the first temperature range is that T is less than or equal to 20 ℃, the second temperature range is that T is more than 20 ℃ and less than or equal to 60 ℃, and the third temperature range is that T is more than 60 ℃.

In some embodiments, the pulse width of the third offset cancellation signal OC3 is smaller than the pulse width of the fourth offset cancellation signal OC4, and the pulse width of the fourth offset cancellation signal OC4 is smaller than the pulse width of the fifth offset cancellation signal OC5.

When the temperature data is in the first temperature range, the first strobe signal output by the pulse width parameter unit 220 is an effective value, and the second strobe signal and the third strobe signal output by the pulse width parameter unit 220 are invalid values, so as to control the selection unit 214 to select the third offset cancellation signal OC3 for output.

When the temperature data is in the second temperature range, the second gating signal output by the pulse width parameter unit 220 is an effective value, and the first gating signal and the third gating signal output by the pulse width parameter unit 220 are invalid values, so that the control selection unit 214 selects the fourth offset cancellation signal OC4 to output.

When the temperature data is in the third temperature range, the third strobe signal output by the pulse width parameter unit 220 is an effective value, the first strobe signal and the second strobe signal output by the pulse width parameter unit 220 are invalid values, and the selection unit 214 is controlled to select the fifth offset cancellation signal OC5 for output.

In the above technical solution, the adjusting unit 210 includes a selecting unit 214 and three adjusting subunits, each of which is used for performing a pulse width adjusting process on the first offset cancellation signal OC1, and the pulse adjusting amounts of the three adjusting subunits are different, the selecting unit 214 selects from output signals of the three adjusting subunits according to three strobe signals, and the selected strobe signal is generated by the temperature decoder 222 according to the temperature data of the amplifying module 100, so as to adjust the pulse width of the first offset cancellation signal OC1 based on the temperature data of the amplifying module 100.

In some embodiments, as shown in fig. 5, the first adjusting subunit 211 comprises a first delay circuit 321 and a first and gate 311, the first delay circuit 321 having an input and an output. The second input terminal In2 of the first and gate 311 is connected to the output terminal of the first delay circuit 321, the input terminal of the first delay circuit 321 receives the first offset cancellation signal OC1, and the first delay circuit 321 delays the first offset cancellation signal OC1 to output a first delay signal. The first input terminal In1 of the first and gate 311 receives the first offset cancellation signal OC1, the second input terminal In2 of the first and gate 311 receives the first delayed signal, and the first and gate 311 performs and operation on the first offset cancellation signal OC1 and the first delayed signal and outputs a third offset cancellation signal OC3 through an output terminal Out1 thereof.

In some embodiments, the first delay circuit 321 includes a first access line 331, a first P-type transistor P1, and a first N-type transistor N1. One end of the first access line 331 is connected to the second input terminal In2 of the first and gate 311, the other end of the first access line 331 receives the first offset cancellation signal OC1, and the first access line 331 transmits the first offset cancellation signal OC1 to the second input terminal In2 of the first and gate 311.

The gate of the first P-type transistor P1 is connected to the first access line 331, and the drain of the first P-type transistor P1 is connected to the source of the first P-type transistor P1 and then connected to the first power terminal V1. The gate of the first N-type transistor N1 is connected to the first access line 331, and the drain of the first N-type transistor N1 is connected to the source of the first N-type transistor N1 and then connected to the second power terminal V2. The voltage of the first power source terminal V1 is greater than the voltage of the second power source terminal V2, and the second power source terminal V2 is usually a ground terminal. With this arrangement, the first P-type transistor P1 and the first N-type transistor N1 are connected as capacitors to the second input terminal In2 of the first and gate 311, so as to achieve the delay processing of the first offset cancellation signal OC1 transmitted from the first access line 331, and enable the second input terminal In2 of the first and gate 311 to receive the first delay signal. That is, if the first offset canceling signal OC1 is a low-level pulse signal, the first delayed signal is also a low-level pulse signal, and the falling edge timing of the first delayed signal is later than the falling edge timing of the first offset canceling signal OC 1. If the first offset cancellation signal OC1 is a high level pulse signal, the first delayed signal is also a high level pulse signal, and the rising edge time of the first delayed signal is later than the rising edge time of the first offset cancellation signal OC 1.

As shown In fig. 6, if the first offset cancellation signal OC1 is a low-level pulse signal, the first input terminal In1 of the first and gate 311 receives the first offset cancellation signal OC1, and the second input terminal In2 of the first and gate 311 receives the first delayed signal, and the falling time of the first delayed signal is later than the falling time of the first offset cancellation signal OC 1. The first and gate 311 performs and operation on the first offset cancellation signal OC1 and the first delayed signal, and outputs a third offset cancellation signal OC3 through an output end Out1 thereof, where the third offset cancellation signal OC3 is still a low-level pulse signal, the pulse width of the third offset cancellation signal OC3 is increased, and the increase is the time difference Δ τ 1 between the falling edges of the first delayed signal and the first offset cancellation signal OC 1.

In some embodiments, the second adjusting subunit 212 includes a second delay circuit 322 and a second and gate 312, the second delay circuit 322 includes an input terminal and an output terminal, and the output terminal of the second delay circuit 322 is connected to a second input terminal In4 of the second and gate 312. The input terminal of the second delay circuit 322 receives the first offset cancellation signal OC1, and the second delay circuit 322 delays the first offset cancellation signal OC1 to output a second delayed signal. And the delay amount of the delay processing performed by the second delay circuit 322 is greater than the delay amount of the delay processing performed by the first delay circuit 321, that is, when the first offset cancellation signal OC1 is a low-level pulse signal, the time difference Δ τ 2 between the falling edge time of the second delay signal and the falling edge time of the second offset cancellation signal OC2 is greater than the time difference Δ τ 1 between the falling edge time of the first delay signal and the falling edge time of the first offset cancellation signal OC 1.

A first input terminal In3 of the second and gate 312 receives the first offset cancellation signal OC1, a second input terminal In4 of the second and gate 312 receives the second delayed signal, and the second and gate 312 outputs a fourth offset cancellation signal OC4 through an output terminal Out2 thereof after performing and operation on the first offset cancellation signal OC1 and the second delayed signal.

In some embodiments, as shown in fig. 7, the second delay circuit 322 includes a second access line 332, a second P-type transistor P2, a second N-type transistor N2, a third P-type transistor P3, and a third N-type transistor N3. One end of the second access line 332 is connected to the second input terminal In4 of the second and gate 312, the other end of the second access line 332 receives the first offset cancellation signal OC1, and the second access line 332 transmits the first offset cancellation signal OC1 to the second input terminal In4 of the second and gate 312.

The gate of the second P-type transistor P2 is connected to the second access line 332, and the drain of the second P-type transistor P2 is connected to the source of the second P-type transistor P2 and then connected to the first power terminal V1. The gate of the second N-type transistor N2 is connected to the second access line 332, and the drain of the second N-type transistor N2 is connected to the source of the second N-type transistor N2 and then connected to the second power terminal V2. The gate of the third P-type transistor P3 is connected to the second access line 332, and the drain of the third P-type transistor P3 is connected to the source of the third P-type transistor P3 and then connected to the first power terminal V1. The gate of the third N-type transistor N3 is connected to the second access line 332, and the drain of the third N-type transistor N3 is connected to the source of the third N-type transistor N3 and then connected to the second power terminal V2.

With such a configuration, the second P-type transistor P2, the second N-type transistor N2, the third P-type transistor P3, and the third N-type transistor N3 are all connected to the second input terminal In4 of the second and gate 312 as capacitors, so as to achieve a delay processing of the first offset cancellation signal OC1 transmitted through the second access line 332.

Since there are four transistors In the second delay circuit 322, it is equivalent to that there are four capacitors connected to the second input terminal In4 of the second and gate 312. The first delay circuit 321 includes two transistors, and two capacitors are connected to the second input terminal In2 of the first and gate 311. Therefore, the second delay circuit 322 delays the first offset cancel signal OC1 by a larger delay amount.

As shown in fig. 8, if the first offset cancellation signals OC1 are all low-level pulse signals. A first input terminal In3 of the second and gate 312 receives the first offset canceling signal OC1, and a second input terminal In4 of the second and gate 312 receives a second delayed signal, a falling edge time of which is later than that of the first offset canceling signal OC 1. The second and gate 312 performs and operation on the first offset cancellation signal OC1 and the second delayed signal, and outputs a fourth offset cancellation signal OC4 through an output terminal Out2 thereof. The fourth offset cancel signal OC4 is still a low-level pulse signal, and the pulse width of the fourth offset cancel signal OC4 increases by the time difference Δ τ 2 between the falling edges of the second delayed signal and the first offset cancel signal OC 1. Since the time difference Δ τ 2 of the falling edges of the second delayed signal and the first offset cancel signal OC1 is greater than the time difference Δ τ 1 of the falling edges of the first delayed signal and the first offset cancel signal OC1, the pulse width of the fourth offset cancel signal OC4 is greater than the pulse width of the third offset cancel signal OC3.

In some embodiments, as shown in fig. 9, the third regulation subunit 213 includes a third delay circuit 323 and a third and gate 313. The third delay circuit 323 has an input terminal and an output terminal, and the output terminal of the third delay circuit 323 is connected to the second input terminal In6 of the third and gate 313. The input terminal of the third delay circuit 323 receives the first offset cancellation signal OC1, the third delay circuit 323 delays the first offset cancellation signal OC1 to output a third delayed signal, and the delay amount of the third delay circuit 323 is greater than the delay amount of the second delay circuit 322. When the first offset canceling signal OC1 is a low-level pulse signal, a time difference Δ τ 3 between falling edges of the third delayed signal and the first offset canceling signal OC1 is greater than a time difference Δ τ 2 between falling edges of the second delayed signal and the first offset canceling signal OC 1.

A first input terminal In5 of the third and gate 313 receives the first offset canceling signal OC1, a second input terminal In6 of the third and gate 313 receives the third delayed signal, and the third and gate 313 and the first offset canceling signal OC1 and the third delayed signal and outputs a fifth offset canceling signal OC5 via an output terminal Out3 thereof.

In some embodiments, the third delay circuit 323 includes a third access line 333, a fourth P-type transistor P4, a fourth N-type transistor N4, a fifth P-type transistor P5, a fifth N-type transistor N5, a sixth P-type transistor P6, and a sixth N-type transistor N6. One end of the third access line 333 is connected to the second input terminal In6 of the third and gate 313, the other end of the third access line 333 receives the first offset cancellation signal OC1, and the third access line 333 transmits the first offset cancellation signal OC1 to the second input terminal In6 of the third and gate 313.

The gate of the fourth P-type transistor P4 is connected to the third connection line 333, and the drain of the fourth P-type transistor P4 is connected to the source of the fourth P-type transistor P4 and then connected to the first power terminal V1. The gate of the fourth N-type transistor N4 is connected to the third access line 333, and the drain of the fourth N-type transistor N4 is connected to the source of the fourth N-type transistor N4 and then connected to the second power terminal V2.

The gate of the fifth P-type transistor P5 is connected to the third connection line 333, and the drain of the fifth P-type transistor P5 is connected to the source of the fifth P-type transistor P5 and then connected to the first power terminal V1. The gate of the fifth N-type transistor N5 is connected to the third connection line 333, and the drain of the fifth N-type transistor N5 is connected to the source of the fifth N-type transistor N5 and then connected to the second power terminal V2.

The gate of the sixth P-type transistor P6 is connected to the third access line 333, and the drain of the sixth P-type transistor P6 is connected to the source of the sixth P-type transistor P6 and then connected to the first power terminal V1. The gate of the sixth N-type transistor N6 is connected to the third connection line 333, and the drain of the sixth N-type transistor N6 is connected to the source of the sixth N-type transistor N6 and then connected to the second power terminal V2.

With this arrangement, the fourth P-type transistor P4, the fourth N-type transistor N4, the fifth P-type transistor P5, the fifth N-type transistor N5, the sixth P-type transistor P6, and the sixth N-type transistor N6 are all connected as capacitors to the second input terminal In6 of the third and gate 313, so as to delay the first offset cancellation signal OC1 transmitted through the third access line 333. Since there are six transistors In the third delay circuit 323, six capacitors are connected to the second input terminal In6 of the third and gate 313. There are four transistors In the second delay circuit 322, and four capacitors are connected to the second input terminal In4 of the second and gate 312. Therefore, the third delay circuit 323 delays the first offset cancel signal OC1 by a larger amount than the second delay circuit 322.

As shown in fig. 10, the first offset canceling signals OC1 are all low-level pulse signals. A first input terminal In5 of the third and gate 313 receives the first offset canceling signal OC1, and a second input terminal In6 of the third and gate 313 receives a third delayed signal, a falling edge timing of which is later than that of the first offset canceling signal OC 1. After the third and gate 313 and the first offset cancellation signal OC1 and the third delayed signal, a fifth offset cancellation signal OC5 is output via an output end Out3 thereof, the fifth offset cancellation signal OC5 is still a low-level pulse signal, the pulse width of the fifth offset cancellation signal OC5 becomes larger, and the increase is the time difference Δ τ 3 between the falling edges of the third delayed signal and the first offset cancellation signal OC 1. Since the time difference Δ τ 3 of the falling edges of the third delayed signal and the first offset cancel signal OC1 is greater than the time difference Δ τ 2 of the falling edges of the second delayed signal and the first offset cancel signal OC1, the pulse width of the fifth offset cancel signal OC5 is greater than the pulse width of the fourth offset cancel signal OC4.

In the above technical solution, each adjusting subunit includes an and gate and a delay circuit, where the delay circuit is configured to perform delay processing on the first offset cancellation signal OC1, and the and gate is configured to perform and operation on the first offset cancellation signal OC1 and the delayed first offset cancellation signal OC1, so as to increase a pulse width of the first offset signal, and increase the pulse width by the amount of delay of the delay circuit. The number of transistors serving as capacitors in each delay circuit is different, so that the delay amount of the delay processing of the first offset cancellation signal OC1 can be adjusted, and the pulse width of the offset cancellation signal output by each adjusting subunit is different.

In some embodiments, as shown in fig. 4, the adjusting unit 210 further includes an inverter 215, an input terminal of the inverter 215 is connected to an output terminal of the selecting unit 214, and an output signal of the inverter 215 is used for controlling to eliminate the noise signal of the amplifying module.

In some embodiments, the output terminal of the inverter 215 is connected to the control terminal of the amplifying module 100 as the output terminal of the control module 200, and the amplifying module 100 eliminates the internal noise signal under the control of the output signal of the inverter.

In some embodiments, with continued reference to fig. 3, the amplification module 100 includes a seventh P-type transistor P7, an eighth P-type transistor P8, a seventh N-type transistor N7, an eighth N-type transistor N8, a ninth N-type transistor N9, a tenth N-type transistor N10, an eleventh N-type transistor N1, and a twelfth N-type transistor N12. The connection relationship of the transistors has been explained in detail in the description of fig. 1, and is not described in detail here.

In some embodiments, the amplification block 100 includes a ninth P-type transistor P9 and a thirteenth N-type transistor N13, a source of the ninth P-type transistor P9 is connected to the third power source terminal V3, and a drain of the ninth P-type transistor P9 is connected to the first terminal LA of the amplification block 100. A source of the thirteenth N-type transistor N13 is connected to the fourth power source terminal V4, and a drain of the thirteenth N-type transistor N13 is connected to the second terminal LAB of the amplifying module 100. The voltage of the third power source terminal V3 is greater than the voltage of the fourth power source terminal V4, and the fourth power source terminal V4 is normally a ground terminal.

The gate of the ninth N-type transistor N9 and the gate of the tenth N-type transistor N10 are both used as control terminals of the amplifying module 100 and are connected to the output terminal of the control module 200.

In some embodiments, when the first offset canceling signal OC is a low-level pulse signal, the output terminal of the inverter 215 is used as the output terminal of the control module 200, and the gate of the ninth N-type transistor N9 and the gate of the tenth N-type transistor N10 are both connected to the output terminal of the inverter 215.

As shown in fig. 11, during the precharge period T1, the isolation control signal ISO and the second offset canceling signal OC2 are high, the eleventh N-type transistor N11 and the twelfth N-type transistor N12 are both turned on, the bit line BL is connected to the sense bit line SABL, and the complementary bit line BLB is connected to the complementary sense bit line SABLB. The ninth N-type transistor N9 and the tenth N-type transistor N10 are all turned on, and the bit line BL, the sensing bit line SABL, the complementary bit line BLB, and the complementary sensing bit line SABLB are connected to each other. The first enable signal SAP received by the ninth P-type transistor P9 is at a high level, the second enable signal SAN received by the thirteenth N-type transistor N13 is at a low level, and the third and fourth power source terminals V3 and V4 are disconnected from the amplifying module 100. The voltage of the third power source terminal V3 is greater than the voltage of the fourth power source terminal V4. The voltages of bit line BL, complementary bit line BLB, sense bit line SABL, and complementary sense bit line SABLB are pulled to a charged value by a charging module.

In the offset canceling stage T2, the isolation control signal ISO is low, the eleventh N-type transistor N11 and the twelfth N-type transistor N12 are both turned off, the second offset canceling signal OC2 is high, the ninth N-type transistor N9 and the tenth N-type transistor N10 are turned on, and the seventh N-type transistor N7 and the eighth N-type transistor N8 are diode-connected. The ninth P-type transistor P9 receives the first enable signal SAP at a low level, the thirteenth N-type transistor N13 receives the second enable signal SAN at a high level, and the third and fourth power source terminals V3 and V4 are turned on with the amplifying module 100.

When the temperature data is within the first temperature range, the selection unit 214 in the control module 200 selects the third offset cancellation signal OC3 output by the first adjustment subunit 211 to output, and outputs a high-level pulse signal after non-operation by the inverter 215, at this time, the voltage driving capability of the amplification module 100 is relatively strong, the third offset cancellation signal OC3 with a smaller pulse width is selected to output, and the ninth N-type transistor N9 and the tenth N-type transistor N10 are controlled to be turned on, so that the duration of the offset cancellation stage T2 can be shortened, and after a compensation voltage Vos with a proper magnitude is generated on the bit line BL and the complementary bit line BLB, the ninth N-type transistor N9 and the tenth N-type transistor N10 are timely turned off, thereby preventing the ninth N-type transistor N9 and the tenth N-type transistor N10 from being turned on continuously to generate an excessive compensation voltage Vos.

When the temperature data is in the second temperature range, the selection unit 214 in the control module 200 selects the fourth offset cancellation signal OC4 output by the second adjustment subunit 212 to output, and outputs a high-level pulse signal after non-operation by the inverter 215, at this time, compared with the temperature data in the first temperature range, the voltage driving capability of the amplification module 100 is weakened, the fourth offset cancellation signal OC4 with a pulse width larger than the third offset cancellation signal OC3 is selected to output, and the ninth N-type transistor N9 and the tenth N-type transistor N10 are controlled to be turned on, so that the duration of the offset cancellation stage T2 can be properly prolonged to compensate for the weakened voltage driving capability of the transistors in the amplification module 100, and a compensation voltage Vos with a proper magnitude is generated on the bit line BL and the complementary bit line BLB.

When the temperature data is in the third temperature range, the selection unit 214 in the control module 200 selects the fifth offset cancellation signal OC5 output by the third adjustment subunit 213, and outputs a high-level pulse signal after non-operation by the inverter 215, at this time, compared with the temperature data in the second temperature range, the voltage driving capability of the amplification module 100 is weakened, the fifth offset cancellation signal OC5 having a pulse width larger than the fourth offset cancellation signal OC4 is selected to be output, and the ninth N-type transistor N9 and the tenth N-type transistor N10 are controlled to be turned on, so that the duration of the offset cancellation stage T2 can be further prolonged to compensate for the weakened voltage driving capability of the transistors in the amplification module 100, and a compensation voltage Vos with a proper magnitude is generated on the bit line BL and the complementary bit line BLB.

In the charge sharing stage T3, the isolation control signal ISO is at a low level, the eleventh N-type transistor N11 and the twelfth N-type transistor N12 are turned off, the second offset cancellation signal OC2 is at a low level, the ninth N-type transistor N9 and the tenth N-type transistor N10 are turned off, the first enable signal SAP received by the ninth P-type transistor P9 is at a high level, the second enable signal SAN received by the thirteenth N-type transistor N13 is at a low level, and the third power source terminal V3 and the fourth power source terminal V4 are disconnected from the amplifying module 100. The word line signal is active and the memory cell shares charge with either bit line BL or complementary bit line BLB.

The sense amplifying stage T4, the isolation control signal ISO is low, the eleventh N-type transistor N11 and the twelfth N-type transistor N12 are turned off, the second offset canceling signal OC2 is low, the ninth N-type transistor N9 and the tenth N-type transistor N10 are turned off, the first enable signal SAP received by the ninth P-type transistor P9 is low, the second enable signal SAN received by the thirteenth N-type transistor N13 is high, the third power terminal V3 and the fourth power terminal V4 pull the voltages of the sense bit line SABL and the complementary sense bit line SABLB based on the difference in the data voltages on the bit line BL and the complementary sense bit line BLB, and the compensation voltage Vos, which may cancel a noise signal caused by the manufacturing difference between the seventh N-type transistor N7 and the eighth N-type transistor N8 in the sense amplifier, accurately presents data on the sense bit line SABL and the complementary sense bit line SABL BLB, due to the compensation voltage Vos already existing on the sense bit line SABL and the complementary sense bit line sabb.

In a recovery period T5, the isolation control signal ISO is at a high level, the eleventh N-type transistor N11 and the twelfth N-type transistor N12 are turned on, the second offset cancellation signal OC2 is at a low level, the ninth N-type transistor N9 and the tenth N-type transistor N10 are turned off, the first enable signal SAP received by the ninth P-type transistor P9 is at a low level, the second enable signal SAN received by the thirteenth N-type transistor N13 is at a high level, the bit line BL voltage is pulled by the sense bit line SABL, and the complementary bit line BLB voltage is pulled by the complementary sense bit line SABLB to recover the charges stored in the memory cell.

In the above technical solution, the sense amplifier includes a control module and an amplification module, where the control module is configured to adjust a pulse width of the first offset cancellation signal according to temperature data of the amplification module to compensate for a situation that a transistor in the amplification module changes with temperature, so that compensation voltages with appropriate magnitudes are generated on the bit line and the complementary bit line, thereby accurately canceling a noise signal of the amplification module 100 and improving accuracy of the sense amplifier.

An embodiment of the present disclosure further provides a semiconductor memory including the sense amplifier provided in the above embodiment.

Other embodiments of the disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the disclosure disclosed herein. This disclosure is intended to cover any variations, uses, or adaptations of the disclosure following, in general, the principles of the disclosure and including such departures from the present disclosure as come within known or customary practice within the art to which the disclosure pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the disclosure being indicated by the following claims.

It will be understood that the present disclosure is not limited to the precise arrangements that have been described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present disclosure is limited only by the appended claims.

Claims

1. A sense amplifier, comprising:

the control module is provided with an input end and an output end and is used for acquiring temperature data of the amplification module, carrying out pulse width adjustment on the first offset cancellation signal received by the input end of the control module according to the temperature data of the amplification module, and generating and outputting a second offset cancellation signal;

and the control end of the amplification module is connected with the output end of the control module, and the amplification module is used for eliminating the noise signal of the amplification module under the control of the second offset elimination signal.

2. The sense amplifier of claim 1, wherein the control module comprises:

and the regulating unit is provided with an input end, an output end and a control end, the control end of the regulating unit is connected with the output end of the pulse width parameter unit, the input end of the regulating unit receives the first offset eliminating signal, carries out pulse width regulating processing on the first offset eliminating signal according to the pulse width regulating signal and outputs the second offset eliminating signal.

3. The sense amplifier of claim 2, wherein the pulse width parameter unit includes three outputs, the pulse width adjustment signal includes three gating signals, and the adjustment unit includes:

the output end of the first adjusting subunit is connected with the first input end of the selection unit, and the first adjusting subunit is used for performing pulse width adjustment on the first offset cancellation signal and outputting a third offset cancellation signal;

the output end of the second adjusting subunit is connected with the second input end of the selection unit, and the second adjusting subunit is used for performing pulse width adjustment on the first offset cancellation signal and outputting a fourth offset cancellation signal;

the output end of the third adjusting subunit is connected with the third input end of the selecting unit, and is used for performing pulse width adjustment on the first offset cancellation signal and outputting a fifth offset cancellation signal; wherein a pulse width of the third offset cancellation signal, a pulse width of the fourth offset cancellation signal, and a pulse width of the fifth offset cancellation signal are all different;

the selection unit is provided with three control ends, and each control end is connected with the corresponding output end of the pulse width parameter unit and receives the corresponding gating signal; for selecting one output from the third offset cancellation signal, the fourth offset cancellation signal and the fifth offset cancellation signal under the control of the three gating signals, the output signal of the selection unit being used for controlling the cancellation of the noise signal of the amplification module.

4. The sense amplifier of claim 3, wherein the adjustment unit further comprises:

5. The sense amplifier of claim 3 or 4, wherein the first regulation subunit comprises:

a first delay circuit, the input end of which receives the first offset cancellation signal, and is used for performing delay processing on the first offset cancellation signal and outputting a first delay signal;

and a first input end of the first AND gate receives the first offset cancellation signal, a second input end of the first AND gate is connected with an output end of the first delay circuit, receives the first delay signal, and an output end of the first AND gate outputs the third offset cancellation signal.

6. The sense amplifier of claim 5, wherein the first delay circuit comprises:

and the grid electrode of the first N-type transistor is connected with the first access line, and the drain electrode of the first N-type transistor is connected with the source electrode of the first N-type transistor and then connected with a second power supply end.

7. The sense amplifier of claim 3 or 4, wherein the second regulation subunit comprises:

a second delay circuit, the input end of which receives the first offset cancellation signal, and is used for performing delay processing on the first offset cancellation signal and outputting a second delay signal; the delay amount of the second delay circuit for delay processing is larger than that of the first delay circuit for delay processing;

and a second and gate, a first input terminal of which receives the first offset cancellation signal, a second input terminal of which is connected to the output terminal of the second delay circuit, receives the second delay signal, and an output terminal of which outputs the fourth offset cancellation signal.

8. The sense amplifier of claim 7, wherein the second delay circuit comprises:

a grid electrode of the third P-type transistor is connected with the second access line, and a drain electrode of the third P-type transistor is connected with the first power supply end after being connected with a source electrode of the third P-type transistor;

and the grid electrode of the third N-type transistor is connected with the second access line, and the drain electrode of the third N-type transistor is connected with the source electrode of the third N-type transistor and then connected with a second power supply end.

9. The sense amplifier of claim 4, wherein the third regulation subunit comprises:

a third delay circuit, an input end of which receives the first offset cancellation signal, and is used for performing delay processing on the first offset cancellation signal to output a third delay signal; the delay amount of the third delay circuit for performing delay processing is larger than that of the second delay circuit for performing delay processing;

and a third and gate, a first input terminal of which receives the first offset cancellation signal, a second input terminal of which is connected to the output terminal of the third delay circuit, receives the third delay signal, and an output terminal of which outputs the fifth offset cancellation signal.

10. The sense amplifier of claim 9, wherein the third delay circuit comprises:

a fourth P-type transistor, a grid electrode of which is connected with the third access line, and a drain electrode of which is connected with a source electrode and then connected with a first power supply end;

a fifth P-type transistor, a grid electrode of which is connected with the third access line, and a drain electrode of which is connected with a source electrode and then connected with a first power supply end;

a fifth N-type transistor, a grid electrode of which is connected with the third access line, and a drain electrode of which is connected with a source electrode and then connected with a second power supply end;

and the grid electrode of the sixth N-type transistor is connected with the third access line, and the drain electrode of the sixth N-type transistor is connected with the source electrode of the sixth N-type transistor and then connected with the second power supply end.

11. The sense amplifier of claim 2, wherein the pulse width parameter unit comprises:

and the input end of the temperature decoder is connected with the output end of the temperature sensor, and the temperature decoder is used for generating the pulse width adjusting signal according to the temperature encoding data.

12. The sense amplifier of claim 3, wherein the pulse width parameter unit is configured to:

when the temperature data is in a first temperature range, the output first gating signal is an effective value, and the output second gating signal and the output third gating signal are invalid values; controlling the selection unit to select the third offset cancellation signal to be output;

when the temperature data is in a second temperature range, the output second gating signal is an effective value, and the output first gating signal and the output third gating signal are invalid values; controlling the selection unit to select the fourth offset cancellation signal to be output;

when the temperature data is within a third temperature range, the output third gating signal is an effective value, and the output first gating signal and the output second gating signal are invalid values; controlling the selection unit to select the fifth offset cancellation signal output;

wherein the upper limit value of the first temperature range is less than or equal to the lower limit value of the second temperature range, and the upper limit value of the second temperature range is less than or equal to the lower limit value of the third temperature range; the pulse width of the third offset cancellation signal is smaller than the pulse width of the fourth offset cancellation signal, and the pulse width of the fourth offset cancellation signal is smaller than the pulse width of the fifth offset cancellation signal.

13. The sense amplifier of claim 1, wherein the amplification module comprises:

the grid electrode of the eighth P-type transistor is connected with the drain electrode of the seventh P-type transistor;

the drain electrode of the eighth N-type transistor is connected with the drain electrode of the eighth P-type transistor, and the gate electrode of the eighth N-type transistor is connected with a complementary bit line;

a ninth N-type transistor, a first end of which is connected with a bit line, a second end of which is connected with the drain electrode of the seventh N-type transistor, and a grid electrode of which is used as the control end of the amplifying module;

and the second end of the tenth N-type transistor is connected with the complementary bit line, the first end of the tenth N-type transistor is connected with the drain electrode of the eighth N-type transistor, and the grid electrode of the tenth N-type transistor is used as the control end of the amplifying module.

14. The sense amplifier of claim 13, wherein the amplifying module comprises:

an eleventh N-type transistor, a first end of which is connected to the bit line, a second end of which is connected to the drain of the eighth N-type transistor, and a gate of which receives an isolation control signal;

a twelfth N-type transistor having a second end connected to the complementary bit line, a first end connected to the drain of the seventh N-type transistor, and a gate receiving an isolation control signal.

15. The sense amplifier of claim 13, wherein the amplification module comprises:

a ninth P-type transistor having a source connected to a third power supply terminal and a drain connected to the source of the seventh P-type transistor;

16. A semiconductor memory comprising a sense amplifier as claimed in any one of claims 1 to 15.