CN114822617A

CN114822617A - Sensitive amplifier

Info

Publication number: CN114822617A
Application number: CN202210499913.7A
Authority: CN
Inventors: 杨宇
Original assignee: Changxin Memory Technologies Inc
Current assignee: Changxin Memory Technologies Inc
Priority date: 2022-05-09
Filing date: 2022-05-09
Publication date: 2022-07-29

Abstract

The application provides a sensitive amplifier, including the control module, it is equipped with input and output for carry out the pulse width adjustment according to the first skew cancelling signal that transistor technology angle received to the input, generate and output second skew cancelling signal, the amplifier module is connected with the output of control module, and it is used for eliminating the skew noise of amplifier module under the control of second skew cancelling signal. According to the scheme, the compensation voltage with proper size can be formed on the read bit line and the complementary read bit line, noise caused by manufacturing difference of the transistors is accurately eliminated, and the accuracy of the sensitive amplifier is improved.

Description

Sensitive amplifier

Technical Field

The present application relates to, but is not limited to, a sense amplifier.

Background

With the shrinking line width of the semiconductor memory, the capacitance of the memory cell in the semiconductor memory decreases, so that the noise has a greater influence on the normal operation of the semiconductor memory.

The sense amplifier can eliminate noise caused by manufacturing variations of transistors in the semiconductor memory, so that the semiconductor memory can accurately store data. When the sense amplifier operates in the offset cancellation stage, compensation voltages are formed on the sense bit lines and the complementary sense bit lines, and the noise cancellation effect is affected by the magnitude of the compensation voltages.

Therefore, how to generate a properly sized compensation voltage on the bit line and complementary bit line is critical to semi-eliminating noise in the semiconductor memory.

Disclosure of Invention

An embodiment of the present application provides a sense amplifier, including:

the control module comprises an input end and an output end, and is used for adjusting the pulse width of the first offset cancellation signal received by the input end of the control module according to the transistor process angle, generating and outputting a second offset cancellation signal through the output end of the control module;

and the amplifying module is connected with the output end of the control module and is used for eliminating the offset noise of the amplifying module under the control of the second offset eliminating signal.

In one embodiment, the control module includes:

the parameter generating circuit is used for generating a pulse width adjusting signal according to a transistor process angle of the parameter generating circuit;

and the control end of the adjusting circuit is connected with the output end of the parameter generating circuit, and the input end of the adjusting circuit receives the first offset eliminating signal, adjusts the pulse width of the first offset eliminating signal according to the pulse width adjusting signal and outputs a second offset eliminating signal.

In one embodiment, the parameter generation circuit includes:

an oscillation control unit for generating an oscillation enable signal of a fixed time width;

the control end of the ring oscillator is connected with the output end of the oscillation control unit and is used for generating an oscillation signal when receiving the oscillation enabling signal;

and the input end of the oscillation counter is connected with the output end of the ring oscillator, and the oscillation counter is used for counting the number of oscillation signals within a fixed time width and outputting a pulse width adjusting signal.

In one embodiment, the transistor process corner of the ring oscillator is the same as the transistor process corner of the amplification module, and the number of oscillation signals generated within the fixed time width is determined by the transistor process corner of the ring oscillator.

In one embodiment, the ring oscillator includes an odd number of first nand gates;

for each first NAND gate circuit, a first input end of the first NAND gate circuit is connected with an output end of a first NAND gate circuit positioned at the previous stage, an output end of the first NAND gate circuit is connected with a first input end of a first NAND gate circuit positioned at the next stage, and a first input end of the first NAND gate circuit is connected with an output end of a first NAND gate at the last stage;

the second input ends of odd first NAND gate circuits are connected to the same node, and the node is used as the control end of the ring oscillator; the output of any one of the first nand gates serves as the output of the ring oscillator.

In one embodiment, the oscillation control unit is configured to output an active oscillation enable signal after the oscillation start signal arrives, and output an inactive oscillation enable signal after the oscillation stop signal arrives.

In one embodiment, the oscillation control unit includes:

a second NAND gate circuit, a first input end of which receives the oscillation starting signal;

a first not gate circuit, an input terminal of which receives an oscillation termination signal; the output end of the first NAND gate circuit is connected with the first input end of the first NAND gate circuit;

and the input end of the second NOT gate circuit is connected with the output end of the second NOT gate circuit, and the output end of the second NOT gate circuit is used as the output end of the oscillation control unit.

In one embodiment, the parameter generating circuit includes a plurality of output terminals, the pulse width adjusting signal includes a plurality of pulse width adjusting sub-signals, and the output terminals of the parameter generating circuit respectively output the pulse width adjusting sub-signals;

the adjusting circuit comprises a plurality of adjusting sub-modules which are sequentially cascaded; the control end of each adjusting submodule is connected with one output end of the parameter generating circuit;

the first-stage adjusting submodule receives the first offset cancellation signal and is used for adjusting the pulse of the first offset cancellation signal according to the received pulse width adjusting sub-signal;

the rest of each level of adjusting sub-module receives the output signal of the previous level of adjusting sub-module and adjusts the pulse of the output signal of the previous level of adjusting sub-module according to the pulse width adjusting sub-signal received by the control end of the adjusting sub-module; and the output signal of the last-stage adjusting submodule is a second offset eliminating signal.

In one embodiment, each of the adjustment sub-modules includes:

the input end of the delay unit is used as the input end of the adjusting submodule;

the first input end of the OR gate circuit is connected with the output end of the delay unit, and the second input end of the OR gate circuit is used as the control end of the adjusting submodule;

and the first input end of the AND circuit is connected with the input end of the delay unit, the second input end of the AND circuit is connected with the output end of the OR gate circuit, and the output end of the AND circuit is used as the output end of the adjusting submodule.

In one embodiment, if the first offset cancellation signal is an active high signal, the oscillation counter is a down counter;

if the first offset cancellation signal is an active low signal, the oscillation counter is an up counter.

In one embodiment, the amplification module comprises:

a first P-type transistor, the source of which is coupled to the first power terminal, and the gate of which is connected to the drain of the second P-type transistor;

the source electrode of the second P-type transistor is connected with the source electrode of the first P-type transistor, and the grid electrode of the second P-type transistor is connected with the drain electrode of the first P-type transistor;

a first N-type transistor, the drain of which is connected to the drain of the first P-type transistor, the gate of which is connected to the bit line, and the source of which is coupled to a second power supply terminal;

a second N-type transistor, the drain of which is connected with the drain of the second P-type transistor, the grid of which is connected with the complementary bit line, and the source of which is connected with the source of the first N-type transistor;

a third N-type transistor, the drain of which is connected with the drain of the first N-type transistor, and the source of which is connected with the bit line; the grid of the first offset cancellation circuit is conducted when receiving the first offset cancellation signal;

a fourth N-type transistor, the drain of which is connected with the drain of the second N-type transistor, and the source of which is connected with the complementary bit line; the gate of which is turned on when receiving the second offset canceling signal.

In one embodiment, the process corner of the third N-type transistor, the process corner of the fourth N-type transistor, and the process corner of the transistors of the ring oscillator are the same.

In one embodiment, the amplification module further comprises:

a fifth N-type transistor, the drain of which is connected to the drain of the second N-type transistor and then to the read bit line, the source of which is connected to the bit line, and the gate of which is used for receiving the pre-charge signal and is turned on under the control of the pre-charge signal;

a sixth N-type transistor, the drain of which is connected to the drain of the first N-type transistor and then to the complementary read bit line, and the source of which is connected to the complementary bit line; the gate of which is used to receive a pre-charge signal for conduction under the control of the pre-charge signal.

In one embodiment, the signal delay between the first offset cancellation signal and the pre-charge signal is preset.

In one embodiment, the amplification module further comprises:

a third P-type transistor having a source connected to the first power terminal and a drain connected to the source of the first P-type transistor;

and the source electrode of the seventh N-type transistor is connected with the second power supply end, and the drain electrode of the seventh N-type transistor is connected with the source electrode of the first N-type transistor.

The embodiment of the application provides a sense amplifier, which comprises a control module and an amplification module, wherein the control module adjusts the pulse width of a first offset cancellation signal based on a transistor process angle to obtain a second offset cancellation signal, and controls the time of the amplification module for forming compensation voltage on a read bit line and a complementary read bit line based on the second offset cancellation signal, so that compensation voltage with proper size is formed on the read bit line and the complementary read bit line, noise caused by manufacturing difference of transistors is accurately eliminated, and the accuracy of the sense amplifier is improved.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and together with the description, serve to explain the principles of the application.

FIG. 1 is a circuit configuration diagram of a sense amplifier;

fig. 2 is a schematic structural diagram of a sense amplifier according to an embodiment of the present disclosure;

fig. 3 is a schematic structural diagram of a control module according to an embodiment of the present application;

fig. 4 is a schematic structural diagram of an adjustment submodule provided in an embodiment of the present application;

fig. 5A is a schematic diagram of an operation principle of the adjusting submodule according to an embodiment of the present application;

fig. 5B is a schematic diagram illustrating another operation principle of the adjusting submodule according to an embodiment of the present application;

fig. 6 is a schematic structural diagram of a parameter generating circuit according to an embodiment of the present application;

fig. 7 is a schematic structural diagram of an oscillation control unit according to an embodiment of the present application;

fig. 8 is a schematic diagram illustrating an operation principle of an oscillation control unit according to an embodiment of the present application;

fig. 9 is a timing diagram of a sense amplifier according to an embodiment of the present application.

Reference numerals:

100. a control module; 110. adjusting the submodule; 111. a delay unit; 112. an OR gate circuit; 113. an AND gate circuit; 120. a parameter generation circuit; 200. an amplifying module; 210. an oscillation control unit; 211. a first not gate circuit; 212. a second NAND gate circuit; 213. a second not gate circuit; 220. a ring oscillator; 221. a first NAND gate circuit; 230. a counter is oscillated.

With the above figures, there are shown specific embodiments of the present application, which will be described in more detail below. These drawings and written description are not intended to limit the scope of the inventive concepts in any manner, but rather to illustrate the inventive concepts to those skilled in the art by reference to specific embodiments.

Detailed Description

Reference will now be made in detail to the exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, like numbers in different drawings represent the same or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present application. Rather, they are merely examples of apparatus and methods consistent with certain aspects of the present application, as detailed in the appended claims.

As shown in FIG. 1, a sense amplifier includes a first P-type transistor P1, a second P-type transistor P2, a first N-type transistor N1, and a second N-type transistor N2.

The gate of the first P-type transistor P1 is connected to the drain of the second P-type transistor P2, and the gate of the second P-type transistor P2 is connected to the drain of the first P-type transistor P1.

The sense amplifier further includes a third N-type transistor N3 and a fourth N-type transistor N4. The drain of the first N-type transistor N1 is connected to the gate of the first N-type transistor N1 through a third N-type transistor N3, and the gate of the first N-type transistor N1 is connected to the bit line BL. The gate of the second N-type transistor N2 is connected to the drain of the second N-type transistor N2 through a fourth N-type transistor N4, and the gate of the second N-type transistor N2 is connected to the complementary bit line BLB.

The sense amplifier further includes a fifth N-type transistor N5 and a sixth N-type transistor N6. The gate of the first N-type transistor N1 is connected to the drain of the second N-type transistor N2 via a fifth N-type transistor N5, and the drain of the second N-type transistor N2 is connected to the drain of the second P-type transistor P2, and then to the read bit line SABL. The gate of the second N-type transistor N2 is connected to the drain of the first N-type transistor N1 through a sixth N-type transistor N6, and the drain of the first N-type transistor N1 is connected to the drain of the first P-type transistor P1 and then to the complementary sense bit line SABLB.

During the offset cancellation phase, the third N-type transistor N3 and the fourth N-type transistor N4 are both turned on, and the first N-type transistor N1 and the second N-type transistor N2 are both operated in a diode state, generating a compensation voltage on the bit line BL and the complementary bit line BLB, and also generating a compensation voltage on the sense bit line SABL and the complementary sense bit line SABLB.

Since the compensation voltages are already stored on the sensing bitline SABL and the complementary sensing bitline SABLB, the compensation voltages can cancel noise caused by manufacturing differences of the first N-type transistor N1 and the second N-type transistor N2 in the sense amplifier during the pre-sensing stage, and data can be accurately represented on the bitline BL and the complementary bitline BLB.

In the recovery phase, the fifth N-type transistor N5 and the sixth N-type transistor N6 are both turned on, the bit line BL is connected to the sensing bit line SABL, and the complementary bit line BLB is connected to the complementary sensing bit line SABLB, so that data in the memory cell can be recovered.

The magnitude of the compensation voltage affects the noise cancellation effect, and the excessive compensation voltage and the insufficient compensation voltage cannot accurately cancel the manufacturing difference between the first N-type transistor N1 and the second N-type transistor N2. The magnitude of the compensation voltage is related to the driving capability of the transistors of the sense amplifier. As the driving capability of the transistor is stronger, a larger compensation voltage can be formed on the sense bit line SABL and the complementary sense bit line SABLB. As the driving capability of the transistor is weaker, the compensation voltage formed on the sense bit line SABL and the complementary sense bit line SABLB is smaller.

In order to more accurately form compensation voltages with proper sizes on the sensing bit line SABL and the complementary sensing bit line SABLB, the present application adjusts the width of an offset cancellation signal based on the driving capability of transistors of a sense amplifier, so that the sense amplifier generates the compensation voltage with the proper size under the control of the adjusted offset cancellation signal, accurately eliminates noise caused by manufacturing differences of the first N-type transistor N1 and the second N-type transistor N2, and improves the accuracy of the sense amplifier.

As shown in fig. 2, an embodiment of the present application provides a sense amplifier, which includes a control module 100 and an amplification module 200.

The control module 100 has an input end and an output end, the input end of the control module 100 receives the first offset cancellation signal OC, and the control module 100 performs pulse width adjustment on the first offset cancellation signal OC according to a transistor process corner to generate and output a second offset cancellation signal OC'. The output terminal of the control module 100 is connected to the control terminal of the amplifying module 200, and the amplifying module 200 generates compensation voltages on the sensing bit line SABL and the complementary sensing bit line SABLB under the control of the second offset canceling signal OC 'to achieve the cancellation of the offset noise of the amplifying module 200 under the control of the second offset canceling signal OC'.

The first offset cancellation signal OC is a pulse signal, and the pulse width of the first offset cancellation signal OC is determined according to the design parameters of each transistor in the amplification module 200.

In an embodiment, since the process angles of the transistors in the manufacturing process of the sense amplifier are the same, the pulse width of the first offset cancellation signal OC may be adjusted according to the process angle of the transistor of the amplifying module 200, and the pulse width of the first offset cancellation signal OC may also be adjusted according to the process angle of the transistor of the control module 100.

In one embodiment, the smaller the pulse width of the second offset cancellation signal OC' is if the transistor process corner is FF (new-FAST-corner & fine-FAST-corner). The larger the pulse width of the second offset cancellation signal OC' is if the transistor process corner is SS (new-SLOW corner & soft-SLOW corner).

When the sense amplifier is in operation, if the process angle of the transistor is SS, the weaker the driving capability of the transistor of the amplification module 200 is, the slower the speed of the transistor pulling the voltages of the sensing bit line SABL and the complementary sensing bit line SABLB is, the larger the pulse width of the second offset canceling signal OC', and the longer the offset canceling phase time is, there is enough time to form a compensation voltage with a proper magnitude on the sensing bit line BL and the complementary sensing bit line SABLB. If the process angle of the transistor is FF, the stronger the driving capability of the transistor of the amplifying module 200 is, the faster the speed of the transistor pulling the voltages of the sensing bit line SABL and the complementary sensing bit line SABLB is, and the smaller the pulse width of the second offset canceling signal OC', the shorter the offset canceling phase time is, which can avoid the too long time to cause the too large formed compensating voltage, and ensure that the compensating voltage with a proper size is formed on the sensing bit line SABL and the complementary sensing bit line SABLB. After the compensation voltage with proper size is formed on the sensing bit line SABL and the complementary sensing bit line SABLB, the compensation voltage can offset noise caused by manufacturing difference of transistors in the sense amplifier in a pre-sensing stage, data on the sensing bit line SABL and the complementary sensing bit line SABLB can be accurately amplified, and accuracy of the sense amplifier is improved.

In the above technical solution, the sense amplifier includes a control module 100 and an amplification module 200, the control module 100 adjusts a pulse width of the first offset cancellation signal OC based on a transistor process angle to obtain a second offset cancellation signal OC ', and controls a time for the amplification module 200 to form a compensation voltage on the sense bit line SABL and the complementary sense bit line SABLB based on the second offset cancellation signal OC', so as to form a compensation voltage with an appropriate size on the sense bit line SABL and the complementary sense bit line SABLB, accurately eliminate noise caused by a manufacturing difference of transistors, and improve accuracy of the sense amplifier.

In one embodiment, the control module 100 includes a parameter generating circuit 120 and an adjusting circuit, the adjusting circuit has an input terminal, an output terminal and a control terminal, the parameter generating circuit 120 has an output terminal, and the control terminal of the adjusting circuit is connected to the output terminal of the parameter generating circuit 120. The parameter generating circuit 120 generates a pulse width adjusting signal according to a transistor process corner of the parameter generating circuit, inputs the pulse width adjusting signal to a control terminal of the adjusting circuit, an input terminal of the adjusting circuit receives the first offset canceling signal OC, and the adjusting circuit is configured to adjust a pulse width of the first offset canceling signal OC according to the pulse width adjusting signal and output a second offset canceling signal OC'.

In one embodiment, as shown in fig. 3, the adjusting circuit includes a plurality of cascaded adjusting sub-modules 110, each adjusting sub-module 110 having an input terminal a1, an output terminal a2, and a control terminal a 3. The cascade connection of the plurality of adjusting sub-modules 110 means that the output terminal a2 of the previous adjusting sub-module 110 is connected to the input terminal a1 of the next adjusting sub-module 110.

The parameter generating circuit 120 includes a plurality of output terminals, and the number of the output terminals of the parameter generating circuit 120 is the same as the number of the adjusting sub-modules 110, so that the control terminal a3 of each adjusting sub-module 110 is connected to one output terminal of the parameter generating circuit 120. The pulse width adjusting signal includes a plurality of pulse width adjusting sub-signals, the number of the pulse width adjusting sub-signals is the same as the number of the output terminals of the parameter generating circuit 120, and one pulse width adjusting sub-signal is output from the output terminal of one parameter generating circuit 120.

The input end a1 of the first-stage adjusting submodule 110 receives the first offset cancellation signal OC, the parameter generating circuit 120 inputs a corresponding pulse width adjusting sub-signal to the control end a3 of the first-stage adjusting submodule 110, and the first-stage adjusting submodule 110 is configured to adjust the pulse width of the first offset cancellation signal OC according to the received pulse width adjusting sub-signal. For each of the rest of the adjusting sub-modules 110, the parameter generating circuit 120 inputs a corresponding pulse width adjusting sub-signal to the control terminal a3 of the corresponding adjusting sub-module 110, and each of the adjusting sub-modules 110 receives an output signal of the previous adjusting sub-module 110 and adjusts the pulse width of the output signal of the previous adjusting sub-module 110 according to the received pulse width adjusting sub-signal. The output a2 of the last stage of the adjusting submodule 110 is used for outputting the second offset canceling signal OC'.

For example: the trimming circuit includes n trimming sub-modules 110, which are sequentially labeled as a first-level trimming sub-module 110, a second-level trimming sub-module 110, … …, and an nth-level trimming sub-module 110. The parameter generating circuit 120 includes n output terminals, which are labeled as a first output terminal Q1, a second output terminal Q2, … …, and an nth output terminal Q (n), in that order.

The control end a3 of the first-stage adjusting submodule 110 is connected with the first output end Q1 of the parameter generating circuit 120, and the output end a2 of the first-stage adjusting submodule 110 is connected with the input end a1 of the second-stage adjusting submodule 110; the control end a3 of the second-stage adjusting submodule 110 is connected with the second output end Q2 of the parameter generating circuit 120, and the output end a2 of the second-stage adjusting submodule 110 is connected with the input end a1 of the third-stage adjusting submodule 110; and so on; the control terminal a3 of the nth-stage adjusting sub-module 110 is connected to the nth output terminal q (n) of the parameter generating circuit 120, and the output terminal a2 of the (n-1) th-stage adjusting sub-module 110 is connected to the input terminal a1 of the nth-stage adjusting sub-module 110.

The input terminal a1 of the first-stage adjusting submodule 110 is configured to receive the first offset cancellation signal OC, and the first-stage adjusting submodule 110 is configured to perform a pulse width adjustment process on the first offset cancellation signal OC according to the pulse width adjustment sub signal received by the control terminal a3 of the first-stage adjusting submodule 110. The second-stage adjusting sub-module 110 is configured to perform a pulse width adjusting process on an output signal of the first-stage adjusting sub-module 110 according to the pulse width adjusting sub-signal received by the control terminal a 3. The third-stage adjusting submodule 110 is configured to perform a pulse width adjusting process on an output signal of the second-stage adjusting submodule 110 according to the pulse width adjusting sub-signal received by the control terminal a 3. By analogy, the nth-level adjusting sub-module 110 is configured to perform a pulse width adjusting process on an output signal of the (n-1) th-level adjusting sub-module 110 according to the pulse width adjusting sub-signal received by the control terminal a 3.

In one embodiment, if a pulse width modulation sub-signal is active, the modulation sub-module 110 performs a pulse width modulation process on the output signal of the previous modulation sub-module 110. If a pulse width adjustment sub-signal is invalid, the adjustment sub-module 110 directly outputs the output signal of the previous adjustment sub-module 110.

In the above technical solution, the pulse width adjustment signal is determined based on the transistor process angle, and the number of the adjustment sub-modules 110 for performing the pulse width adjustment is adjusted, so that the pulse width of the second offset cancellation signal OC' output by the last-stage adjustment sub-module 110 can be adjusted.

In an embodiment, each of the adjusting sub-modules 110 is configured to perform a pulse width reduction process on the output signal of the previous adjusting sub-module 110 or the first offset cancellation signal OC, so that the pulse width of the output second offset cancellation signal OC' is smaller than the pulse width of the first offset cancellation signal OC.

In an embodiment, each of the adjusting sub-modules 110 is configured to perform a pulse width increasing process on the output signal of the previous adjusting sub-module 110 or the first offset cancellation signal OC, so that the pulse width of the output second offset cancellation signal OC' is greater than the pulse width of the first offset cancellation signal OC.

In one embodiment, as shown in FIG. 4, each of the trimming sub-modules 110 includes a delay unit 111, an OR gate 112, and an AND gate 113. The delay unit 111 has an input terminal and an output terminal, the input terminal of the delay unit 111 is used as the input terminal a1 of the adjusting submodule 110, and the input terminal of the delay unit 111 is used for receiving the first offset cancellation signal OC or the output signal of the adjusting submodule 110 at the previous stage. The or gate 112 has a first input terminal, a second input terminal, and an output terminal, where the first input terminal of the or gate 112 is connected to the output terminal of the delay unit 111, and the second input terminal of the or gate 112 is used as the control terminal a3 of the adjusting submodule 110, and is connected to a corresponding output terminal of the parameter generating circuit 120. The and circuit 113 has a first input terminal, a second input terminal, and an output terminal. A first input terminal of the and circuit 113 is connected to the input terminal of the delay unit 111, a first input terminal of the and circuit 113 is configured to receive the first offset cancellation signal OC or the output signal of the previous-stage adjustment submodule 110, a second input terminal of the and circuit 113 is connected to the output terminal of the or circuit 112, and an output terminal of the and circuit 113 serves as the output terminal a2 of the adjustment submodule 110 and is configured to be connected to the input terminal a1 of the next-stage adjustment submodule 110.

For the first-stage adjusting submodule 110, an input terminal of the delay unit 111 receives the first offset cancellation signal OC, and for the adjusting submodule 110 except the first-stage adjusting submodule 110, an input terminal of the delay unit 111 receives an output signal of the previous-stage adjusting submodule 110, and for convenience of description, the output signal of the previous-stage adjusting submodule 110 or the first offset cancellation signal OC is collectively referred to as a signal to be processed S1.

As shown in fig. 5A, when the signal to be processed S1 is an active high signal, the delay unit 111 is configured to perform a delay process on the signal to be processed S1, and generate a delayed signal to be processed S2. When the pulse width adjustment sub-signal received by the second input terminal of the or gate circuit 112 is at a low level, the or gate circuit 112 outputs the delayed signal to be processed S2. The and circuit 113 performs an and operation on the signal to be processed S1 and the delayed signal to be processed S2 to obtain an output signal S3 having a pulse width Δ T2, which is shorter than the pulse width Δ T1 of the signal to be processed.

As shown in fig. 5B, when the pulse width adjustment sub-signal received by the second input terminal of the or gate circuit 112 is at a high level, the or gate circuit 112 outputs a high level S4, and the and gate circuit 113 performs an and operation on the high level S4 and the signal to be processed S1, so that the pulse width of the output signal S5 is the same as the width of the signal to be processed S1.

In the above technical solution, the adjusting sub-module 110 includes a delay unit 111, an and circuit 113 and an or circuit 112, when the pulse width adjusting sub-signal received by the second input terminal of the or circuit 112 is at a high level, the and circuit 113 directly outputs the output signal of the adjusting sub-module 110 at the previous stage, and when the pulse width adjusting sub-signal received by the second input terminal of the or circuit 112 is at a low level, the and circuit 113 outputs an output signal with a smaller pulse width, so that the adjusting sub-module 110 can perform the pulse width adjusting process on the output signal of the adjusting sub-module 110 at the previous stage based on the pulse width adjusting sub-signal.

In one embodiment, as shown in fig. 6, the parameter generation circuit 120 includes an oscillation control unit 210, a ring oscillator 220, and an oscillation counter 230. The oscillation control unit 210 is configured to generate an oscillation enable signal with a fixed time width, the oscillation control unit 210 is provided with an output end, the ring oscillator 220 is provided with a control end and an output end, and the output end of the oscillation control unit 210 is connected to the control end of the ring oscillator 220. The ring oscillator 220 is configured to generate at least one oscillating signal within a fixed time width, the number of oscillating signals generated by the ring oscillator 220 within the fixed time width being determined by the transistor process corner of the ring oscillator 220. Oscillation counter 230 has an input and an output. The input terminal of the oscillation counter 230 is connected to the output terminal of the ring oscillator 220, and the oscillation counter 230 is configured to count the number of oscillation signals within a fixed time width and output a pulse width adjustment signal via the output terminal.

In one embodiment, the oscillation control unit 210 is configured to output an effective oscillation enable signal after the oscillation start signal arrives, and output an ineffective oscillation enable signal after the oscillation stop signal arrives, and by controlling an interval between an arrival time of the oscillation start signal and an arrival time of the oscillation stop signal, a time for outputting the effective oscillation enable signal may be controlled, and an interval between the arrival time of the oscillation start signal and the arrival time of the oscillation stop signal is made to be a fixed time width, so that the effective time of the output oscillation enable signal may be made to be the fixed time width.

In the above technical solution, since the transistor process corner of the ring oscillator 220 is the same as the transistor process corner of the amplification module 200, the number of the oscillation signals generated by the ring oscillator 220 within the fixed time width is related to the process corner of the amplification module 200, and the oscillation counter 230 counts the number of the oscillation signals to generate the pulse width adjustment signal, so that the generation of the pulse width adjustment signal based on the transistor process corner can be realized, and the adjustment circuit performs the width adjustment on the first offset cancellation signal OC based on the pulse width adjustment signal.

In one embodiment, as shown in FIG. 6, ring oscillator 220 includes an odd number of first NAND gate circuits 221. Each first nand gate 221 has a first input terminal, a second input terminal, and an output terminal.

For each first nand gate 221, a first input end of the first nand gate 221 is connected to an output end of the first nand gate 221 located at the previous stage, an output end of the first nand gate 221 located at the next stage is connected to a first input end of the first nand gate 221 located at the next stage, and a first input end of the first nand gate 221 located at the first stage is connected to an output end of the first nand gate 221 located at the last stage, so that the ring oscillator 220 is finally formed. Second input ends of the odd number of first nand gates 221 are connected to the same node and then serve as a control end of the ring oscillator 220, and an output end of any one first nand gate 221 of the odd number of first nand gates 221 serves as an output end of the ring oscillator 220.

In the ring oscillator 220, when the oscillation enable signal is at a high level, the ring oscillator 220 outputs the oscillation signal, that is, the oscillation enable signal is at a high level. When the oscillation enable signal is at a low level, the ring oscillator 220 stops outputting the oscillation signal, i.e., the oscillation enable signal is active when the oscillation enable signal is at a low level.

When the time for generating the oscillation signals by the ring oscillator 220 is fixed, the number of the oscillation signals generated by the ring oscillator 220 is only related to the transistor process corner of the ring oscillator 220, and when the transistor process corner of the ring oscillator 220 is FF, the number of the oscillation signals generated by the ring oscillator 220 is larger, and when the transistor process corner of the ring oscillator 220 is SS, the number of the oscillation signals generated by the ring oscillator 220 is smaller.

In the above technical solution, if the time width of the oscillation enable signal at the high level is fixed, the time for the ring oscillator 220 to generate the oscillation signal is fixed, so that the number of oscillation signals generated by the ring oscillator 220 is only related to the transistor process corner, and the pulse width adjustment of the first offset cancellation signal OC based on the transistor process corner is realized by counting the number of oscillation signals and using the counted result as the pulse width adjustment signal.

In one embodiment, as shown in fig. 7, the oscillation control unit 210 includes a first not gate circuit 211, a second not gate circuit 212, and a second not gate circuit 213. The first not gate circuit 211 and the second not gate circuit 213 are each provided with an input terminal and an output terminal, and the second not gate circuit 212 is provided with a first input terminal, a second input terminal and an output terminal. A first input terminal of the second nand gate 212 receives the oscillation start signal Rin1, an input terminal of the first not gate 211 receives the oscillation stop signal Rin2, a second input terminal of the second nand gate 212 is connected to an output terminal of the first not gate 211, an input terminal of the second not gate 213 is connected to an output terminal of the second nand gate 212, and an output terminal of the second not gate 213 serves as an output terminal of the oscillation control unit 210.

As shown in fig. 8, the oscillation start signal Rin1 and the oscillation stop signal Rin2 are both active high pulse signals, and the rising edge of the oscillation start signal Rin1 is earlier than the rising edge of the oscillation stop signal Rin 2. When the oscillation start signal Rin1 is at a high level, the first input terminal of the second nand gate 212 is at a high level, the oscillation stop signal Rin2 is at a low level, and the oscillation stop signal Rin2 is at a high level, and outputs a high level after being inverted by the first nand gate 211, and the second input terminal of the second nand gate 212 is at a high level, and the output of the second nand gate 212 is at a low level, and outputs a high level after passing through the second nand gate 213, that is, outputs the active oscillation enable signal Ro. When the oscillation start signal Rin1 is still at the high level, the first input terminal of the second nand gate 212 is still at the high level, the oscillation stop signal Rin2 becomes the high level, and outputs the low level after the inversion operation by the first nand gate 211, the second input terminal of the second nand gate 212 is at the low level, the second nand gate 212 outputs the high level, and outputs the low level after the second nand gate 213, that is, outputs the invalid oscillation enable signal Ro.

The second nand gate 212 outputs the oscillation enable signal Ro that is active between the rising edge timing of the oscillation start signal Rin1 and the rising edge timing of the oscillation stop signal Rin2, and outputs the oscillation enable signal Ro that is inactive at any other timing. By making the interval between the rising edge timing of the oscillation start signal Rin1 and the rising edge timing of the oscillation end signal Rin2 a fixed time width, the effective time of the output oscillation enable signal Ro can be made a fixed time width.

In an embodiment, the pulse width adjustment amount of the first-stage adjustment sub-module 110, the pulse width adjustment amount of the second-stage adjustment sub-module 110, … …, and the pulse width adjustment amount of the nth-stage adjustment sub-module 110 are increased or decreased in an equal-ratio array, and the pulse width adjustment signal is output after counting the oscillation signal generated by the ring oscillator 220, so that when the transistor process angle is FF, the pulse width adjustment signal output can make the pulse width of the second offset cancellation signal OC' smaller.

In one embodiment, oscillation counter 230 has n outputs, and the n outputs of oscillation counter 230 are labeled as a first output, a second output, … …, and an nth output in order from a low count to a high count.

A first output terminal of the oscillation counter 230 is connected to the control terminal of the first-stage adjustment sub-module 110, a second output terminal of the oscillation counter 230 is connected to the control terminal of the second-stage adjustment sub-module 110, and so on, and an nth output terminal of the oscillation counter 230 is connected to the control terminal of the nth-stage adjustment sub-module 110.

If the first offset removal signal OC is an active high signal, the pulse width reduction of the first-stage adjustment sub-module 110, the pulse width reduction of the second-stage adjustment sub-module 110, … …, and the pulse width reduction of the nth-stage adjustment sub-module 110 are incremented in an equal ratio, and the oscillation counter 230 is a down counter.

For example: the first offset canceling signal OC is an active high signal, the adjusting circuit includes 3 adjusting sub-modules 110, and a pulse width reduction amount of the first-stage adjusting sub-module 110, a pulse width reduction amount of the second-stage adjusting sub-module 110, and a pulse width reduction amount of the third-stage adjusting sub-module 110 are Δ t, 2 Δ t, and 4 Δ t in sequence.

The transistor process corners are different, and the number of oscillation signals generated within a fixed time width is different. As shown in table 1, if the number of oscillation signals generated within a fixed time width is 0, the pulse width adjustment signal is 111, and if the three adjustment submodules 110 do not perform pulse width adjustment, the total pulse adjustment amount of the adjustment circuit is 0.

If the number of the oscillation signals generated within the fixed time width is 7, the pulse width adjustment signal is 000, the first-stage adjustment sub-module 110 performs pulse width reduction processing on the first offset cancellation signal OC, the reduction amount is- Δ t, the second-stage adjustment sub-module 110 performs pulse width reduction processing on the output signal of the first-stage adjustment sub-module 110, the reduction amount is-2 Δ t, the third-stage adjustment sub-module 110 performs pulse width reduction processing on the output signal of the second-stage adjustment sub-module 110, the reduction amount is-4 Δ t, and then the total pulse adjustment amount of the adjustment circuit is-7 Δ t.

TABLE 1 first relation table

Number of oscillation signals	Pulse width adjusting signal	Total pulse adjustment of the adjusting circuit
			0	111	0
1	110	-△t
			2	101	-2△t
3	100	-3△t
			4	011	-4△t
5	010	-5△t
			6	001	-6△t
7	000	-7△t

If the first offset cancellation signal OC is an active low signal, the pulse width increment of the first-stage adjustment submodule 110, the pulse width increment of the second-stage adjustment submodule 110, … …, and the pulse width increment of the nth-stage adjustment submodule 110 are incremented in an equal-ratio sequence, and the oscillation counter 230 is an up counter.

For example: the first offset canceling signal OC is an active low signal, the adjusting circuit includes 3 adjusting sub-modules 110, and the pulse width increment of the first-stage adjusting sub-module 110, the pulse width increment of the second-stage adjusting sub-module 110, and the pulse width increment of the third-stage adjusting sub-module 110 are Δ t, 2 Δ t, and 4 Δ t in sequence.

As shown in table 2, if the number of oscillation signals generated within the fixed time width is 0, the pulse width adjustment signal is 000, the first-stage adjustment sub-module 110 performs the pulse width increasing process on the output first offset canceling signal OC by an amount Δ t, the second-stage adjustment sub-module 110 performs the pulse width increasing process on the output signal of the first-stage adjustment sub-module 110 by an amount 2 Δ t, and the third-stage adjustment sub-module 110 performs the pulse width increasing process on the output signal of the first-stage adjustment sub-module 110 by an amount 4 Δ t, then the total pulse adjustment amount of the adjustment circuit is 7 Δ t.

TABLE 2 second relation table

Number of oscillation signals	Pulse width adjusting signal	Total pulse adjustment of the adjusting circuit
			0	000	+7△t
1	001	+6△t
			2	010	+5△t
3	011	+4△t
			4	100	+3△t
5	101	+2△t
			6	110	+△t
7	111	+0

In the above technical solution, if the first offset cancellation signal is an active high signal, the oscillation counter is a down counter, and if the first offset cancellation signal is an active low signal, the oscillation counter is an up counter, so that when the transistor process corner is FF, the larger the number of the oscillation signals is, the smaller the pulse width of the second offset cancellation signal OC' can be made by the output pulse width adjustment signal.

With continued reference to fig. 2, another embodiment of the present application provides a sense amplifier that includes a control module 100 and an amplification module 200. The amplification block 200 includes a first P-type transistor P1, a second P-type transistor P2, a first N-type transistor N1, and a second N-type transistor N2.

The source of the first P-type transistor P1 is coupled to the first power source terminal VCC, the gate of the first P-type transistor P1 is connected to the drain of the second P-type transistor P2, the source of the second P-type transistor P2 is connected to the source of the first P-type transistor P1, and the gate of the second P-type transistor P2 is connected to the drain of the first P-type transistor P1.

The drain of the first N-type transistor N1 is connected to the drain of the first P-type transistor P1 and then to the complementary sensing bit line SABLB, the gate of the first N-type transistor N1 is connected to the bit line BL, and the source of the first N-type transistor N1 is coupled to the second power supply terminal VSS. The drain of the second N-type transistor N2 is connected to the drain of the second P-type transistor P2 and then to the sense bit line SABL, the gate of the second N-type transistor N2 is connected to the complementary bit line BLB, and the source of the second N-type transistor N2 is connected to the source of the first N-type transistor N1.

In one embodiment, the amplifying module 200 further includes a third N-type transistor N3 and a fourth N-type transistor N4. The drain of the third N-type transistor N3 is connected to the drain of the first N-type transistor N1, the source of the third N-type transistor N3 is connected to the gate of the first N-type transistor N1, and the gate of the third N-type transistor N3 is connected to the output terminal of the control module 100. The drain of the fourth N-type transistor N4 is connected to the drain of the second N-type transistor N2, the source of the fourth N-type transistor N4 is connected to the gate of the second N-type transistor N2, and the gate of the fourth N-type transistor N4 is connected to the output terminal of the control module 100.

In one embodiment, the amplifying module 200 further includes a fifth N-type transistor N5 and a sixth N-type transistor N6, wherein a drain of the fifth N-type transistor N5 is connected to a drain of the second N-type transistor N2, a source of the fifth N-type transistor N5 is connected to a gate of the first N-type transistor N1, and a gate of the fifth N-type transistor N5 is configured to receive the precharge signal ISO. The drain of the sixth N-type transistor N6 is connected to the drain of the first N-type transistor N1, the source of the sixth N-type transistor N6 is connected to the gate of the second N-type transistor N2, and the gate of the sixth N-type transistor N6 is used for receiving the precharge signal ISO.

In an embodiment, the source of the first P-type transistor P1 is coupled to the first power source terminal VCC, and the source of the first P-type transistor P1 is directly connected to the first power source terminal VCC, and the power module controls whether the first power source terminal VCC supplies power to the sense amplifier.

In one embodiment, the amplifying module 200 further includes a third P-type transistor P3, wherein the source of the first P-type transistor P1 is coupled to the first power terminal VCC, and the source of the first P-type transistor P1 is connected to the first power terminal VCC through the third P-type transistor P3. The source of the third P-type transistor P3 is connected to the first power supply terminal VCC, and the drain of the third P-type transistor P3 is connected to the source of the first P-type transistor P1. The first power terminal VCC is controlled by the third P-type transistor P3 to supply power to the sense amplifier.

In one embodiment, the source of the first N-type transistor N1 is coupled to the second power source terminal VSS, and the source of the first N-type transistor N1 is directly connected to the second power source terminal VSS, and the power module controls whether the second power source terminal VSS supplies power to the sense amplifier.

In one embodiment, the amplifying module 200 further includes a seventh N-type transistor N7, wherein the source of the first N-type transistor N1 is coupled to the second power source terminal VSS, and wherein the source of the first N-type transistor N1 is connected to the second power source terminal VSS through the seventh N-type transistor N7. The source of the seventh N-type transistor N7 is connected to the second power source terminal VSS, the drain of the seventh N-type transistor N7 is connected to the source of the first N-type transistor N1, and the seventh N-type transistor N7 controls the second power source terminal VSS to supply power to the sense amplifier.

As shown in fig. 9, at time t0 to t1, in the precharge phase, the precharge signal ISO and the second offset cancel signal OC' are both active, the fifth N-type transistor N5 and the sixth N-type transistor N6 are both turned on, the bit line BL is connected to the sense bit line SABL, and the complementary bit line BLB is connected to the complementary sense bit line SABLB. The third N-type transistor N3 and the fourth N-type transistor N4 are turned on, and the bit line BL, the sense bit line SABL, the complementary bit line BLB, and the complementary sense bit line SABLB are connected to each other. The first power signal SAP and the second power signal SAN are in an inactive state, the third P-type transistor P3 and the seventh N-type transistor N7 are turned off, and the first power terminal VCC and the second power terminal VSS are turned off from the sense amplifier. The voltages of bit line BL, complementary bit line BLB, sense bit line SABL, and complementary sense bit line SABLB are pulled to a charged value by a charging module.

At time t1 to time t2, the precharge signal ISO is in an inactive state, the second offset cancel signal OC' is in an active state, the third N-type transistor N3 and the fourth N-type transistor N4 are turned on, and the first N-type transistor N1 and the second N-type transistor N2 are diode-connected. The first power signal SAP and the second power signal SAN are in an active state, the third P-type transistor P3 and the seventh N-type transistor N7 are turned on, and the first power terminal VCC and the second power terminal VSS are turned on with the sense amplifier. The compensation voltage Vos is generated on the bit line BL and the complementary bit line BLB, and the compensation voltage Vos is generated on the sense bit line SABL and the complementary sense bit line SABLB.

At time t2 to time t3, in the voltage sharing stage, the precharge signal ISO and the second offset cancel signal OC' are both in an inactive state, the third N-type transistor N3 and the fourth N-type transistor N4 are turned off, the fifth N-type transistor N5 and the sixth N-type transistor N6 are turned off, the first power signal SAP and the second power signal SAN are in an inactive state, and the third P-type transistor P3 and the seventh N-type transistor N7 are turned off. The word line signal WL is asserted and the memory cell shares charge with either the bit line BL or the complementary bit line BLB, presenting a data voltage difference across the bit line BL and the complementary bit line BLB.

At time t3 to time t4, in the pre-read stage, the pre-charge signal ISO and the second offset cancellation signal OC' are both inactive, the third N-type transistor N3 and the fourth N-type transistor N4 are turned off, the fifth N-type transistor N5 and the sixth N-type transistor N6 are turned off, the first power signal SAP and the second power signal SAN are active, and the third P-type transistor P3 and the seventh N-type transistor N7 are turned on. The first power terminal VCC pulls the voltages of the sensing bit line SABL and the complementary sensing bit line SABLB based on the difference between the data voltages on the bit line BL and the complementary sensing bit line BLB, and since the compensation voltage Vos is already stored on the sensing bit line SABL and the complementary sensing bit line SABLB, the compensation voltage Vos can cancel noise caused by the manufacturing difference between the first N-type transistor N1 and the second N-type transistor N2 in the sense amplifier at the time t3 to t4, and data can be accurately represented on the sensing bit line SABL and the complementary sensing bit line SABLB.

At time t4 to time t5, in the recovery stage, the precharge signal ISO is in an active state, the second offset canceling signal OC' is in an inactive state, the third N-type transistor N3 and the fourth N-type transistor N4 are turned off, the fifth N-type transistor N5 and the sixth N-type transistor N6 are turned on, the bit line BL voltage is pulled by the sense bit line SABL, and the complementary bit line BLB voltage is pulled by the complementary sense bit line SABLB to recover the charges stored in the memory cell.

The pulse width of the second offset canceling signal OC 'is obtained by determining a length of a time period between a falling edge time of the first offset canceling signal OC and a falling edge time of the precharge signal according to design parameters of respective transistors within the amplification block 200, and performing pulse width adjustment on the first offset canceling signal OC based on a transistor process corner, and a time period between the falling edge time of the precharge signal ISO to the falling edge time of the second offset canceling signal OC' is a time tOC 'at which the compensation voltage Vos is generated on the sense bit line SABL and the complementary sense bit line SABLB, and thus, a time tOC' at which the compensation voltage Vos is generated is adaptively adjusted based on the transistor process corner speed.

The smaller the pulse width of the second offset canceling signal OC ', the shorter the time tOC' for generating the compensating voltage Vos, and the shorter the on-time of the third N-type transistor N3 and the fourth N-type transistor N4, and at this time, the stronger the driving capability of the third N-type transistor N3 and the fourth N-type transistor N4, so that the shorter the on-time of the third N-type transistor N3 and the fourth N-type transistor N4, the excessive compensating voltage Vos generated on the read bit line SABL and the read complementary bit line BLB by the first N-type transistor N1 and the second N-type transistor N2 can be prevented.

The transistor process corner SS is defined as SS, the larger the pulse width of the second offset cancel signal OC ', the longer the time tOC' for generating the compensation voltage Vos, and the longer the on-time of the third N-type transistor N3 and the fourth N-type transistor N4, and at this time, the weaker the driving capability of the third N-type transistor N3 and the fourth N-type transistor N4, so that the first N-type transistor N1 and the second N-type transistor N2 can generate the appropriate compensation voltage Vos on the read bit line SABL and the complementary read bit line SABLB by prolonging the on-time of the third N-type transistor N3 and the fourth N-type transistor N4.

In the above technical solution, by adjusting the pulse width of the second offset cancellation signal OC' received by the gates of the third N-type transistor N3 and the fourth N-type transistor N4, the on-time of the third N-type transistor N3 and the fourth N-type transistor N4 can be adjusted, different transistor driving capabilities caused by transistor process corners can be compensated, so that an appropriate compensation voltage Vos is generated on the sensing bit line SABL and the complementary sensing bit line SABLB, noise introduced by transistor manufacturing differences is effectively cancelled, and introduction of new noise is avoided.

Other embodiments of the present application will be apparent to those skilled in the art from consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of the invention following, in general, the principles of the application and including such departures from the present disclosure as come within known or customary practice within the art to which the invention pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the application being indicated by the following claims.

It will be understood that the present application is not limited to the precise arrangements described above and shown in the drawings and that various modifications and changes may be made without departing from the scope thereof. The scope of the application is limited only by the appended claims.

Claims

1. A sense amplifier, comprising:

2. The sense amplifier of claim 1, wherein the control module comprises:

and the control end of the adjusting circuit is connected with the output end of the parameter generating circuit, the input end of the adjusting circuit receives the first offset cancellation signal, the pulse width of the first offset cancellation signal is adjusted according to the pulse width adjusting signal received by the control end of the adjusting circuit, and the second offset cancellation signal is output.

3. The sense amplifier of claim 2, wherein the parameter generation circuit comprises:

and the input end of the oscillation counter is connected with the output end of the ring oscillator, and the oscillation counter is used for counting the number of the oscillation signals within the fixed time width and outputting the pulse width adjusting signal.

4. The sense amplifier of claim 3, wherein the transistor process corner of the ring oscillator and the transistor process corner of the amplification block are the same, and the number of oscillation signals generated within the fixed time width is determined by the transistor process corner of the ring oscillator.

5. The sense amplifier of claim 3 or 4, wherein the ring oscillator comprises an odd number of first NAND gates;

for each first NAND gate circuit, a first input end of the first NAND gate circuit is connected with an output end of the first NAND gate circuit positioned at the previous stage, an output end of the first NAND gate circuit positioned at the next stage is connected with a first input end of the first NAND gate circuit positioned at the next stage, and a first input end of the first NAND gate of the first stage is connected with an output end of the first NAND gate of the last stage;

second input ends of the odd number of first NAND gate circuits are connected to the same node, and the node is used as a control end of the ring oscillator; and the output end of any one first NAND gate circuit is used as the output end of the ring oscillator.

6. The sense amplifier of claim 3 or 4, wherein the oscillation control unit is configured to output an active oscillation enable signal after the oscillation start signal arrives and an inactive oscillation enable signal after the oscillation stop signal arrives.

7. The sense amplifier of claim 6, wherein the oscillation control unit comprises:

a first not gate circuit, an input end of which receives the oscillation termination signal; the output end of the first NAND gate circuit is connected with the first input end of the first NAND gate circuit;

8. The sense amplifier of any of claims 2 to 4, wherein the parameter generating circuit comprises a plurality of output terminals, the pulse width adjusting signal comprises a plurality of pulse width adjusting sub-signals, and the output terminals of the parameter generating circuit respectively output the pulse width adjusting sub-signals;

the first-stage adjusting sub-module receives the first offset cancellation signal and is used for adjusting the pulse of the first offset cancellation signal according to the received pulse width adjusting sub-signal;

the rest of each level of the adjusting sub-modules receive the output signal of the previous level of the adjusting sub-module, and adjust the pulse of the output signal of the previous level of the adjusting sub-module according to the pulse width adjusting sub-signal received by the control end of the adjusting sub-module; and the output signal of the adjusting submodule at the last stage is the second offset eliminating signal.

9. The sense amplifier of claim 8, wherein each of the adjustment submodules comprises:

and the first input end of the AND gate circuit is connected with the input end of the delay unit, the second input end of the AND gate circuit is connected with the output end of the OR gate circuit, and the output end of the AND gate circuit is used as the output end of the adjusting submodule.

10. The sense amplifier of claim 8, wherein;

if the first offset cancellation signal is a high-level effective signal, the oscillation counter is a down counter;

11. The sense amplifier of any of claims 1 to 4, wherein the amplifying module comprises:

a second P-type transistor, the source of which is connected with the source of the first P-type transistor, and the gate of which is connected with the drain of the first P-type transistor;

a first N-type transistor, wherein the drain electrode of the first N-type transistor is connected with the drain electrode of the first P-type transistor and then connected with a complementary reading bit line, the grid electrode of the first N-type transistor is connected with the bit line, and the source electrode of the first N-type transistor is coupled with a second power supply end;

a second N-type transistor, the drain of which is connected with the drain of the second P-type transistor and then connected with the read bit line, the grid of which is connected with the complementary bit line, and the source of which is connected with the source of the first N-type transistor;

a third N-type transistor, the drain of which is connected with the drain of the first N-type transistor, and the source of which is connected with the bit line; the grid electrode of the first offset cancellation signal is conducted when receiving the second offset cancellation signal;

a fourth N-type transistor, the drain of which is connected to the drain of the second N-type transistor, and the source of which is connected to the complementary bit line; the gate of which is turned on when receiving the second offset canceling signal.

12. The sense amplifier of claim 11, wherein a process corner of the third N-type transistor, a process corner of the fourth N-type transistor, and a transistor process corner of a ring oscillator are the same.

13. The sense amplifier of claim 11, wherein the amplification module further comprises:

a fifth N-type transistor, wherein the drain of the fifth N-type transistor is connected to the drain of the second N-type transistor, the source of the fifth N-type transistor is connected to the bit line, and the gate of the fifth N-type transistor is used for receiving a pre-charge signal and is used for conducting under the control of the pre-charge signal;

a sixth N-type transistor having a drain connected to the drain of the first N-type transistor and a source connected to the complementary bit line; the gate of which is used to receive a pre-charge signal, which is used to conduct under the control of the pre-charge signal.

14. The sense amplifier of claim 13, wherein a length of a time period between a falling edge time of the first offset cancellation signal and a falling edge time of the precharge signal is preset.

15. The sense amplifier of claim 11, wherein the amplification module further comprises: