WO2024000640A1 - Sense amplifier and semiconductor memory - Google Patents

Abstract

Provided in the present disclosure are a sense amplifier and a semiconductor memory. The sense amplifier comprises a control module provided with an input end and an output end and an amplification module. The control module is configured to acquire temperature data of the amplification module, perform pulse width adjustment on a first offset cancellation signal received at the input end thereof according to the temperature data of the amplification module, and generate and output a second offset cancellation signal. The amplification module has a control end connected to the output end of the control module, and is configured to cancel a noise signal of the amplification module under the control of the second offset cancellation signal. The above arrangement can compensate for the defect that a transistor in the amplification module changes with a change in the temperature, such that a complementary voltage of an appropriate magnitude is generated on a bit line and a complementary bit line, thereby accurately cancelling a noise signal in the amplification module, and improving the accuracy of the sense amplifier.

Description

Sensitive amplifiers and semiconductor memories

This disclosure claims priority to the Chinese patent application filed with the China Patent Office on June 30, 2022, with application number 202210760106.6 and the application name "Sensitive Amplifier and Semiconductor Memory", the entire content of which is incorporated into this disclosure by reference.

Technical field

The present disclosure relates to, but is not limited to, a sense amplifier and a semiconductor memory.

Background technique

As the line width of the semiconductor memory shrinks, the capacitance value of the memory cell in the semiconductor memory decreases, making the impact of noise on the normal operation of the semiconductor memory greater.

The sense amplifier can eliminate noise caused by manufacturing differences in transistors in semiconductor memory, so that semiconductor memory can accurately store data. When the sensitive amplifier works in the offset elimination stage, a compensation voltage is formed on the readout bit line and the complementary readout bit line. The size of the compensation voltage will affect the noise elimination effect.

Therefore, how to generate appropriate compensation voltages on bit lines and complementary bit lines is crucial to semi-eliminating noise in semiconductor memories.

Contents of the invention

The present disclosure provides a sensitive amplifier, including:

A control module, which is provided with an input terminal and an output terminal, is used to obtain the temperature data of the amplification module, adjust the pulse width of the first offset cancellation signal received at the input terminal according to the temperature data of the amplification module, and generate and output a second offset cancellation signal;

The control end of the amplification module is connected to the output end of the control module, and is used to eliminate the noise signal of the amplification module under the control of the second offset cancellation signal.

In some embodiments, the control module includes:

A pulse width parameter unit, which is provided with an output terminal and is used to generate a pulse width adjustment signal according to the temperature data of the amplification module;

The adjustment unit is provided with an input end, an output end and a control end. The control end is connected to the output end of the pulse width parameter unit. The input end receives the first offset elimination signal and eliminates the first offset according to the pulse width adjustment signal. The signal undergoes pulse width adjustment processing and a second offset cancellation signal is output.

In some embodiments, the pulse width parameter unit includes three output terminals, the pulse width adjustment signal includes three strobe signals, and the adjustment unit includes:

The first adjustment subunit, the output end of which is connected to the first input end of the selection unit, is used to perform pulse width adjustment on the first offset cancellation signal and output a third offset cancellation signal;

The second adjustment subunit, the output end of which is connected to the second input end of the selection unit, is used to perform pulse width adjustment on the first offset cancellation signal and output a fourth offset cancellation signal;

The third adjustment subunit, the output end of which is connected to the third input end of the selection unit, is used to perform pulse width adjustment on the first offset cancellation signal and output a fifth offset cancellation signal; wherein, the pulse of the third offset cancellation signal The width, the pulse width of the fourth offset cancellation signal and the pulse width of the fifth offset cancellation signal are all different;

The selection unit is provided with three control terminals, each control terminal is connected to the corresponding output terminal of the pulse width parameter unit, and receives the corresponding strobe signal; used to eliminate the signal from the third offset under the control of the three strobe signals. , select one of the fourth offset cancellation signal and the fifth offset cancellation signal to output, and the output signal of the selection unit is used to control the noise signal cancellation of the amplification module.

In some embodiments, the adjustment unit further includes:

The input terminal of the inverter is connected to the output terminal of the selection unit, and its output signal is used to control and eliminate the noise signal of the amplification module.

In some embodiments, the first regulating subunit includes:

A first delay circuit, the input end of which receives the first offset cancellation signal, is used to delay the first offset cancellation signal and output the first delay signal;

The first AND gate has a first input terminal that receives the first offset cancellation signal, a second input terminal that is connected to the output terminal of the first delay circuit to receive the first delay signal, and an output terminal that outputs a third offset cancellation signal.

In some embodiments, the first delay circuit includes:

A first access line, one end of which serves as the output end of the first delay circuit, and the other end of which receives the first offset cancellation signal;

The first P-type transistor has its gate connected to the first access line, its drain connected to its source and then connected to the first power terminal;

The first N-type transistor has its gate connected to the first access line, its drain connected to its source and then connected to the second power terminal.

In some embodiments, the second regulating subunit includes:

A second delay circuit, whose input terminal receives the first offset cancellation signal, is used to delay the first offset cancellation signal and output a second delay signal; and the delay amount of the second delay circuit for delay processing is greater than that of the first delay circuit The amount of delay for deferred processing;

The second AND gate has a first input terminal that receives the first offset cancellation signal, a second input terminal that is connected to the output terminal of the second delay circuit to receive the second delay signal, and an output terminal that outputs a fourth offset cancellation signal.

In some embodiments, the second delay circuit includes:

a second access line, one end of which serves as the output end of the second delay circuit, and the other end of which receives the first offset cancellation signal;

The second P-type transistor has its gate connected to the second access line, its drain connected to its source and then connected to the first power terminal;

The second N-type transistor has a gate connected to the second access line, a drain connected to its source and then connected to the second power terminal;

The third P-type transistor has its gate connected to the second access line, its drain connected to its source and then connected to the first power terminal;

The third N-type transistor has its gate connected to the second access line, its drain connected to its source and then connected to the second power terminal.

In some embodiments, the third regulatory subunit includes:

A third delay circuit whose input terminal receives the first offset cancellation signal is used to delay the first offset cancellation signal and output a third delay signal; and the delay amount of the third delay circuit for delay processing is greater than that of the second delay circuit The amount of delay for deferred processing;

The third AND gate has a first input terminal that receives the first offset cancellation signal, a second input terminal that is connected to the output terminal of the third delay circuit to receive the third delay signal, and an output terminal that outputs a fifth offset cancellation signal.

In some embodiments, the third delay circuit includes:

A third access line, one end of which serves as the output end of the third delay circuit, and the other end of which receives the first offset cancellation signal;

The fourth P-type transistor has its gate connected to the third access line, its drain connected to its source and then connected to the first power terminal;

The fourth N-type transistor has its gate connected to the third access line, its drain connected to its source and then connected to the second power terminal;

The fifth P-type transistor has its gate connected to the third access line, its drain connected to its source and then connected to the first power terminal;

The fifth N-type transistor has its gate connected to the third access line, its drain connected to its source and then connected to the second power terminal;

The sixth P-type transistor has its gate connected to the third access line, its drain connected to its source and then connected to the first power terminal;

The sixth N-type transistor has its gate connected to the third access line, its drain connected to its source and then connected to the second power terminal.

In some embodiments, the pulse width parameter unit includes:

A temperature sensor, which is used to detect the temperature data of the amplification module and generate temperature coded data based on the temperature data;

A temperature decoder, whose input terminal is connected to the output terminal of the temperature sensor, is used to generate a pulse width adjustment signal based on the temperature encoded data.

In some embodiments, the pulse width parameter unit is used to:

When the temperature data is within the first temperature range, the output first strobe signal is a valid value, and the output second strobe signal and third strobe signal are invalid values; the control selection unit selects the third offset elimination signal output ;

When the temperature data is within the second temperature range, the output second strobe signal is a valid value, and the output first strobe signal and third strobe signal are invalid values; the control selection unit selects the fourth offset cancellation signal output ;

When the temperature data is within the third temperature range, the output third strobe signal is a valid value, and the output first strobe signal and second strobe signal are invalid values; the control selection unit selects the fifth offset cancellation signal output ;

Wherein, the upper limit value of the first temperature range is less than or equal to the lower limit value of the second temperature range, and the upper limit value of the second temperature range is less than or equal to the lower limit value of the third temperature range; the pulse of the third offset cancellation signal The width is smaller than the pulse width of the fourth offset cancellation signal, and the pulse width of the fourth offset cancellation signal is smaller than the pulse width of the fifth offset cancellation signal.

In some embodiments, the amplification module includes:

The seventh P-type transistor has its source connected to the source of the eighth P-type transistor, and its gate connected to the drain of the eighth P-type transistor;

The gate of the eighth P-type transistor is connected to the drain of the seventh P-type transistor;

The seventh N-type transistor has its drain connected to the drain of the seventh P-type transistor, its source connected to the source of the eighth N-type transistor, and its gate connected to the bit line;

The drain of the eighth N-type transistor is connected to the drain of the eighth P-type transistor, and the gate thereof is connected to the complementary bit line;

The ninth N-type transistor has a first end connected to the bit line, a second end connected to the drain of the seventh N-type transistor, and its gate serves as the control end of the amplification module;

The second end of the tenth N-type transistor is connected to the complementary bit line, the first end is connected to the drain of the eighth N-type transistor, and its gate serves as the control end of the amplification module.

In some embodiments, the amplification module includes:

The eleventh N-type transistor has its first end connected to the bit line, its second end connected to the drain of the eighth N-type transistor, and its gate receives the isolation control signal;

The second end of the twelfth N-type transistor is connected to the complementary bit line, the first end is connected to the drain of the seventh N-type transistor, and its gate receives the isolation control signal.

In some embodiments, the amplification module includes:

The ninth P-type transistor has its source connected to the third power terminal and its drain connected to the source of the seventh P-type transistor;

The source of the thirteenth N-type transistor is connected to the fourth power supply terminal, and the drain is connected to the source of the seventh N-type transistor.

An embodiment of the present disclosure provides a semiconductor memory, including the sense amplifier involved in the above embodiment.

The present disclosure provides a sensitive amplifier and a semiconductor memory. The sensitive amplifier includes a control module and an amplification module. The control module is used to adjust the pulse width of the first offset cancellation signal according to the temperature data of the amplification module to compensate for the changes of the transistors in the amplification module. The changing conditions due to temperature changes generate a compensation voltage of appropriate size on the bit line and the complementary bit line, accurately eliminating the mismatch error of the transistor and improving the accuracy of the sensitive amplifier.

Description of drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the disclosure and together with the description, serve to explain the principles of the disclosure.

Figure 1 is a schematic circuit diagram of a sensitive amplifier;

Figure 2A is a working principle diagram of the sensitive amplifier shown in Figure 1 in the offset elimination stage;

Figure 2B is another working principle diagram of the sensitive amplifier shown in Figure 1 in the offset elimination stage;

Figure 2C is another working principle diagram of the sensitive amplifier shown in Figure 1 in the offset elimination stage;

Figure 3 is a schematic circuit diagram of a sense amplifier provided by an embodiment of the present disclosure;

Figure 4 is a schematic circuit diagram of a control module provided by another embodiment of the present disclosure;

Figure 5 is a schematic circuit diagram of the first adjustment subunit provided by yet another embodiment of the present disclosure;

Figure 6 is a schematic diagram of the working principle of the first adjustment subunit in the embodiment shown in Figure 5;

Figure 7 is a schematic circuit diagram of a second adjustment subunit provided by yet another embodiment of the present disclosure;

Figure 8 is a schematic diagram of the working principle of the second adjustment subunit in the embodiment shown in Figure 7;

Figure 9 is a schematic circuit diagram of a third adjustment subunit provided by yet another embodiment of the present disclosure;

Figure 10 is a schematic diagram of the working principle of the third adjustment subunit in the embodiment shown in Figure 9;

FIG. 11 is a timing diagram of a sense amplifier provided by an embodiment of the present disclosure.

Reference signs:

200. Control module; 100. Amplification module; 220. Pulse width parameter unit; 210. Adjustment unit; 211. First adjustment subunit; 212. Second adjustment subunit; 213. Third adjustment subunit; 214. Selection unit ; 215. Inverter; 221. Temperature sensor; 222. Temperature decoder; 311. First AND gate; 321. First delay circuit; 331. First access line; 312. Second AND gate; 322. Second delay circuit; 332, second access line; 313, third AND gate; 323, third delay circuit; 333, third access line.

Specific embodiments of the present disclosure have been shown through the above-mentioned drawings and will be described in more detail below. These drawings and written description are not intended to limit the scope of the disclosed concepts in any way, but rather to illustrate the concepts of the present disclosure to those skilled in the art with reference to the specific embodiments.

Detailed ways

Exemplary embodiments will be described in detail herein, examples of which are illustrated in the accompanying drawings. When the following description refers to the drawings, the same numbers in different drawings refer to the same or similar elements unless otherwise indicated. The implementations described in the following exemplary embodiments do not represent all implementations consistent with the present disclosure. Rather, they are merely examples of apparatus and methods consistent with aspects of the disclosure as detailed in the appended claims.

As shown in Figure 1, a sense amplifier includes an amplification module 100. The amplification module 100 includes a seventh P-type transistor P7, an eighth P-type transistor P8, a seventh N-type transistor N7 and an eighth N-type transistor N8.

Among them, after the source of the seventh P-type transistor P7 and the source of the eighth P-type transistor P8 are connected, they serve as the first terminal LA of the amplification module 100, and the source of the seventh N-type transistor N7 and the eighth N-type transistor N8 After the source is connected, it serves as the second terminal LAB of the amplification module 100. The gate of the seventh P-type transistor P7 is connected to the drain of the eighth P-type transistor P8, and the gate of the eighth P-type transistor P8 is connected to the drain of the seventh P-type transistor P7. The drain of the seventh P-type transistor P7 is connected to the drain of the seventh N-type transistor N7 and then connected to the complementary readout bit line SABLB. The drain of the eighth P-type transistor P8 is connected to the drain of the eighth N-type transistor N8, and then connected to the readout bit line SABL. The gate of the seventh N-type transistor N7 is connected to the bit line BL, and the gate of the eighth N-type transistor N8 is connected to the readout bit line SABL. pole is connected to the complementary bit line BLB.

The amplification module 100 also includes a ninth N-type transistor N9 and a tenth N-type transistor N10. The first terminal of the ninth N-type transistor N9 is connected to the bit line, and the second terminal of the ninth N-type transistor N9 is connected to the drain of the seventh N-type transistor N7. The second terminal of the tenth N-type transistor N10 is connected to the complementary bit line BLB, and the first terminal of the tenth N-type transistor N10 is connected to the drain of the eighth N-type transistor N8.

The amplification module 100 also includes an eleventh N-type transistor N11 and a twelfth N-type transistor N12. The first terminal of the eleventh N-type transistor N11 is connected to the bit line BL, and the second terminal of the eleventh N-type transistor N11 is connected to the drain of the eighth N-type transistor N8. The first terminal of the twelfth N-type transistor N12 is connected to the drain of the seventh N-type transistor N7, and the second terminal of the twelfth N-type transistor N12 is connected to the complementary bit line BLB.

In the offset elimination phase T2, the ninth N-type transistor N9 and the tenth N-type transistor N10 are both turned on, the seventh N-type transistor N7 and the eighth N-type transistor N8 both work in the diode state, and the bit line BL and the complementary bit A compensation voltage Vos is generated on the line BLB, and a compensation voltage Vos is also generated on the sense bit line SABL and the complementary sense bit line SABLB.

Since the compensation voltage Vos already exists on the sense bit line SABL and the complementary sense bit line SABLB, during the sensing amplification stage, the compensation voltage Vos can offset the noise signal of the amplification module 100, and the compensation voltage Vos can be accurately detected on the bit line BL and the complementary bit line BLB. Present data.

In the recovery phase, the eleventh N-type transistor N11 and the twelfth N-type transistor N12 are both turned on, the bit line BL is connected to the read bit line SABL, and the complementary bit line BLB is connected to the complementary read bit line SABLB to realize the storage operation. In-unit data recovery.

The size of the compensation voltage Vos will affect the noise elimination effect. If the compensation voltage Vos is too large or the compensation voltage Vos is too small, the noise signal of the amplifier module 100 cannot be accurately eliminated. The size of the compensation voltage Vos is related to the pulse width of the offset cancellation signal. When the pulse width of the offset cancellation signal of the amplification module 100 is larger, a larger compensation voltage Vos can be formed on the sense bit line SABL and the complementary sense bit line SABLB. When the pulse width of the offset cancellation signal of the amplification module 100 is smaller, the compensation voltage Vos formed on the sense bit line SABL and the complementary sense bit line SABLB is smaller. Therefore, in the design stage of the sense amplifier, it is necessary to design a suitable pulse width of the offset cancellation signal to form a suitable compensation voltage Vos on the bit line BL and the complementary bit line BLB.

However, the drive capability of the sense amplifier also changes when the temperature of the sense amplifier changes. As shown in Figure 2A, when the temperature of the sense amplifier is moderate, the voltage driving capability of the sense amplifier is also moderate, and a compensation voltage Vos of appropriate size can be generated on the bit BL line and the complementary bit line BLB. As shown in FIG. 2B , when the temperature of the sensitive amplifier becomes high, the voltage driving capability of the transistor in the amplification module 100 becomes weaker, and the compensation voltage Vos formed during the offset elimination stage T2 becomes smaller, and the noise signal of the amplification module 100 cannot be eliminated. . As shown in FIG. 2C , when the temperature of the sensitive amplifier is relatively low, the voltage driving capability of the transistor in the amplification module 100 is strong, and the compensation voltage Vos formed during the offset elimination stage T2 becomes larger, which will introduce new noise.

In order to more accurately form a compensation voltage Vos of appropriate size on the sense bit line SABL and the complementary sense bit line SABLB, the present disclosure provides a sensitive amplifier and a semiconductor memory, including an amplification module 100 and a control module 200. The control module 200 is based on The temperature data of the amplification module 100 adjusts the pulse width of the offset cancellation signal to compensate for changes in the voltage driving capabilities of the transistors in the amplification module 100, so as to generate a compensation voltage Vos of appropriate size on the bit line BL and the complementary bit line BLB to accurately eliminate Amplifying the noise signal of the module 100 improves the accuracy of the sensitive amplifier.

As shown in Figure 3, an embodiment of the present disclosure provides a sensitive amplifier, which includes a control module 200 and an amplification module 100. The amplification module 100 is provided with a control terminal, and the control module 200 is provided with an input terminal and an output terminal. The control terminal of the amplification module 100 is connected to the output terminal of the control module 200 .

The input end of the control module 200 receives the first offset cancellation signal OC1. The control module 200 is used to obtain the temperature data of the amplification module 100, and perform pulse width adjustment on the first offset cancellation signal OC1 according to the temperature data of the amplification module 100 to generate a third two offset cancellation signals OC2, and the second offset cancellation signal OC2 is output from its output terminal. The amplification module 100 is used to eliminate the noise signal of the amplification module 100 under the control of the second offset cancellation signal OC2.

When the temperature data of the amplification module 100 becomes larger, the pulse width of the second offset cancellation signal OC2 output by the control module 200 is relatively large to compensate for the change in the voltage driving capability of the amplification module 100 as its temperature increases. Weak situation, in order to achieve a suitable size of the compensation voltage Vos on the bit line BL and the complementary bit line BLB.

When the temperature data of the amplification module 100 becomes smaller, the pulse width of the second offset cancellation signal OC2 output by the control module 200 is relatively small to compensate for the voltage driving capability of the amplification module 100 becoming stronger as its temperature decreases. situation to generate a compensation voltage Vos of appropriate magnitude on the bit line BL and the complementary bit line BLB.

In the above technical solution, the sensitive amplifier includes a control module 200 and an amplification module 100. The control module 200 is used to adjust the pulse width of the first offset cancellation signal OC1 according to the temperature data of the amplification module 100 to compensate for the voltage of the amplification module 100. The driving capability changes with temperature, so that a compensation voltage Vos of appropriate size is generated on the bit line BL and the complementary bit line BLB, which accurately eliminates the noise signal of the amplification module 100 and improves the accuracy of the sensitive amplifier.

In some embodiments, as shown in Figure 4, the control module 200 includes a pulse width parameter unit 220 and an adjustment unit 210. The pulse width parameter unit 220 is provided with an output end, and the adjustment unit 210 is provided with an input end, an output end and a control end, The output terminal of the pulse width parameter unit 220 is connected to the control terminal of the adjustment unit 210 . The pulse width parameter unit 220 is used to generate a pulse width adjustment signal according to the temperature data of the amplification module 100 . The input end of the adjustment unit 210 receives the first offset cancellation signal OC1. The adjustment unit 210 performs pulse width adjustment processing on the first offset cancellation signal OC1 according to the pulse width adjustment signal and outputs a second offset cancellation signal OC2.

In some embodiments, the pulse width parameter unit 220 compares the temperature data of the amplification module 100 with each temperature gear range to obtain the gear information, and then generates a pulse width adjustment signal according to the gear information. When the gear information corresponding to the temperature data is different, the pulse width adjustment signal is different.

In the above technical solution, the control module 200 is provided with a pulse width parameter unit 220 and an adjustment unit 210. The pulse width parameter unit 220 generates a pulse width adjustment signal according to the temperature data of the amplification module 100, so that the adjustment unit 210 controls the pulse width adjustment signal. The pulse width of the first offset cancellation signal OC1 is adjusted to adjust the pulse width of the first offset cancellation signal OC1 based on the temperature data of the amplification module 100 .

In some embodiments, as shown in Figure 4, the pulse width parameter unit 220 includes a temperature sensor 221 and a temperature decoder 222. The temperature sensor 221 is provided with an output terminal, and the temperature decoder 222 is provided with an input terminal and an output terminal. The output terminal of the temperature sensor 221 is connected to the input terminal of the temperature decoder 222 . The temperature sensor 221 is used to detect the temperature data of the amplification module 100 and generate temperature coded data according to the temperature data. Temperature decoder 222 is used to generate a pulse width adjustment signal based on the temperature encoded data.

In some embodiments, the temperature decoder 222 is used to decode the temperature encoded data, compare the decoding result with each temperature gear range to obtain the gear information, and then generate a pulse width adjustment according to the gear information. Signal.

In some embodiments, as shown in FIG. 4 , the pulse width parameter unit 220 includes three output terminals, the pulse width adjustment signal includes three gate signals, and each output terminal of the pulse width parameter unit 220 outputs one gate signal. The adjustment unit 210 includes a first adjustment sub-unit 211, a second adjustment sub-unit 212, a third adjustment sub-unit 213 and a selection unit 214. The first adjustment sub-unit 211, the second adjustment sub-unit 212 and the third adjustment sub-unit 213 are each provided with an input end and an output end. The selection unit 214 is provided with three input terminals, which are sequentially labeled as a first input terminal, a second input terminal and a third input terminal. The selection unit 214 is also provided with three control terminals.

The input end of the first adjustment sub-unit 211 receives the first offset cancellation signal OC1. The output end of the first adjustment sub-unit 211 is connected to the first input end of the selection unit 214. The first adjustment sub-unit 211 is used to adjust the first offset signal OC1. The offset cancellation signal OC1 is pulse width adjusted to output a third offset cancellation signal OC3. The input end of the second adjustment sub-unit 212 receives the first offset cancellation signal OC1. The output end of the second adjustment sub-unit 212 is connected to the second input end of the selection unit 214. The second adjustment sub-unit 212 is used to adjust the first offset signal OC1. The offset cancellation signal OC1 is pulse width adjusted to output a fourth offset cancellation signal OC4. The input end of the third adjustment sub-unit 213 receives the first offset cancellation signal OC1. The output end of the third adjustment sub-unit 213 is connected to the third input end of the selection unit 214. The third adjustment sub-unit 213 is used to adjust the first offset signal OC1. The offset cancellation signal OC1 is pulse width adjusted to output a fifth offset cancellation signal OC5.

The pulse width adjustment amounts of the first adjustment sub-unit 211, the second adjustment sub-unit 212 and the third adjustment sub-unit 213 are all different. The pulse width of the fifth offset cancellation signal OC5, the pulse width of the fourth offset cancellation signal OC4 and The pulse widths of the third offset cancellation signals OC3 are all different.

Each control terminal of the selection unit 214 is connected to the output terminal of the corresponding pulse width parameter unit 220, so that each control terminal of the selection unit 214 receives the corresponding strobe signal. The selection unit 214 is used to control the three strobe signals. Next, one of the third offset cancellation signal OC3, the fourth offset cancellation signal OC4, and the fifth offset cancellation signal OC5 is selected to be output. The output signal of the selection unit 214 is used to control the elimination of the noise signal of the amplification module 100.

In some embodiments, the output terminal of the selection unit 214 is connected to the control terminal of the amplification module 100, and the amplification module 100 eliminates its internal noise signal under the control of the output signal of the selection unit 214.

The three strobe signals output by the pulse width parameter unit 220 are labeled as a first strobe signal, a second strobe signal and a third strobe signal. The first strobe signal is used to control whether the selection unit 214 selects the third offset cancellation signal OC3 output by the first adjustment sub-unit 211, and the second strobe signal is used to control whether the selection unit 214 selects the second adjustment sub-unit. The fourth offset cancellation signal OC4 output by 212 is output, and the third strobe signal is used to control whether the selection unit 214 selects the fifth offset cancellation signal OC5 output by the third adjustment sub-unit 213 for output.

In some embodiments, the upper limit of the first temperature range is less than or equal to the lower limit of the second temperature range, and the upper limit of the second temperature range is less than or equal to the lower limit of the third temperature range. For example: the first temperature range is T≤20℃, the second temperature range is 20℃<T≤60℃, and the third temperature range is T>60℃.

In some embodiments, the pulse width of the third offset cancellation signal OC3 is smaller than the pulse width of the fourth offset cancellation signal OC4, and the pulse width of the fourth offset cancellation signal OC4 is smaller than the pulse width of the fifth offset cancellation signal OC5.

When the temperature data is within the first temperature range, the first strobe signal output by the pulse width parameter unit 220 is a valid value, and the second strobe signal and the third strobe signal output by the pulse width parameter unit 220 are invalid values, achieving The control selection unit 214 selects the third offset cancellation signal OC3 to output.

When the temperature data is within the second temperature range, the second strobe signal output by the pulse width parameter unit 220 is a valid value, and the first strobe signal and the third strobe signal output by the pulse width parameter unit 220 are invalid values, achieving The control selection unit 214 selects the fourth offset cancellation signal OC4 to output.

When the temperature data is within the third temperature range, the third strobe signal output by the pulse width parameter unit 220 is a valid value, and the first strobe signal and the second strobe signal output by the pulse width parameter unit 220 are invalid values, and the control The selection unit 214 selects the fifth offset cancellation signal OC5 to output.

In the above technical solution, the adjustment unit 210 includes a selection unit 214 and three adjustment sub-units. Each adjustment sub-unit is used to perform pulse width adjustment processing on the first offset cancellation signal OC1, and the pulse width of the three adjustment sub-units is The adjustment amounts are different. The selection unit 214 selects from the output signals of the three adjustment subunits according to the three strobe signals. The selection strobe signal is generated by the temperature decoder 222 according to the temperature data of the amplification module 100, thereby realizing the operation based on the amplification module 100. The temperature data adjusts the pulse width of the first offset cancellation signal OC1.

In some embodiments, as shown in FIG. 5 , the first adjustment subunit 211 includes a first delay circuit 321 and a first AND gate 311 , and the first delay circuit 321 is provided with input and output terminals. The second input terminal In2 of the first AND gate 311 is connected to the output terminal of the first delay circuit 321. The input terminal of the first delay circuit 321 receives the first offset cancellation signal OC1. The first delay circuit 321 performs the first offset cancellation on The signal OC1 undergoes delay processing and outputs a first delayed signal. The first input terminal In1 of the first AND gate 311 receives the first offset cancellation signal OC1. The second input terminal In2 of the first AND gate 311 receives the first delay signal. The first AND gate 311 responds to the first offset cancellation signal OC1. After performing an AND operation with the first delayed signal, the third offset cancellation signal OC3 is output through its output terminal Out1.

In some embodiments, the first delay circuit 321 includes a first access line 331, a first P-type transistor P1, and a first N-type transistor N1. One end of the first access line 331 is connected to the second input terminal In2 of the first AND gate 311, the other end of the first access line 331 receives the first offset cancellation signal OC1, and the first access line 331 The shift cancellation signal OC1 is transmitted to the second input terminal In2 of the first AND gate 311 .

The gate of the first P-type transistor P1 is connected to the first access line 331, and the drain of the first P-type transistor P1 is connected to the source of the first P-type transistor P1 and then connected to the first power terminal V1. The gate of the first N-type transistor N1 is connected to the first access line 331, and the drain of the first N-type transistor N1 is connected to the source of the first N-type transistor N1 and then connected to the second power terminal V2. The voltage of the first power terminal V1 is greater than the voltage of the second power terminal V2, and the second power terminal V2 is usually a ground terminal. Through such arrangement, the first P-type transistor P1 and the first N-type transistor N1 are connected as capacitors to the second input terminal In2 of the first AND gate 311 to achieve the first offset cancellation signal transmitted by the first access line 331 The delay processing of OC1 causes the second input terminal In2 of the first AND gate 311 to receive the first delayed signal. That is, if the first offset cancellation signal OC1 is a low-level pulse signal, the first delay signal is also a low-level pulse signal, and the falling edge moment of the first delay signal is later than the falling edge of the first offset cancellation signal OC1 along time. If the first offset cancellation signal OC1 is a high-level pulse signal, the first delay signal is also a high-level pulse signal, and the rising edge time of the first delay signal is later than the rising edge time of the first offset cancellation signal OC1 .

As shown in Figure 6, if the first offset cancellation signals OC1 are all low-level pulse signals, the first input terminal In1 of the first AND gate 311 receives the first offset cancellation signal OC1, and the second input terminal In1 of the first AND gate 311 The input terminal In2 receives the first delayed signal, and the falling edge time of the first delayed signal is later than the falling edge time of the first offset cancellation signal OC1. The first AND gate 311 performs an AND operation on the first offset cancellation signal OC1 and the first delay signal, and outputs the third offset cancellation signal OC3 through its output terminal Out1. The third offset cancellation signal OC3 is still low level. The pulse width of the pulse signal, the third offset cancellation signal OC3 becomes larger, and the increase amount is the time difference Δτ1 between the falling edges of the first delay signal and the first offset cancellation signal OC1.

In some embodiments, the second adjustment subunit 212 includes a second delay circuit 322 and a second AND gate 312. The second delay circuit 322 includes an input terminal and an output terminal. The output terminal of the second delay circuit 322 is connected to the second AND gate. The second input terminal In4 of 312 is connected. The input terminal of the second delay circuit 322 receives the first offset cancellation signal OC1, and the second delay circuit 322 delays the first offset cancellation signal OC1 and outputs a second delayed signal. And the delay amount of the delay processing performed by the second delay circuit 322 is greater than the delay amount of the delay processing performed by the first delay circuit 321. That is, when the first offset cancellation signal OC1 is a low-level pulse signal, the falling edge of the second delay signal The time difference Δτ2 between the falling edge time of the second offset cancellation signal OC2 and the falling edge time of the second offset cancellation signal OC2 is greater than the time difference Δτ1 between the falling edge time of the first delayed signal and the falling edge time of the first offset cancellation signal OC1 .

The first input terminal In3 of the second AND gate 312 receives the first offset cancellation signal OC1, the second input terminal In4 of the second AND gate 312 receives the second delayed signal, and the second AND gate 312 converts the first offset cancellation signal OC1 After performing an AND operation with the second delayed signal, the fourth offset cancellation signal OC4 is output through its output terminal Out2.

In some embodiments, as shown in FIG. 7 , the second delay circuit 322 includes a second access line 332, a second P-type transistor P2, a second N-type transistor N2, a third P-type transistor P3, and a third N-type transistor. Transistor N3. One end of the second access line 332 is connected to the second input terminal In4 of the second AND gate 312, the other end of the second access line 332 receives the first offset cancellation signal OC1, and the second access line 332 transmits the first offset signal OC1. Move the cancellation signal OC1 to the second input terminal In4 of the second AND gate 312 .

The gate of the second P-type transistor P2 is connected to the second access line 332, and the drain of the second P-type transistor P2 is connected to the source of the second P-type transistor P2 and then connected to the first power terminal V1. The gate of the second N-type transistor N2 is connected to the second access line 332, and the drain of the second N-type transistor N2 is connected to the source of the second N-type transistor N2 and then connected to the second power terminal V2. The gate of the third P-type transistor P3 is connected to the second access line 332, and the drain of the third P-type transistor P3 is connected to the source of the third P-type transistor P3 and then connected to the first power terminal V1. The gate of the third N-type transistor N3 is connected to the second access line 332, and the drain of the third N-type transistor N3 is connected to the source of the third N-type transistor N3 and then connected to the second power terminal V2.

With such an arrangement, the second P-type transistor P2, the second N-type transistor N2, the third P-type transistor P3 and the third N-type transistor N3 are all connected as capacitors to the second input terminal In4 of the second AND gate 312, so as to achieve Delay processing of the first offset cancellation signal OC1 transmitted through the second access line 332 .

Since there are four transistors in the second delay circuit 322, it is equivalent to connecting four capacitors to the second input terminal In4 of the second AND gate 312. There are two transistors in the first delay circuit 321, which is equivalent to two capacitors connected to the second input terminal In2 of the first AND gate 311. Therefore, the second delay circuit 322 delays the first offset cancellation signal OC1 by a larger delay amount.

As shown in Figure 8, if the first offset cancellation signal OC1 is both a low-level pulse signal. The first input terminal In3 of the second AND gate 312 receives the first offset cancellation signal OC1. The second input terminal In4 of the second AND gate 312 receives the second delayed signal. The falling edge of the second delayed signal is later than the first offset signal. Shift the falling edge moment of cancellation signal OC1. The second AND gate 312 performs an AND operation on the first offset cancellation signal OC1 and the second delay signal, and outputs the fourth offset cancellation signal OC4 through its output terminal Out2. The fourth offset cancellation signal OC4 is still a low-level pulse signal, and the pulse width of the fourth offset cancellation signal OC4 becomes larger by the time difference Δτ2 between the falling edges of the second delay signal and the first offset cancellation signal OC1 . Since the time difference Δτ2 between the falling edges of the second delay signal and the first offset cancellation signal OC1 is greater than the time difference Δτ1 between the falling edges of the first delay signal and the first offset cancellation signal OC1, then the fourth offset cancellation signal OC4 The pulse width of is greater than the pulse width of the third offset cancellation signal OC3.

In some embodiments, as shown in FIG. 9 , the third adjustment subunit 213 includes a third delay circuit 323 and a third AND gate 313 . The third delay circuit 323 is provided with an input terminal and an output terminal, and the output terminal of the third delay circuit 323 is connected to the second input terminal In6 of the third AND gate 313 . The input terminal of the third delay circuit 323 receives the first offset cancellation signal OC1, the third delay circuit 323 performs delay processing on the first offset cancellation signal OC1 and outputs a third delay signal, and the third delay circuit 323 performs delay processing. The amount is greater than the delay amount for the second delay circuit 322 to perform delay processing. When the first offset cancellation signal OC1 is a low-level pulse signal, the time difference Δτ3 between the falling edges of the third delay signal and the first offset cancellation signal OC1 is greater than the falling edge of the second delay signal and the first offset cancellation signal OC1 The time difference along the edge is Δτ2.

The first input terminal In5 of the third AND gate 313 receives the first offset cancellation signal OC1, the second input terminal In6 of the third AND gate 313 receives the third delay signal, and the third AND gate 313 converts the first offset cancellation signal OC1 AND operation is performed with the third delayed signal, and the fifth offset cancellation signal OC5 is output through its output terminal Out3.

In some embodiments, the third delay circuit 323 includes a third access line 333, a fourth P-type transistor P4, a fourth N-type transistor N4, a fifth P-type transistor P5, a fifth N-type transistor N5, a sixth P-type transistor type transistor P6 and the sixth N-type transistor N6. One end of the third access line 333 is connected to the second input terminal In6 of the third AND gate 313, the other end of the third access line 333 receives the first offset cancellation signal OC1, and the third access line 333 transmits the first offset signal OC1. Move the cancellation signal OC1 to the second input terminal In6 of the third AND gate 313 .

The gate of the fourth P-type transistor P4 is connected to the third access line 333, and the drain of the fourth P-type transistor P4 is connected to the source of the fourth P-type transistor P4 and then connected to the first power terminal V1. The gate of the fourth N-type transistor N4 is connected to the third access line 333, and the drain of the fourth N-type transistor N4 is connected to the source of the fourth N-type transistor N4 and then connected to the second power terminal V2.

The gate of the fifth P-type transistor P5 is connected to the third access line 333, and the drain of the fifth P-type transistor P5 is connected to the source of the fifth P-type transistor P5 and then connected to the first power terminal V1. The gate of the fifth N-type transistor N5 is connected to the third access line 333, and the drain of the fifth N-type transistor N5 is connected to the source of the fifth N-type transistor N5 and then connected to the second power terminal V2.

The gate of the sixth P-type transistor P6 is connected to the third access line 333, and the drain of the sixth P-type transistor P6 is connected to the source of the sixth P-type transistor P6 and then connected to the first power terminal V1. The gate of the sixth N-type transistor N6 is connected to the third access line 333, and the drain of the sixth N-type transistor N6 is connected to the source of the sixth N-type transistor N6 and then connected to the second power terminal V2.

With this arrangement, the fourth P-type transistor P4, the fourth N-type transistor N4, the fifth P-type transistor P5, the fifth N-type transistor N5, the sixth P-type transistor P6 and the sixth N-type transistor N6 all serve as capacitors and are connected At the second input terminal In6 of the third AND gate 313, the delay processing of the first offset cancellation signal OC1 transmitted through the third access line 333 is achieved. Since there are six transistors in the third delay circuit 323, it is equivalent to having six capacitors connected to the second input terminal In6 of the third AND gate 313. There are four transistors in the second delay circuit 322, and four capacitors are connected to the second input terminal In4 of the second AND gate 312. Therefore, compared with the second delay circuit 322, the third delay circuit 323 delays the first offset cancellation signal OC1 by a larger delay amount.

As shown in Figure 10, the first offset cancellation signals OC1 are all low-level pulse signals. The first input terminal In5 of the third AND gate 313 receives the first offset cancellation signal OC1, and the second input terminal In6 of the third AND gate 313 receives the third delayed signal. The falling edge time of the third delayed signal is later than that of the first offset signal. Shift the falling edge moment of cancellation signal OC1. The third AND gate 313 performs an AND operation on the first offset cancellation signal OC1 and the third delay signal, and outputs the fifth offset cancellation signal OC5 through its output terminal Out3. The fifth offset cancellation signal OC5 is still low level. The pulse width of the pulse signal, the fifth offset cancellation signal OC5 becomes larger, and the increase amount is the time difference Δτ3 between the falling edges of the third delay signal and the first offset cancellation signal OC1. Since the time difference Δτ3 between the falling edges of the third delayed signal and the first offset cancellation signal OC1 is greater than the time difference Δτ2 between the falling edges of the second delay signal and the first offset cancellation signal OC1, then the fifth offset cancellation signal OC5 The pulse width of is greater than the pulse width of the fourth offset cancellation signal OC4.

In the above technical solution, each adjustment subunit includes an AND gate and a delay circuit. The delay circuit is used to delay the first offset cancellation signal OC1. The AND gate is used to delay the first offset cancellation signal OC1 and the delayed delay circuit. The first offset cancellation signal OC1 is ANDed to increase the pulse width of the first offset signal, and the increase amount is equal to the delay amount of the delay circuit for delay processing. The number of transistors set as capacitors in each delay circuit is different, and the delay amount of the first offset cancellation signal OC1 can be adjusted to achieve different pulse widths of the offset cancellation signals output by each adjustment subunit.

In some embodiments, as shown in Figure 4, the adjustment unit 210 also includes an inverter 215. The input end of the inverter 215 is connected to the output end of the selection unit 214. The output signal of the inverter 215 is used to control the elimination of the The noise signal of the amplification module.

In some embodiments, the output terminal of the inverter 215 serves as the output terminal of the control module 200 and is connected to the control terminal of the amplification module 100. The amplification module 100 eliminates its internal noise signal under the control of the output signal of the inverter.

In some embodiments, continuing to refer to FIG. 3 , the amplification module 100 includes a seventh P-type transistor P7, an eighth P-type transistor P8, a seventh N-type transistor N7, an eighth N-type transistor N8, a ninth N-type transistor N9, The tenth N-type transistor N10, the eleventh N-type transistor N1, and the twelfth N-type transistor N12. The connection relationship of each transistor has been explained in detail in the description of Figure 1 and will not be repeated here.

In some embodiments, the amplification module 100 includes a ninth P-type transistor P9 and a thirteenth N-type transistor N13. The source of the ninth P-type transistor P9 is connected to the third power terminal V3, and the drain of the ninth P-type transistor P9 is connected to the third power terminal V3. The pole is connected to the first terminal LA of the amplifier module 100 . The source of the thirteenth N-type transistor N13 is connected to the fourth power terminal V4, and the drain of the thirteenth N-type transistor N13 is connected to the second terminal LAB of the amplification module 100. The voltage of the third power terminal V3 is greater than the voltage of the fourth power terminal V4, and the fourth power terminal V4 is usually a ground terminal.

Among them, the gate of the ninth N-type transistor N9 and the gate of the tenth N-type transistor N10 serve as the control terminal of the amplification module 100 and are connected to the output terminal of the control module 200 .

In some embodiments, when the first offset cancellation signal OC is a low-level pulse signal, the output terminal of the inverter 215 serves as the output terminal of the control module 200, the gate of the ninth N-type transistor N9 and the tenth N The gates of the transistors N10 are connected to the output terminals of the inverter 215 .

As shown in Figure 11, in the precharge stage T1, the isolation control signal ISO and the second offset cancellation signal OC2 are high level, the eleventh N-type transistor N11 and the twelfth N-type transistor N12 are both turned on, and the bit line BL It is connected to the sense bit line SABL, and the complementary bit line BLB is connected to the complementary sense bit line SABLB. The ninth N-type transistor N9 and the tenth N-type transistor N10 are both turned on, and the bit line BL, the sense bit line SABL, the complementary bit line BLB and the complementary sense bit line SABLB are connected to each other. The first enable signal SAP received by the ninth P-type transistor P9 is high level, the second enable signal SAN received by the thirteenth N-type transistor N13 is low level, the third power supply terminal V3 and the fourth power supply terminal V4 Disconnected from the amplification module 100 . The voltage of the third power terminal V3 is greater than the voltage of the fourth power terminal V4. The charging module pulls the voltages of the bit line BL, the complementary bit line BLB, the sense bit line SABL and the complementary sense bit line SABLB to the charging value.

In the offset elimination stage T2, the isolation control signal ISO is at low level, the eleventh N-type transistor N11 and the twelfth N-type transistor N12 are both turned off, the second offset elimination signal OC2 is at high level, the ninth N-type transistor N9 and The tenth N-type transistor N10 is turned on, and the seventh N-type transistor N7 and the eighth N-type transistor N8 are diode connected. The first enable signal SAP received by the ninth P-type transistor P9 is low level, the second enable signal SAN received by the thirteenth N-type transistor N13 is high level, the third power supply terminal V3 and the fourth power supply terminal V4 Connected to the amplification module 100.

When the temperature data is within the first temperature range, the selection unit 214 in the control module 200 selects the third offset cancellation signal OC3 output by the first adjustment sub-unit 211 to output, and after the inverter 215 does not operate, a high-level pulse signal is output. , at this time, the voltage driving capability of the amplification module 100 is relatively strong, and the third offset cancellation signal OC3 with a smaller pulse width is selected to be output, and the ninth N-type transistor N9 and the tenth N-type transistor N10 are controlled to be turned on, which can shorten the offset. Eliminate the duration of the phase T2. After the compensation voltage Vos of appropriate size is generated on the bit line BL and the complementary bit line BLB, the ninth N-type transistor N9 and the tenth N-type transistor N10 are turned off in time to avoid the ninth N-type transistor N9 and the tenth N-type transistor N10. The tenth N-type transistor N10 continues to be turned on to generate an excessive compensation voltage Vos.

When the temperature data is within the second temperature range, the selection unit 214 in the control module 200 selects the fourth offset cancellation signal OC4 output by the second adjustment sub-unit 212 to output, and after the inverter 215 does not operate, a high-level pulse signal is output. , at this time, compared with the temperature data within the first temperature range, the voltage driving capability of the amplification module 100 is weakened, and the fourth offset cancellation signal OC4 with a pulse width larger than the third offset cancellation signal OC3 is selected to be output, and the ninth N is controlled. The N-type transistor N9 and the tenth N-type transistor N10 are turned on, which can appropriately extend the duration of the offset elimination phase T2 to compensate for the weakening of the transistor voltage driving capability in the amplification module 100, resulting in a Suitable size compensation voltage Vos.

When the temperature data is within the third temperature range, the selection unit 214 in the control module 200 selects the fifth offset cancellation signal OC5 output by the third adjustment sub-unit 213, and after the inverter 215 performs a non-operation, a high-level pulse signal is output. At this time, compared with the temperature data within the second temperature range, the voltage driving capability of the amplification module 100 is weakened, and the fifth offset cancellation signal OC5 with a pulse width greater than the fourth offset cancellation signal OC4 is selected to be output to control the ninth N-type The transistor N9 and the tenth N-type transistor N10 are turned on, which can further extend the duration of the offset elimination phase T2 to compensate for the weakening of the transistor voltage driving capability in the amplification module 100 and generate appropriate voltage on the bit line BL and the complementary bit line BLB. The size of the compensation voltage Vos.

In the charge sharing stage T3, the isolation control signal ISO is low level, the eleventh N-type transistor N11 and the twelfth N-type transistor N12 are turned off, the second offset cancellation signal OC2 is low level, the ninth N-type transistor N9 and The tenth N-type transistor N10 is turned off, the first enable signal SAP received by the ninth P-type transistor P9 is high level, the second enable signal SAN received by the thirteenth N-type transistor N13 is low level, and the third power supply The terminal V3 and the fourth power terminal V4 are disconnected from the amplifier module 100 . The word line signal is valid, and the memory cell shares charge with the bit line BL or the complementary bit line BLB.

In the sensing amplification stage T4, the isolation control signal ISO is low level, the eleventh N-type transistor N11 and the twelfth N-type transistor N12 are turned off, the second offset cancellation signal OC2 is low level, the ninth N-type transistor N9 and The tenth N-type transistor N10 is turned off, the first enable signal SAP received by the ninth P-type transistor P9 is low level, the second enable signal SAN received by the thirteenth N-type transistor N13 is high level, and the third power supply The terminal V3 and the fourth power terminal V4 pull the voltages of the sense bit line SABL and the complementary sense bit line SABLB based on the data voltage difference on the bit line BL and the complementary bit line BLB. Since the sense bit line SABL and the complementary sense bit line SABLB There is already a compensation voltage Vos on the sense amplifier. The compensation voltage Vos can offset the noise signal caused by the manufacturing difference of the seventh N-type transistor N7 and the eighth N-type transistor N8 in the sense amplifier. On the sense bit line SABL and the complementary sense bit line SABLB Present data accurately.

In the recovery stage T5, the isolation control signal ISO is high level, the eleventh N-type transistor N11 and the twelfth N-type transistor N12 are turned on, the second offset cancellation signal OC2 is low level, the ninth N-type transistor N9 and The tenth N-type transistor N10 is turned off, the first enable signal SAP received by the ninth P-type transistor P9 is low level, the second enable signal SAN received by the thirteenth N-type transistor N13 is high level, and the read bit The line SABL pulls the voltage of the bit line BL, and the complementary sense bit line SABLB pulls the voltage of the complementary bit line BLB to restore the stored charge in the memory cell.

In the above technical solution, the sensitive amplifier includes a control module and an amplification module. The control module is used to adjust the pulse width of the first offset cancellation signal according to the temperature data of the amplification module to compensate for the changes in the transistors in the amplification module as the temperature changes. situation, a suitable size of compensation voltage is generated on the bit line and the complementary bit line, the noise signal of the amplification module 100 is accurately eliminated, and the accuracy of the sensitive amplifier is improved.

An embodiment of the present disclosure also provides a semiconductor memory, including the sense amplifier provided in the above embodiment.

Other embodiments of the disclosure will be readily apparent to those skilled in the art from consideration of the specification and practice of the invention disclosed herein. The present disclosure is intended to cover any variations, uses, or adaptations of the disclosure that follow the general principles of the disclosure and include common common sense or customary technical means in the technical field that are not disclosed in the disclosure. . It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the disclosure being indicated by the following claims.

It is to be understood that the present disclosure is not limited to the precise structures described above and illustrated in the accompanying drawings, and various modifications and changes may be made without departing from the scope thereof. The scope of the disclosure is limited only by the appended claims.

Claims (16)

1. A sensitive amplifier including:

   A control module, which is provided with an input end and an output end, is used to obtain the temperature data of the amplification module, perform pulse width adjustment on the first offset elimination signal received at the input end according to the temperature data of the amplification module, generate and output a second offset cancellation signal;

   The control end of the amplification module is connected to the output end of the control module, and is used to eliminate the noise signal of the amplification module under the control of the second offset cancellation signal.
2. The sense amplifier of claim 1, wherein the control module includes:

   A pulse width parameter unit, which is provided with an output terminal and is used to generate a pulse width adjustment signal according to the temperature data of the amplification module;

   An adjustment unit is provided with an input end, an output end and a control end. Its control end is connected to the output end of the pulse width parameter unit. Its input end receives the first offset elimination signal and adjusts the signal according to the pulse width. The first offset cancellation signal is subjected to pulse width adjustment processing, and the second offset cancellation signal is output.
3. The sense amplifier according to claim 2, wherein the pulse width parameter unit includes three output terminals, the pulse width adjustment signal includes three strobe signals, and the adjustment unit includes:

   A first adjustment subunit, the output end of which is connected to the first input end of the selection unit, for performing pulse width adjustment on the first offset cancellation signal and outputting a third offset cancellation signal;

   A second adjustment subunit, the output end of which is connected to the second input end of the selection unit, is used to perform pulse width adjustment on the first offset cancellation signal and output a fourth offset cancellation signal;

   A third adjustment subunit, the output end of which is connected to the third input end of the selection unit, is used to perform pulse width adjustment on the first offset cancellation signal and output a fifth offset cancellation signal; wherein, the third The pulse width of the offset cancellation signal, the pulse width of the fourth offset cancellation signal, and the pulse width of the fifth offset cancellation signal are all different;

   The selection unit is provided with three control terminals, each control terminal is connected to the output terminal corresponding to the pulse width parameter unit, and receives the corresponding strobe signal; used to select from the control terminal under the control of the three strobe signals. One of the third offset cancellation signal, the fourth offset cancellation signal and the fifth offset cancellation signal is selected to be output, and the output signal of the selection unit is used to control the elimination of the noise signal of the amplification module.
4. The sense amplifier according to claim 3, wherein the adjustment unit further includes:

   The input end of the inverter is connected to the output end of the selection unit, and its output signal is used to control the elimination of the noise signal of the amplification module.
5. The sense amplifier according to claim 3 or 4, wherein the first adjustment subunit includes:

   A first delay circuit, the input end of which receives the first offset cancellation signal, and is used to delay processing the first offset cancellation signal and output a first delay signal;

   A first AND gate, a first input terminal of which receives the first offset cancellation signal, a second input terminal of which is connected to the output terminal of the first delay circuit, receives the first delay signal, and an output terminal of which outputs the first delay signal. The third offset cancellation signal.
6. The sense amplifier of claim 5, wherein the first delay circuit includes:

   A first access line, one end of which serves as the output end of the first delay circuit, and the other end of which receives the first offset cancellation signal;

   The first P-type transistor has its gate connected to the first access line, its drain connected to its source and then connected to the first power terminal;

   The first N-type transistor has its gate connected to the first access line, its drain connected to its source and then connected to the second power terminal.
7. The sense amplifier according to claim 3 or 4, wherein the second adjustment subunit includes:

   A second delay circuit, the input terminal of which receives the first offset cancellation signal, is used to delay the first offset cancellation signal and output a second delay signal; and the second delay circuit performs delay processing. The amount is greater than the delay amount of the first delay circuit for delay processing;

   The second AND gate has a first input end that receives the first offset cancellation signal, a second input end that is connected to the output end of the second delay circuit, receives the second delay signal, and an output end that outputs the second AND gate. The fourth offset cancellation signal.
8. The sense amplifier of claim 7, wherein the second delay circuit includes:

   a second access line, one end of which serves as the output end of the second delay circuit, and the other end of which receives the first offset cancellation signal;

   The second P-type transistor has a gate connected to the second access line, a drain connected to its source and then connected to the first power terminal;

   The second N-type transistor has a gate connected to the second access line, a drain connected to its source and then connected to the second power terminal;

   The third P-type transistor has its gate connected to the second access line, its drain connected to its source and then connected to the first power terminal;

   The third N-type transistor has its gate connected to the second access line, its drain connected to its source and then connected to the second power terminal.
9. The sense amplifier according to claim 4, wherein the third adjustment subunit includes:

   A third delay circuit whose input terminal receives the first offset cancellation signal is used to delay the first offset cancellation signal and output a third delay signal; and the third delay circuit performs delay processing. The amount is greater than the delay amount of the second delay circuit for delay processing;

   A third AND gate has a first input end that receives the first offset cancellation signal, a second input end that is connected to the output end of the third delay circuit, receives the third delay signal, and an output end that outputs the The fifth offset cancellation signal.
10. The sense amplifier of claim 9, wherein the third delay circuit includes:

    A third access line, one end of which serves as the output end of the third delay circuit, and the other end of which receives the first offset cancellation signal;

    The fourth P-type transistor has its gate connected to the third access line, its drain connected to its source and then connected to the first power terminal;

    The fourth N-type transistor has its gate connected to the third access line, its drain connected to its source and then connected to the second power terminal;

    The fifth P-type transistor has its gate connected to the third access line, its drain connected to its source and then connected to the first power terminal;

    The fifth N-type transistor has its gate connected to the third access line, its drain connected to its source and then connected to the second power terminal;

    The sixth P-type transistor has its gate connected to the third access line, its drain connected to its source and then connected to the first power terminal;

    The sixth N-type transistor has its gate connected to the third access line, its drain connected to its source and then connected to the second power terminal.
11. The sense amplifier according to claim 2, wherein the pulse width parameter unit includes:

    A temperature sensor used to detect the temperature data of the amplification module and generate temperature coded data according to the temperature data;

    A temperature decoder, the input end of which is connected to the output end of the temperature sensor, is used to generate the pulse width adjustment signal according to the temperature encoded data.
12. The sense amplifier according to claim 3, wherein the pulse width parameter unit is used for:

    When the temperature data is within the first temperature range, the output first strobe signal is a valid value, and the output second strobe signal and third strobe signal are invalid values; the selection unit is controlled to select the third strobe signal. Three offset cancellation signal outputs;

    When the temperature data is within the second temperature range, the output second strobe signal is a valid value, and the output first strobe signal and the third strobe signal are invalid values; control the The selection unit selects the fourth offset cancellation signal output;

    When the temperature data is within the third temperature range, the output third strobe signal is a valid value, and the output first strobe signal and the second strobe signal are invalid values; control the The selection unit selects the fifth offset cancellation signal output;

    Wherein, the upper limit value of the first temperature range is less than or equal to the lower limit value of the second temperature range, and the upper limit value of the second temperature range is less than or equal to the lower limit value of the third temperature range; the third temperature range The pulse width of the offset cancellation signal is smaller than the pulse width of the fourth offset cancellation signal, and the pulse width of the fourth offset cancellation signal is smaller than the pulse width of the fifth offset cancellation signal.
13. The sensitive amplifier according to claim 1, wherein the amplification module includes:

    The seventh P-type transistor has its source connected to the source of the eighth P-type transistor, and its gate connected to the drain of the eighth P-type transistor;

    The gate of the eighth P-type transistor is connected to the drain of the seventh P-type transistor;

    The seventh N-type transistor has its drain connected to the drain of the seventh P-type transistor, its source connected to the source of the eighth N-type transistor, and its gate connected to the bit line;

    The drain of the eighth N-type transistor is connected to the drain of the eighth P-type transistor, and the gate thereof is connected to the complementary bit line;

    The ninth N-type transistor has a first end connected to the bit line, a second end connected to the drain of the seventh N-type transistor, and a gate thereof serving as the control end of the amplification module;

    The second end of the tenth N-type transistor is connected to the complementary bit line, the first end is connected to the drain of the eighth N-type transistor, and its gate serves as the control end of the amplification module.
14. The sensitive amplifier according to claim 13, wherein the amplification module includes:

    An eleventh N-type transistor, a first end of which is connected to the bit line, a second end of which is connected to the drain of the eighth N-type transistor, and a gate of which receives an isolation control signal;

    The second end of the twelfth N-type transistor is connected to the complementary bit line, the first end is connected to the drain of the seventh N-type transistor, and its gate receives the isolation control signal.
15. The sensitive amplifier according to claim 13, wherein the amplification module includes:

    The ninth P-type transistor has its source connected to the third power terminal and its drain connected to the source of the seventh P-type transistor;

    The source of the thirteenth N-type transistor is connected to the fourth power supply terminal, and the drain of the thirteenth N-type transistor is connected to the source of the seventh N-type transistor.
16. A semiconductor memory including the sense amplifier according to any one of claims 1 to 15.

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