CN115145542B - True random number generating circuit and chip - Google Patents

True random number generating circuit and chip Download PDF

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Publication number
CN115145542B
CN115145542B CN202211068443.5A CN202211068443A CN115145542B CN 115145542 B CN115145542 B CN 115145542B CN 202211068443 A CN202211068443 A CN 202211068443A CN 115145542 B CN115145542 B CN 115145542B
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switch
terminal
capacitor
random number
comparator
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CN115145542A (en
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束克留
万海军
韩兴成
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Suzhou Powerlink Microelectronics Inc
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Suzhou Powerlink Microelectronics Inc
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    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/58—Random or pseudo-random number generators
    • G06F7/588—Random number generators, i.e. based on natural stochastic processes

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Abstract

The invention discloses a true random number generating circuit and a chip, wherein the circuit comprises: a current integrator, a second order low pass filter and a comparator. The current integrator is used for outputting an integration voltage under the control of a data signal; the second-order low-pass filter is used for carrying out low-pass filtering on the integrated voltage to obtain an input voltage; the comparator is used for receiving the input voltage and the reference voltage and outputting a data signal under the action of noise of the input voltage, noise of the reference voltage and equivalent input noise of the comparator, and the sum of the noise of the input voltage, the noise of the reference voltage and the equivalent input noise of the comparator is larger than the difference value of the input voltage of the comparator and the reference voltage in a random time period. According to the true random number generation circuit provided by the embodiment of the invention, the problem of data signal deadlock is solved through the current integrator, and the bandwidth requirement of the second-order low-pass filter is reduced. The second order low pass filter can enhance high frequency attenuation, and can reduce the total capacitance and the chip area due to the larger bandwidth.

Description

True random number generating circuit and chip
Technical Field
The present invention relates to the field of integrated circuits, and more particularly, to a true random number generating circuit and a chip.
Background
With the progress of semiconductor chip technology and communication technology, digital economy has been vigorously developed around the world, bringing great convenience and high efficiency to people's daily life. Meanwhile, the security factor in digital storage and transmission also attracts great attention.
The digital encryption technology not only relates to the security of traditional information, but also is directly related to the money wealth of all groups and individuals in the form of numbers. Generating true random, non-repeatable or speculative data is of great importance to data storage and transmission security.
The generation of true random numbers has a very large number of mechanisms and forms. FIG. 1 is a diagram of a conventional true random number generation circuit. To obtain low-pass filtered output voltages with fluctuations in millivolts
Figure 617520DEST_PATH_IMAGE001
Two capacitors
Figure 407097DEST_PATH_IMAGE002
And
Figure 983571DEST_PATH_IMAGE003
in a ratio of
Figure 847622DEST_PATH_IMAGE004
Typically up to 1000 times more. Considering the influence of irrational factors such as clock feed-through (clock feed-through) and channel charge injection (channel charge injection) when the MOS switch tube is closed, the capacitance
Figure 756935DEST_PATH_IMAGE003
It cannot be too small. For example, when the capacitance
Figure 313818DEST_PATH_IMAGE005
Time, capacitance
Figure 174326DEST_PATH_IMAGE002
The value of (B) must be as high as
Figure 842068DEST_PATH_IMAGE006
The above. Thus, the capacitance
Figure 104422DEST_PATH_IMAGE002
It takes up too much chip area and increases the chip cost.
In addition, data signals that fluctuate widely between power and ground
Figure 894524DEST_PATH_IMAGE007
Output voltage changed into millivolt level fluctuation by first-order low-pass filter
Figure 383274DEST_PATH_IMAGE008
When signal, output voltage
Figure 212296DEST_PATH_IMAGE008
For data signal
Figure 204523DEST_PATH_IMAGE007
Is very low. Some non-ideal factors such as clock coupling, channel charge injection, leakage, etc. may cause the data signal
Figure 227843DEST_PATH_IMAGE007
Dead-locked at the potential of power or ground.
The information disclosed in this background section is only for enhancement of understanding of the general background of the invention and should not be taken as an acknowledgement or any form of suggestion that this information forms the prior art already known to a person skilled in the art.
Disclosure of Invention
The invention aims to provide a true random number generation circuit and a chip, which can prevent data signals
Figure 266206DEST_PATH_IMAGE009
Is deadlocked and avoids using too large on-chip capacitors, reducing cost.
To achieve the above object, an embodiment of the present invention provides a true random number generation circuit, including: a current integrator, a second order low pass filter and a comparator.
The current integrator is used for outputting an integration voltage under the control of a data signal; the second-order low-pass filter is used for low-pass filtering the integral voltage to obtain an input voltage; the comparator is used for comparing the input voltage with the reference voltage and outputting a data signal under the action of noise of the input voltage, noise of the reference voltage and input noise equivalent to the comparator, wherein the sum of the noise of the input voltage, the noise of the reference voltage and the input noise equivalent to the comparator is larger than the differential input voltage of the comparator in a random time period.
In one or more embodiments of the present invention, the current integrator includes a charging unit for providing a charging current charged by the integrating unit under control of the data signal, a discharging unit for providing a discharging current discharged by the integrating unit under control of the data signal, and an integrating unit for integrating a difference value of the charging current and the discharging current that do not overlap to obtain an integrated voltage.
In one or more embodiments of the present invention, the charging unit includes a first constant current source and a charging switch connected, and the charging switch is controlled to be turned on and off by a data signal.
In one or more embodiments of the present invention, the discharge unit includes a second constant current source and a discharge switch connected, and the closing and opening of the discharge switch is controlled by a data signal.
In one or more embodiments of the present invention, the integration unit includes an integration capacitor, a first end of the integration capacitor is connected to the charging unit and the discharging unit, a second end of the integration capacitor is connected to ground, the integration capacitor is charged by the charging current, and the integration capacitor is discharged by the discharging current.
In one or more embodiments of the present invention, the current integrator further comprises an inverter, an input terminal of the inverter is connected to an output terminal of the comparator, and an output terminal of the inverter is connected to the charging unit or the discharging unit, so that the charging unit and the discharging unit do not work in an overlapping manner.
In one or more embodiments of the present invention, the second-order low-pass filter includes a plurality of switches and capacitors, the switches are sequentially connected in series between the output end of the current integrator and the first input end of the comparator, the connection ends of two adjacent switches and the connection ends of the switches and the first input end of the comparator are respectively connected to the first end of the capacitor, and the second end of the capacitor is connected to ground.
In one or more embodiments of the present invention, the switches and the capacitors are respectively provided with four, which are respectively a first switch, a second switch, a third switch, a fourth switch, a first capacitor, a second capacitor, a third capacitor and a fourth capacitor, a first end of the first switch is connected to the output end of the current integrator, a second end of the first switch is connected to the first end of the second switch, a second end of the second switch is connected to the first end of the third switch, a second end of the third switch is connected to the first end of the fourth switch, a second end of the fourth switch is connected to the first input end of the comparator, a first end of the first capacitor is connected to the second end of the first switch and the first end of the second switch, a second end of the first capacitor is connected to ground, a first end of the second capacitor is connected to the second end of the second switch and the first end of the third switch, a first end of the third capacitor is connected to the second end of the third switch and the second end of the fourth capacitor, and a second end of the fourth capacitor is connected to the second end of the fourth switch, and the second end of the fourth capacitor is connected to the second end of the fourth switch.
In one or more embodiments of the present invention, the current integrator includes an integrating capacitor, and the second-order low-pass filter is connected to the integrating capacitor to form a third-order low-pass filter.
The invention also discloses a chip comprising the true random number generation circuit.
Compared with the prior art, the true random number generation circuit and the chip provided by the embodiment of the invention eliminate the data signal through the current integrator
Figure 10171DEST_PATH_IMAGE009
The deadlock problem reduces the bandwidth requirement of the subsequent second-order low-pass filter. The high frequency attenuation can be enhanced by the second order low pass filter, and the total capacitance and the chip area can be reduced due to the larger bandwidth.
The random number generated by the true random number generating circuit of the embodiment of the invention is related to the noise, the electrical characteristics, the relative mismatch, the power voltage and the noise of the chip, the temperature of the chip and even the electromagnetic interference outside the chip of the electronic device on the chip, thereby increasing the sensitivity of the generated true random number to the random factors, having stronger randomness of output data and having white noise in frequency spectrum.
Compared with the traditional circuit structure, the true random number generation circuit provided by the embodiment of the invention is not influenced by non-ideal factors such as electric leakage, clock coupling of a switch, charge injection and the like, avoids output data deadlock, and increases the reliability of the function and performance of the circuit.
The true random number generation circuit has the advantages of simple structure, low power consumption, small area and the like.
Drawings
FIG. 1 is a circuit schematic of a prior art true random number generating circuit.
FIG. 2 is a circuit schematic diagram of a true random number generating circuit according to an embodiment of the present invention.
FIG. 3 is a diagram illustrating random noise voltage variation of the output of a comparator according to an embodiment of the present invention.
FIG. 4 is a diagram showing simulation results of transmission frequency characteristics of low pass filters in a conventional true random number generating circuit and the true random number generating circuit of the present invention.
FIG. 5 is a diagram illustrating a distribution of differential input voltage values of comparators in a conventional true random number generating circuit.
FIG. 6 is a diagram illustrating the distribution of the differential input voltage values of the comparators in the true random number generating circuit according to the present invention.
FIG. 7 is a spectral diagram of a true random number generated by a conventional true random number generating circuit.
FIG. 8 is a spectral diagram of a true random number generated by the true random number generating circuit according to the present invention.
Detailed Description
Specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings, but it should be understood that the scope of the present invention is not limited to the specific embodiments.
Throughout the specification and claims, unless explicitly stated otherwise, the word "comprise", or variations such as "comprises" or "comprising", will be understood to imply the inclusion of a stated element or component but not the exclusion of any other element or component.
As shown in fig. 2, a true random number generating circuit includes: a current integrator 10, a second order low pass filter 20 and a comparator 30.
Wherein the current integrator 10 is used for generating a data signal
Figure 247117DEST_PATH_IMAGE010
Under the control of (2) to output an integrated voltage
Figure 316704DEST_PATH_IMAGE011
. The second order low pass filter 20 is used for integrating the voltage
Figure 140566DEST_PATH_IMAGE011
Low-pass filtering to obtain millivolt or less input voltage
Figure 688222DEST_PATH_IMAGE012
. The comparator 30 has a function of receiving an input voltage
Figure 779675DEST_PATH_IMAGE012
And receiving a reference voltage
Figure 348060DEST_PATH_IMAGE013
A comparator 30 for receiving an output voltage input voltage
Figure 767540DEST_PATH_IMAGE012
And a reference voltage
Figure 243520DEST_PATH_IMAGE013
And at the input voltage
Figure 64846DEST_PATH_IMAGE012
Of (2) noise
Figure 364984DEST_PATH_IMAGE014
Reference voltage
Figure 271760DEST_PATH_IMAGE013
Of (2) noise
Figure 489115DEST_PATH_IMAGE015
Input noise equivalent to comparator 30
Figure 555160DEST_PATH_IMAGE016
Under the action of (2) to output a data signal
Figure 137451DEST_PATH_IMAGE010
By means of data signals
Figure 921736DEST_PATH_IMAGE010
The current integrator 10 is controlled again.
As shown in fig. 3, in order to make the generated data have randomness, it is necessary to make random noise change the data signal output from the comparator 30
Figure 614885DEST_PATH_IMAGE010
. In the present embodiment, the input voltage
Figure 771322DEST_PATH_IMAGE012
Of (2) noise
Figure 524515DEST_PATH_IMAGE014
Reference voltage
Figure 530517DEST_PATH_IMAGE013
Of (2) noise
Figure 355253DEST_PATH_IMAGE015
And input noise equivalent to that of the comparator 30
Figure 5678DEST_PATH_IMAGE016
The sum is greater than the differential input voltage of comparator 30 for a random period of time
Figure 788826DEST_PATH_IMAGE017
(ignoring input offset voltage of comparator 30), differential input voltage
Figure 157490DEST_PATH_IMAGE017
I.e. the input voltage
Figure 917128DEST_PATH_IMAGE012
And a reference voltage
Figure 687638DEST_PATH_IMAGE013
Difference of (2), equivalent input noise of comparator 30
Figure 641688DEST_PATH_IMAGE016
The comparator 30 is a total noise generated by the charging and discharging of the current integrator 10, internal device noise, electrical characteristics, and factors such as ambient temperature, power supply voltage, and external electromagnetic interference. The longer the random period, the better the noise is to affect the data signal
Figure 497648DEST_PATH_IMAGE010
Differential input voltage
Figure 460925DEST_PATH_IMAGE017
=
Figure 243198DEST_PATH_IMAGE018
I.e. by
Figure 633728DEST_PATH_IMAGE019
. To achieve this effect, the input voltage needs to be adjusted
Figure 711406DEST_PATH_IMAGE012
The fluctuations of (a) are attenuated to below millivolt levels.
As shown in fig. 2, the current integrator 10 includes a charging unit 11, a discharging unit 12, an integrating unit 13, and an inverter a.
The charging unit 11 is used for charging the data signal
Figure 743953DEST_PATH_IMAGE010
Under the control of (2) to provide a charging current for charging the integration unit 13
Figure 223476DEST_PATH_IMAGE020
. The discharge unit 12 is used for data signal
Figure 486704DEST_PATH_IMAGE010
Provides a discharge current for the discharge of the integration unit 13 under the control of
Figure 176312DEST_PATH_IMAGE021
. The integration unit 13 is used for charging non-overlapping currents
Figure 356757DEST_PATH_IMAGE020
And discharge current
Figure 81000DEST_PATH_IMAGE021
Is integrated to obtain an integrated voltage
Figure 688699DEST_PATH_IMAGE011
。
Wherein the charging unit 11 comprises a first constant current source connected to
Figure 68864DEST_PATH_IMAGE022
And a charging switch
Figure 413520DEST_PATH_IMAGE023
Charging switch
Figure 867635DEST_PATH_IMAGE023
By the data signal
Figure 770869DEST_PATH_IMAGE010
And (5) controlling. The discharge unit 12 includes a second constant current source connected thereto
Figure 576014DEST_PATH_IMAGE024
And a discharge switch
Figure 222896DEST_PATH_IMAGE025
Discharge switch
Figure 531518DEST_PATH_IMAGE025
By the data signal
Figure 808915DEST_PATH_IMAGE010
And (5) controlling.
First constant current source
Figure 193367DEST_PATH_IMAGE022
Is connected to a supply voltage, a first constant current source
Figure 784885DEST_PATH_IMAGE022
Second terminal and charging switch
Figure 72647DEST_PATH_IMAGE023
Is connected with the first end of the charging switch
Figure 193050DEST_PATH_IMAGE023
Second terminal and discharge switch
Figure 35104DEST_PATH_IMAGE025
Are connected to a first terminal of a discharge switch
Figure 23789DEST_PATH_IMAGE025
Second terminal and second constant current source
Figure 307002DEST_PATH_IMAGE024
Is connected to a first terminal of a second constant current source
Figure 489984DEST_PATH_IMAGE024
Is connected to ground.
The input of inverter a is connected to the output of comparator 30 to receive the data signal
Figure 225859DEST_PATH_IMAGE010
The output terminal of the inverter a is connected to the charging unit 11 or the discharging unit 12 so that the charging unit 11 and the discharging unit 12 operate without overlapping.
In the present embodiment, the output terminal of the comparator 30 and the discharge switch
Figure 221497DEST_PATH_IMAGE025
Connected, data signal
Figure 218272DEST_PATH_IMAGE010
Direct control discharge switch
Figure 946056DEST_PATH_IMAGE025
Closing and opening of. Output end of phase inverter A and charging switch
Figure 293861DEST_PATH_IMAGE023
Connected, data signal
Figure 765294DEST_PATH_IMAGE010
Controlling the charging switch after inversion by inverter A
Figure 583952DEST_PATH_IMAGE023
Closing and opening of. By arranging inverter A to make the switch discharge
Figure 607272DEST_PATH_IMAGE025
When closed, the charging switch
Figure 52159DEST_PATH_IMAGE023
Switch-off and discharge switch
Figure 186337DEST_PATH_IMAGE025
When disconnected, the charging switch
Figure 564229DEST_PATH_IMAGE023
Closed to form a discharge switch
Figure 492871DEST_PATH_IMAGE025
And a charging switch
Figure 690634DEST_PATH_IMAGE023
Alternately opened and closed to achieve non-overlapping generation of charging current
Figure 661126DEST_PATH_IMAGE020
And discharge current
Figure 893525DEST_PATH_IMAGE021
The effect of (1).
In other embodiments, the output of inverter a may not be connected to the charge switch
Figure 993068DEST_PATH_IMAGE023
Is connected to and withDischarge switch
Figure 678127DEST_PATH_IMAGE025
Are connected.
In the present embodiment, the first constant current source
Figure 357370DEST_PATH_IMAGE026
Outputting a charging current
Figure 801864DEST_PATH_IMAGE027
Through a second constant current source
Figure 478833DEST_PATH_IMAGE028
Output discharge current
Figure 510243DEST_PATH_IMAGE029
The data signal output by the comparator 30
Figure 399702DEST_PATH_IMAGE030
The average duty cycle of (d) is:
Figure 669009DEST_PATH_IMAGE031
(ii) a The data signal can be seen
Figure 110355DEST_PATH_IMAGE030
Is no longer compared with the reference voltage of the comparator 30
Figure 770006DEST_PATH_IMAGE032
Remain consistent, but generate data signals
Figure 89254DEST_PATH_IMAGE030
Is still subject to the reference voltage
Figure 885172DEST_PATH_IMAGE032
Noise on
Figure 762998DEST_PATH_IMAGE033
The influence of (c).
As shown in fig. 2, the integratorThe element 13 comprising an integrating capacitor
Figure 441104DEST_PATH_IMAGE034
Integral capacitance
Figure 796999DEST_PATH_IMAGE034
First terminal and charging switch
Figure 713003DEST_PATH_IMAGE023
Second terminal and discharge switch
Figure 260265DEST_PATH_IMAGE025
Is connected to the first end of the housing. Integrating capacitor
Figure 628930DEST_PATH_IMAGE034
Is connected to ground, integrating capacitor
Figure 991778DEST_PATH_IMAGE034
By charging current
Figure 621342DEST_PATH_IMAGE020
Charging and integrating capacitor
Figure 716337DEST_PATH_IMAGE034
By discharge current
Figure 962511DEST_PATH_IMAGE021
Discharging is performed based on charging currents that do not overlap
Figure 535575DEST_PATH_IMAGE020
And discharge current
Figure 786690DEST_PATH_IMAGE021
Is integrated in an integrating capacitor
Figure 380482DEST_PATH_IMAGE034
Forming an integrated voltage
Figure 458160DEST_PATH_IMAGE011
。
In the present embodiment, the current integrator 10 is based on a data signal
Figure 490706DEST_PATH_IMAGE010
Can output an integrated voltage in which a DC component is amplified and a high-frequency component is attenuated
Figure 704650DEST_PATH_IMAGE011
To ensure data signal
Figure 531661DEST_PATH_IMAGE010
D.c. component of (1) and reference voltage
Figure 96634DEST_PATH_IMAGE013
So that the final input voltage of the second-order low-pass filter 20 is greatly enhanced
Figure 634670DEST_PATH_IMAGE012
For data signal
Figure 562174DEST_PATH_IMAGE010
The sensitivity to the DC component of the data signal is increased
Figure 169873DEST_PATH_IMAGE010
Attenuation of medium and high frequency components, thereby effectively preventing data signal
Figure 346777DEST_PATH_IMAGE010
The deadlock of (1).
As shown in fig. 2, the second-order low-pass filter 20 is a second-order switched capacitor low-pass filter.
Specifically, the second-order low-pass filter 20 includes a plurality of switches and capacitors, the switches are sequentially connected in series between the output terminal of the current integrator 10 and the first input terminal of the comparator 30, the connection terminals of two adjacent switches and the connection terminals of the switches and the first input terminal of the comparator 30 are respectively connected to the first ends of the capacitors, and the second ends of the capacitors are connected to ground.
The number of the switches and the number of the capacitors are four, and the switches and the capacitors are respectively the first switches
Figure 65334DEST_PATH_IMAGE035
A second switch
Figure 909662DEST_PATH_IMAGE036
The third switch
Figure 688262DEST_PATH_IMAGE037
The fourth switch
Figure 853926DEST_PATH_IMAGE038
A first capacitor
Figure 704071DEST_PATH_IMAGE039
A second capacitor
Figure 12692DEST_PATH_IMAGE040
A third capacitor
Figure 352407DEST_PATH_IMAGE041
And a fourth capacitor
Figure 113689DEST_PATH_IMAGE042
。
First switch
Figure 564262DEST_PATH_IMAGE035
Is connected to the output of the current integrator 10, i.e. a first switch
Figure 727390DEST_PATH_IMAGE035
First terminal and integrating capacitor
Figure 674224DEST_PATH_IMAGE034
Are connected to each other. First switch
Figure 313016DEST_PATH_IMAGE035
Second terminal and second switch
Figure 442646DEST_PATH_IMAGE036
Is connected to a first terminal of a second switch
Figure 584915DEST_PATH_IMAGE036
Second terminal and third switch
Figure 141798DEST_PATH_IMAGE037
Is connected to the first terminal of the third switch
Figure 205569DEST_PATH_IMAGE037
Second terminal and fourth switch
Figure 233830DEST_PATH_IMAGE038
Is connected to the fourth switch
Figure 371550DEST_PATH_IMAGE038
Is connected to a first input of a comparator 30.
First capacitor
Figure 489548DEST_PATH_IMAGE039
First terminal and first switch
Figure 447140DEST_PATH_IMAGE035
Second terminal and second switch
Figure 43206DEST_PATH_IMAGE036
Is connected to a first terminal of a first capacitor
Figure 35433DEST_PATH_IMAGE039
A second terminal of the first capacitor is connected to ground, and a second capacitor
Figure 996436DEST_PATH_IMAGE040
First terminal and second switch
Figure 353509DEST_PATH_IMAGE036
Second terminal and third switch
Figure 363053DEST_PATH_IMAGE037
Is connected to a first terminal of a second capacitor
Figure 334420DEST_PATH_IMAGE040
Is connected to ground. Second capacitor
Figure 669587DEST_PATH_IMAGE040
First terminal of (2) outputs a voltage
Figure 726404DEST_PATH_IMAGE043
。
Third capacitance
Figure 539640DEST_PATH_IMAGE041
First terminal and third switch
Figure 834355DEST_PATH_IMAGE037
Second terminal and fourth switch
Figure 435363DEST_PATH_IMAGE038
Is connected to a first terminal of a third capacitor
Figure 120422DEST_PATH_IMAGE041
The second terminal of (3) is connected to ground, a fourth capacitor
Figure 596403DEST_PATH_IMAGE038
Second terminal and fourth switch
Figure 417728DEST_PATH_IMAGE038
Is connected to the first input terminal of the comparator 30, a fourth capacitor
Figure 688172DEST_PATH_IMAGE038
Is connected to ground.
In the present embodiment, the first switch
Figure 860528DEST_PATH_IMAGE035
And a third switch
Figure 140199DEST_PATH_IMAGE037
Synchronous operation, second switch
Figure 816031DEST_PATH_IMAGE036
And a fourth switch
Figure 224754DEST_PATH_IMAGE038
Acting in synchronism and by two non-overlapping clock signals
Figure 743460DEST_PATH_IMAGE044
And
Figure 436609DEST_PATH_IMAGE045
and (5) controlling.
Integrating capacitor
Figure 357161DEST_PATH_IMAGE034
The first switch
Figure 110353DEST_PATH_IMAGE035
A first capacitor
Figure 116355DEST_PATH_IMAGE039
A second switch
Figure 613196DEST_PATH_IMAGE036
A second capacitor
Figure 889718DEST_PATH_IMAGE040
The third switch
Figure 813812DEST_PATH_IMAGE037
A third capacitor
Figure 510373DEST_PATH_IMAGE041
The fourth switch
Figure 669959DEST_PATH_IMAGE038
And a fourth capacitor
Figure 174889DEST_PATH_IMAGE038
The three-order low-pass filter is formed by connecting the two circuits, so that the true random number generating circuit has three-order low-pass filtering characteristics, and the requirement of reducing the input voltage is met on the premise of avoiding using an overlarge on-chip capacitor
Figure 394518DEST_PATH_IMAGE012
The amplitude of the fluctuation of the signal.
The transfer function of the low-pass filtering corresponding to the third-order low-pass filter is:
Figure 250479DEST_PATH_IMAGE046
wherein, in the step (A),
Figure 712291DEST_PATH_IMAGE047
for variables analysed in the discrete time domain, i.e.
Figure 337307DEST_PATH_IMAGE048
，
Figure 931099DEST_PATH_IMAGE049
As a function of the frequency,
Figure 133411DEST_PATH_IMAGE050
for two non-overlapping clock signals
Figure 510165DEST_PATH_IMAGE051
And
Figure 114322DEST_PATH_IMAGE052
of (c) is detected. And the values of the capacitances in the transfer function satisfy the relationship:
Figure 816699DEST_PATH_IMAGE053
，
Figure 7771DEST_PATH_IMAGE054
and, and
Figure 188216DEST_PATH_IMAGE055
，
Figure 115721DEST_PATH_IMAGE003
is a first capacitor
Figure 848054DEST_PATH_IMAGE003
The capacitance value of (a) is set,
Figure 634744DEST_PATH_IMAGE002
is a second capacitor
Figure 743515DEST_PATH_IMAGE002
The capacitance value of (a) is set,
Figure 197630DEST_PATH_IMAGE056
is a third capacitor
Figure 864978DEST_PATH_IMAGE056
The capacitance value of (a) is set,
Figure 138964DEST_PATH_IMAGE057
is a fourth capacitor
Figure 785846DEST_PATH_IMAGE058
The capacitance value of (a) is set,
Figure 94468DEST_PATH_IMAGE059
is an integrating capacitor
Figure 371866DEST_PATH_IMAGE059
The capacitance value of (2).
FIG. 4 is a comparison of the transfer function amplitude-frequency characteristics of the low pass filter in the conventional true random number generating circuit of FIG. 1 and the true random number generating circuit of FIG. 2.
Wherein, the simulation parameters are as follows:
Figure 523361DEST_PATH_IMAGE060
using the capacitors of FIG. 1
Figure 583721DEST_PATH_IMAGE061
Capacitor
Figure 904106DEST_PATH_IMAGE062
The integration capacitor in FIG. 3 is adopted
Figure 24509DEST_PATH_IMAGE063
，
Figure 397722DEST_PATH_IMAGE064
，
Figure 261772DEST_PATH_IMAGE065
. The simulation results according to FIG. 4 show that the true random number generating circuit of the present invention has a current integrator 10 added to it for the data signal
Figure 872882DEST_PATH_IMAGE030
Is greater than
Figure 288820DEST_PATH_IMAGE066
The attenuation of the high frequency components of (a) is increased by at least 60dB. Also, the true random number generating circuit of the present invention enhances the data signal provided by the comparator 30
Figure 24695DEST_PATH_IMAGE030
Thereby avoiding the data signal in the conventional true random number generating circuit
Figure 315606DEST_PATH_IMAGE030
Possibly deadlock problems.
FIG. 5 is a simulation result of a distribution diagram of differential input voltage values of the comparator 30 in the conventional true random number generating circuit, and FIG. 6 is a simulation result of a distribution diagram of differential input voltage values of the comparator 30 in the true random number generating circuit of the present invention. From the comparison of the simulation results of FIG. 5 and FIG. 6, it can be seen that the total capacitance value of the low-pass filter is obtained
Figure 718905DEST_PATH_IMAGE067
The variance Std Dev of the differential input voltage of the comparator 30 in the true random number generating circuit of the present invention reduced to 20pF (standard deviation) is reduced by about half compared to the variance Std Dev of the differential input voltage of the comparator 30 in the conventional true random number generating circuit.
FIG. 7 is a spectrum of a true random number output by a conventional true random number generating circuit. FIG. 8 is a spectrum of the true random number output from the true random number generating circuit of the present invention. As can be seen from FIG. 7, although up to one may be used
Figure 305744DEST_PATH_IMAGE068
The randomness ratio of the true random number generated by the traditional true random number generating circuit is poor because the frequency spectrum has the characteristic of first-order high-pass shaped (1 st-order high-pass shaped). This is because when the input differential voltage of the comparator is large, the output data of the comparator is not determined by random noise most of the time. In this case, the data signal
Figure 856811DEST_PATH_IMAGE069
Having a first order
Figure 328244DEST_PATH_IMAGE070
Characteristics of the modulated data. The spectrum of the true random number generated by the true random number generating circuit of the present invention shown in FIG. 8 approximates to a uniform white noise characteristic. This shows that the true random number generated by the true random number generating circuit of the present invention is more ideal and more random (statistical random) in statistical sense.
The invention also discloses a chip which comprises the true random number generating circuit.
The foregoing descriptions of specific exemplary embodiments of the present invention have been presented for purposes of illustration and description. It is not intended to limit the invention to the precise form disclosed, and obviously many modifications and variations are possible in light of the above teaching. The exemplary embodiments were chosen and described in order to explain certain principles of the invention and its practical application to enable one skilled in the art to make and use various exemplary embodiments of the invention and various alternatives and modifications as are suited to the particular use contemplated. It is intended that the scope of the invention be defined by the claims and their equivalents.

Claims (10)

1. A true random number generating circuit, comprising:
a current integrator for outputting an integrated voltage under control of a data signal;
a second order low pass filter for low pass filtering the integrated voltage to obtain an input voltage; and
and the comparator is used for comparing the input voltage with the reference voltage and outputting a data signal under the action of the noise of the input voltage, the noise of the reference voltage and the equivalent input noise of the comparator, and if the sum of the noise of the input voltage, the noise of the reference voltage and the equivalent input noise of the comparator is greater than the differential input voltage of the comparator in a random time period, a true random number is generated.
2. The true random number generating circuit of claim 1 wherein the current integrator includes a charging unit for providing a charging current charged by the integrating unit under control of the data signal, a discharging unit for providing a discharging current discharged by the integrating unit under control of the data signal, and an integrating unit for integrating a difference between the non-overlapping charging current and discharging current to obtain an integrated voltage.
3. The true random number generating circuit of claim 2 wherein the charging unit includes a first constant current source and a charging switch connected, the charging switch being closed and open by the data signal.
4. The true random number generating circuit of claim 2 wherein the discharge cell includes a second constant current source and a discharge switch connected, the closing and opening of the discharge switch being controlled by the data signal.
5. The true random number generating circuit of claim 2 wherein the integrating cell includes an integrating capacitor, a first terminal of the integrating capacitor is connected to the charging cell and the discharging cell, a second terminal of the integrating capacitor is connected to ground, the integrating capacitor is charged by the charging current, and the integrating capacitor is discharged by the discharging current.
6. The true random number generating circuit of claim 2 wherein the current integrator further comprises an inverter having an input coupled to the output of the comparator and an output coupled to the charging cell or the discharging cell such that the charging cell and the discharging cell do not operate in an overlapping manner.
7. The true random number generating circuit of claim 1 wherein the second order low pass filter comprises a plurality of switches and capacitors, the switches being serially connected in sequence between the output of the current integrator and the input of the comparator, the phase connection of each adjacent two of the switches and the phase connection of the switches and the input of the comparator being connected to a first terminal of the capacitor, respectively, and the second terminal of the capacitor being connected to ground.
8. The true random number generating circuit of claim 7, wherein four switches and four capacitors are provided, respectively, a first switch, a second switch, a third switch, a fourth switch, a first capacitor, a second capacitor, a third capacitor and a fourth capacitor, wherein a first terminal of the first switch is connected to the output terminal of the current integrator, a second terminal of the first switch is connected to the first terminal of the second switch, a second terminal of the second switch is connected to the first terminal of the third switch, a second terminal of the third switch is connected to the first terminal of the fourth switch, a second terminal of the fourth switch is connected to the input terminal of the comparator, a first terminal of the first capacitor is connected to the second terminal of the first switch and the first terminal of the second switch, a second terminal of the first capacitor is connected to ground, a first terminal of the second capacitor is connected to the second terminal of the second switch and the first terminal of the third switch, a first terminal of the third capacitor is connected to the second terminal of the third switch, and a second terminal of the fourth capacitor is connected to the input terminal of the comparator.
9. The true random number generating circuit of claim 1 wherein the current integrator includes an integrating capacitor and the second order low pass filter is coupled to the integrating capacitor to form a third order low pass filter.
10. A chip comprising the true random number generating circuit according to any one of claims 1 to 9.
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