CN115132602A - Semiconductor testing device and preparation method thereof - Google Patents
Semiconductor testing device and preparation method thereof Download PDFInfo
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- CN115132602A CN115132602A CN202210903571.0A CN202210903571A CN115132602A CN 115132602 A CN115132602 A CN 115132602A CN 202210903571 A CN202210903571 A CN 202210903571A CN 115132602 A CN115132602 A CN 115132602A
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- 238000012360 testing method Methods 0.000 title claims abstract description 116
- 239000004065 semiconductor Substances 0.000 title claims abstract description 37
- 238000002360 preparation method Methods 0.000 title abstract description 9
- 229910052751 metal Inorganic materials 0.000 claims abstract description 230
- 239000002184 metal Substances 0.000 claims abstract description 230
- 239000000758 substrate Substances 0.000 claims abstract description 28
- 230000007547 defect Effects 0.000 claims abstract description 20
- 230000000149 penetrating effect Effects 0.000 claims abstract description 8
- 238000000034 method Methods 0.000 claims description 21
- 238000004519 manufacturing process Methods 0.000 claims description 14
- 238000005229 chemical vapour deposition Methods 0.000 claims description 4
- 239000004020 conductor Substances 0.000 description 8
- 238000010586 diagram Methods 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000002950 deficient Effects 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012544 monitoring process Methods 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
- H01L22/32—Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/10—Measuring as part of the manufacturing process
- H01L22/14—Measuring as part of the manufacturing process for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
- H01L23/4821—Bridge structure with air gap
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- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The invention provides a semiconductor testing device and a preparation method thereof, wherein the preparation method comprises the following steps: a substrate; the first metal wiring layer is positioned on the substrate and comprises insulated interconnection metal wires and test metal wires, and the test metal wires are arranged around the interconnection metal wires; the dielectric layer covers the first metal wiring layer and the substrate, and an air gap is formed in the dielectric layer between the interconnection metal line and the test metal line; and the second metal wiring layer is positioned on the dielectric layer and is electrically connected with the interconnection metal wire through a plug penetrating through the dielectric layer. When the side wall of the plug is broken or protruded, the air gap and the dielectric layer between the plugs generate cracks due to stress between the film layers, the cracks are communicated with the plugs and the air gaps, the plugs are in an open circuit, and an operator can judge whether the plugs generate defects or not by measuring the resistance of the plugs.
Description
Technical Field
The invention relates to the field of semiconductor manufacturing, in particular to a semiconductor testing device and a preparation method thereof.
Background
As the integrated circuit is developed to the ultra-large scale integrated circuit, the circuit density inside the integrated circuit is increased, and the number of the included elements is increased, and this development trend makes two or more metal interconnection layers adopted inside the integrated circuit. The metal interconnection layers are electrically connected through the plugs, but in the production and manufacturing process, the situation that the side walls of part of the plugs protrude or are broken due to factors such as stress between film layers is found, and the defects of the plugs can cause that the metal interconnection layers cannot be effectively electrically connected, so that the yield of the semiconductor testing device is influenced.
In the prior art, a Wafer Acceptance Test (WAT) is used to electrically measure a Wafer after a process flow is finished to check whether various performances of the Wafer meet standards, but the WAT cannot detect defects of plugs, so that a semiconductor test device capable of directly measuring the performances of the plugs is required.
Disclosure of Invention
The invention aims to provide a semiconductor testing device and a preparation method thereof, which can judge whether a plug generates defects or not.
In order to achieve the above object, the present invention provides a semiconductor test device comprising:
a substrate;
the first metal wiring layer is positioned on the substrate and comprises insulated interconnection metal wires and test metal wires, and the test metal wires are arranged around the interconnection metal wires;
a dielectric layer covering the first metal wiring layer and the substrate, wherein an air gap is formed in the dielectric layer between the interconnection metal line and the test metal line;
and the second metal wiring layer is positioned on the dielectric layer and is electrically connected with the interconnection metal wire through a plug penetrating through the dielectric layer.
Optionally, the top of the air gap is higher than the top of the first metal wiring layer.
Optionally, the plug is located at one end of the interconnection metal line.
Optionally, the plugs are located at two ends of the interconnection metal line.
Optionally, the plug is located in a region between two ends of the interconnection metal line.
Optionally, the testing metal line is U-shaped, and one end of the interconnection metal line corresponding to the plug is located in the U-shaped opening of the testing metal line.
Optionally, the test metal line forms a closed pattern, and the interconnection metal line is located inside the closed pattern.
Optionally, the test metal line and the interconnection metal line are arranged in parallel.
Optionally, the distance between the test metal line and the interconnection metal line is 0.15 μm to 0.7 μm, and/or the heights of the interconnection metal line and the test metal line are 0.25 μm to 0.7 μm. Based on the same inventive concept, the invention also provides a preparation method of the semiconductor test device, which comprises the following steps:
providing a substrate;
forming a first metal wiring layer on the substrate, wherein the first metal wiring layer comprises insulated interconnection metal wires and test metal wires, and the test metal wires are arranged around the interconnection metal wires;
forming a dielectric layer on the first metal wiring layer, wherein the dielectric layer covers the first metal wiring layer and the substrate, and an air gap is formed in the dielectric layer between the interconnection metal line and the test metal line;
and forming a second metal wiring layer on the dielectric layer, wherein the second metal wiring layer is electrically connected with the interconnection metal wire through a plug penetrating through the dielectric layer.
Optionally, the interconnection metal line is formed simultaneously with the test metal line.
Optionally, the distance between the test metal line and the interconnection metal line is 0.15 μm to 0.7 μm, the heights of the interconnection metal line and the test metal line are 0.25 μm to 0.7 μm, and the dielectric layer is formed by a chemical vapor deposition process, so that the air gap is formed in the dielectric layer between the interconnection metal line and the test metal line.
Optionally, after forming the second metal wiring layer, the method further includes:
and testing the resistance of the plug, and judging whether the plug generates defects according to the resistance of the plug.
Optionally, the defects of the plug include a break of the plug and a protrusion of a sidewall of the plug.
The invention provides a semiconductor testing device and a preparation method thereof, wherein the preparation method comprises the following steps: a substrate; the first metal wiring layer is positioned on the substrate and comprises interconnection metal wires and test metal wires, the test metal wires are arranged around the interconnection metal wires, and the test metal wires are insulated from the interconnection metal wires; the dielectric layer is positioned on the first metal wiring layer and covers the first metal wiring layer, and an air gap is formed in the dielectric layer between the interconnection metal wire and the test metal wire; and the second metal wiring layer is positioned on the dielectric layer and is electrically connected with the interconnection metal wire through a plug. When the plug has defects such as side wall protrusion or breakage, cracks are generated on the air gap and the dielectric layer between the plugs due to stress between the film layers, the cracks are communicated with the plugs and the air gaps, the plugs are disconnected, and an operator can judge whether the plugs have defects or not by measuring the resistance of the plugs.
Drawings
FIGS. 1-5 are top views of a semiconductor test device according to an embodiment of the present invention;
FIG. 6 is a flow chart of a method for fabricating a semiconductor test device according to an embodiment of the present invention;
fig. 7 to 12 are schematic structural diagrams corresponding to respective steps of a method for manufacturing a semiconductor test device according to an embodiment of the present invention;
wherein the drawings are described as follows:
100-a substrate; 102-an insulating layer; 103-a first layer of conductive material; 104-interconnect metal lines; 106-test metal lines; 108-a dielectric layer; 109-air gap; 110-a via; 112-a plug; 114-second metal routing layer.
Detailed Description
The following describes in more detail embodiments of the present invention with reference to the schematic drawings. The advantages and features of the present invention will become more apparent from the following description. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.
In the following, the terms "first," "second," and the like are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the terms so used are interchangeable under appropriate circumstances. Similarly, if a method described herein comprises a series of steps, and the steps presented herein are not necessarily the only order in which they may be performed, some of the described steps may be omitted and/or some other steps not described herein may be added to the method.
Fig. 12 is a schematic structural diagram of the semiconductor test device provided in this embodiment, and as shown in fig. 12, the present embodiment provides a semiconductor test device, including: substrate 100, a first metal wiring layer, a dielectric layer 108 and a second metal wiring layer 114.
Specifically, the substrate 100 further includes an insulating layer 102, a gate structure is disposed in the insulating layer 102, and the first metal wiring layer is located on the insulating layer 102 and electrically connected to the gate structure through an electrical connector.
The first metal wiring layer comprises an interconnection metal line 104 and a test metal line 106, the interconnection metal line 104 is electrically connected with the gate structure, the test metal line 106 is insulated from the gate structure and the interconnection metal line 104, the distance between the test metal line 106 and the interconnection metal line 104 is 0.15-0.7 μm, the heights of the interconnection metal line 104 and the test metal line 106 are 0.25-0.7 μm, and a groove between the interconnection metal line 104 and the test metal line 106 has a larger depth-to-width ratio.
Further, the dielectric layer 108 covers the first metal wiring layer, and an air gap 109 is formed in the dielectric layer 108 between the interconnection metal line 104 and the test metal line 106, and a top surface of the air gap 109 is higher than a top surface of the first metal wiring layer.
The second metal wiring layer 114 is located on the dielectric layer 108 and is electrically connected to the interconnection metal line through a plug 112 penetrating the dielectric layer.
Fig. 1 to 3 are top views of the semiconductor testing device provided in this embodiment, wherein fig. 10 is a cross-sectional view of the semiconductor testing device in fig. 1 to 3 along the line a to a'. As shown in fig. 1, the plug 112 is located at one end of the interconnection metal line 104, the test metal line 106 is disposed around the interconnection metal line 104, the test metal line 106 is U-shaped, and one end of the interconnection metal line 104 corresponding to the plug 112 is located in the U-shaped opening of the test metal line 106.
As shown in fig. 2, when the plug 112 is located in the region between the two ends of the interconnection metal line 104, the test metal line 106 is disposed parallel to the interconnection metal line 104; as shown in fig. 3, when the plugs 112 are located at two ends of the interconnection metal line 104, the test metal line 106 forms a closed pattern around the interconnection metal line 104, and the interconnection metal line 104 is located inside the closed pattern to ensure that the air gaps 109 are located outside the plugs 112. Fig. 1 to 3 only illustrate the preferred embodiment of the present invention, and the arrangement of the test metal line 106 in the present invention is not affected by the position of the plug 112, and only the air gap 109 is ensured in the dielectric layer between the plug 112 and the test metal line 106.
Fig. 4 and 5 are top views of the semiconductor test device provided in this embodiment, and as shown in fig. 4 and 5, when the distance between the interconnection metal lines 104 is short, the test metal lines 106 may form a parallel array as shown in fig. 4 and 5, thereby reducing the process cost and improving the monitoring efficiency. It should be understood that the test metal lines 106 in the U shape and the test metal lines 106 in the closed pattern may be alternatively disposed, and the present invention is not limited thereto.
Note that the first metal wiring layer, the plugs 112, and the air gaps 109 are not actually visible in a plan view, and fig. 1 to 3 are only intended to show the positions and connection relationships among the first metal wiring layer, the plugs 112, the air gaps 109, and the second metal wiring layer 114 from a plan view.
In the manufacturing process, the plug 112 may have defects such as sidewall protrusion or fracture due to process and stress problems between films, the defects of the plug 112 may cause poor connection between the first metal wiring layer and the second metal wiring layer 114, and the defects of the plug 112 are difficult to detect by conventional detection means.
In the present embodiment, the test metal line 106 is disposed around the periphery of the interconnection metal line 104, the distance between the test metal line 106 and the interconnection metal line 104 is small, and the trench between the interconnection metal line 104 and the test metal line 106 has a large aspect ratio, so that when the dielectric layer 108 is formed by a process with a weak filling capability, the air gap 109 is formed between the interconnection metal line 104 and the test metal line 106 due to the surface tension of the material during the formation of the dielectric layer 108. In the longitudinal direction, the top surface of the air gap 109 is higher than the top surface of the first metal wiring layer, so that the air gap 109 and the plug 112 have partial area overlap; in the transverse direction, the distance between the air gap 109 and the plug 112 is small, and if the plug 112 has defects such as sidewall protrusion or fracture during the formation process, the dielectric layer 108 between the air gap 109 and the plug 112 may be cracked, resulting in cracks connected with the plug 112. When the air gap 109 and the plug 112 are communicated through the crack, the plug 112 is disconnected, and an operator can test whether the plug 112 is defective or not by measuring the resistance.
Fig. 6 is a flowchart of a method for manufacturing a semiconductor test device according to this embodiment, and as shown in fig. 6, the present invention provides a method for manufacturing a semiconductor test device, including:
step S1: providing a substrate;
step S2: forming a first metal wiring layer on the substrate, wherein the first metal wiring layer comprises insulated interconnection metal wires and test metal wires, and the test metal wires are arranged around the interconnection metal wires;
step S3: forming a dielectric layer on the first metal wiring layer, wherein the dielectric layer covers the first metal wiring layer and the substrate, and an air gap is formed in the dielectric layer between the interconnection metal line and the test metal line;
step S4: and forming a second metal wiring layer on the dielectric layer, wherein the second metal wiring layer is electrically connected with the interconnection metal wire through a plug penetrating through the dielectric layer.
Fig. 7 to 12 are schematic structural diagrams corresponding to respective steps of a manufacturing method of a semiconductor test device provided in this embodiment, and the manufacturing method of a semiconductor test device provided in this embodiment is described in more detail below with reference to fig. 5 to 10, in which preferred embodiments of the present invention are illustrated.
As shown in fig. 7, a substrate 100 is provided, and an insulating layer 102 is formed on the substrate 100, wherein the insulating layer 102 has a gate structure (not shown).
As shown in fig. 8 and 9, a first conductive material layer 103 is formed on the insulating layer 102, and the first conductive material layer 103 is etched to form a first metal wiring layer, where the first metal wiring layer includes an interconnection metal line 104 and a test metal line 106, the test metal line 106 and the interconnection metal line 104 are formed simultaneously, and the test metal line 106 and the interconnection metal line 104 are insulated from each other.
As shown in fig. 10, a dielectric layer 108 is formed on the first metal wiring layer by using a chemical vapor deposition process, and the dielectric layer 108 covers the first metal wiring layer and the substrate 100. When the dielectric layer 108 is formed, because the filling capability of the chemical vapor deposition process is weak, and the trench between the interconnection metal line 104 and the test metal line 106 has a large aspect ratio, when the dielectric layer 108 is filled between the interconnection metal line 104 and the test metal line 106, an air gap 109 is formed, and the top surface of the air gap 109 is higher than the top surface of the first metal wiring layer. It should be appreciated that the air gap 109 may reduce the parasitic capacitance between the interconnect metal line 104 and the test metal line 106 due to the very small dielectric constant of air.
As shown in fig. 11 and 12, the dielectric layer 108 is etched, and a via 110 penetrating through the dielectric layer 108 is formed in the dielectric layer 108, where the via 110 exposes the interconnection metal line 104. Then forming a second conductive material layer on the dielectric layer 108, wherein the second conductive material layer also fills the through hole 110, a portion of the second conductive material layer located in the through hole 110 forms a plug 112, and a portion of the second conductive material layer located on the dielectric layer 108 forms a second metal wiring layer 114; the interconnection metal line 104 is electrically connected to the second metal wiring layer 114 through the plug 112, and the second metal wiring layer 114 is insulated from the test metal line 106.
Further, after forming the second metal wiring layer 114, the method further includes: the resistance of the plug 112 is measured, and whether the plug generates a defect is determined according to the resistance of the plug.
Since the second conductive material is generally a stack of titanium, titanium nitride and tungsten, which have high stress, when the plug 112 and the second metal wiring layer 114 are formed, the plug 112 may have defects such as sidewall protrusion or fracture due to stress between film layers. The dielectric layer 108 between the plugs 112 and the air gaps 109 is thin, and when the plugs 112 have defects such as sidewall protrusion or fracture, the dielectric layer 108 between the air gaps 109 and the plugs 112 may be cracked, and cracks communicating with the plugs 112 may be generated. The crack and the air gap 109 may open the plug 112, and an operator may test whether the plug 112 is defective by measuring the resistance.
In summary, the present invention provides a semiconductor test device and a method for manufacturing the same, including: a substrate 100; a first metal wiring layer on the substrate 100, the first metal wiring layer including an interconnection metal line 104 and a test metal line 106, the test metal line 106 being disposed around the interconnection metal line 104, and the test metal line 106 being insulated from the interconnection metal line 104; a dielectric layer 108 on and covering the first metal wiring layer, wherein an air gap 109 is formed in the dielectric layer 108 between the interconnection metal line 104 and the test metal line 106; and a second metal wiring layer 114 on the dielectric layer 108 and electrically connected to the interconnection metal line 104 through a plug 112. When the plug 112 has defects such as sidewall protrusion or fracture, a crack is generated between the air gap 109 and the dielectric layer 108 between the plugs 112 due to stress between film layers, the crack communicates the plug 112 and the air gap 109, so that the plug 112 is open-circuited, and an operator can determine whether the plug 112 has defects by measuring the resistance of the plug 112. In addition, the layout condition between the test metal line 106 and the interconnection metal line 104 is changed according to the position of the plug 112, so that an air gap 109 is ensured outside the plug 112, and whether the plug 112 generates defects is judged more accurately.
The above description is only a preferred embodiment of the present invention, and does not limit the present invention in any way. Any person skilled in the art can make any equivalent substitutions or modifications on the technical solutions and technical contents disclosed in the present invention without departing from the scope of the technical solutions of the present invention, and still fall within the protection scope of the present invention without departing from the technical solutions of the present invention.
Claims (14)
1. A semiconductor test device, comprising:
a substrate;
the first metal wiring layer is positioned on the substrate and comprises insulated interconnection metal wires and test metal wires, and the test metal wires are arranged around the interconnection metal wires;
a dielectric layer covering the first metal wiring layer and the substrate, wherein an air gap is formed in the dielectric layer between the interconnection metal line and the test metal line;
and the second metal wiring layer is positioned on the dielectric layer and is electrically connected with the interconnection metal wire through a plug penetrating through the dielectric layer.
2. The semiconductor test device of claim 1, wherein a top of the air gap is higher than a top of the first metal wiring layer.
3. The semiconductor test device of claim 1, wherein the plug is located at an end of the interconnect metal line.
4. The semiconductor test device of claim 1, wherein said plugs are located at both ends of said interconnection metal line.
5. The semiconductor test device of claim 1, wherein the plug is located in a region between two ends of the interconnection metal line.
6. The semiconductor test device according to any one of claims 3 to 5, wherein the test metal line is U-shaped, and an end of the interconnection metal line corresponding to the plug is located in a U-shaped opening of the test metal line.
7. A semiconductor test device as claimed in any one of claims 3 to 5, characterized in that the test metal lines form a closed pattern, the interconnection metal lines being located inside the closed pattern.
8. The semiconductor test device of claim 5, wherein the test metal line is disposed in parallel with the interconnect metal line.
9. The semiconductor test device of claim 1, wherein a distance between the test metal line and the interconnection metal line is 0.15 μm to 0.7 μm, and/or a height of the interconnection metal line and the test metal line is 0.25 μm to 0.7 μm.
10. A method for manufacturing a semiconductor test device, comprising:
providing a substrate;
forming a first metal wiring layer on the substrate, wherein the first metal wiring layer comprises insulated interconnection metal wires and test metal wires, and the test metal wires are arranged around the interconnection metal wires;
forming a dielectric layer on the first metal wiring layer, wherein the dielectric layer covers the first metal wiring layer and the substrate, and an air gap is formed in the dielectric layer between the interconnection metal line and the test metal line;
and forming a second metal wiring layer on the dielectric layer, wherein the second metal wiring layer is electrically connected with the interconnection metal wire through a plug penetrating through the dielectric layer.
11. The method of manufacturing a semiconductor test device according to claim 10, wherein the interconnection metal line is formed simultaneously with the test metal line.
12. The method according to claim 10, wherein a distance between the test metal line and the interconnection metal line is 0.15 μm to 0.7 μm, a height of the interconnection metal line and the test metal line is 0.25 μm to 0.7 μm, and the dielectric layer is formed by a chemical vapor deposition process so that the air gap is provided in the dielectric layer between the interconnection metal line and the test metal line.
13. The method for manufacturing a semiconductor test device according to claim 10, further comprising, after forming the second metal wiring layer:
and testing the resistance of the plug, and judging whether the plug generates defects according to the resistance of the plug.
14. The method of manufacturing a semiconductor test device according to claim 13, wherein the defects of the plug include a break of the plug and a protrusion of a sidewall of the plug.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN202210903571.0A CN115132602A (en) | 2022-07-28 | 2022-07-28 | Semiconductor testing device and preparation method thereof |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202210903571.0A CN115132602A (en) | 2022-07-28 | 2022-07-28 | Semiconductor testing device and preparation method thereof |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20130320549A1 (en) * | 2012-05-31 | 2013-12-05 | Hyo-Seok Lee | Semiconductor device with air gap and method for fabricating the same |
| CN104321856A (en) * | 2012-03-27 | 2015-01-28 | 科磊股份有限公司 | Method and apparatus for detecting buried defects |
| CN205231023U (en) * | 2015-12-18 | 2016-05-11 | 中芯国际集成电路制造（天津）有限公司 | Conductive plunger resistance measurement structure |
| CN206134676U (en) * | 2016-11-03 | 2017-04-26 | 中芯国际集成电路制造(北京)有限公司 | Detect cracked test structure between metal level |
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- 2022-07-28 CN CN202210903571.0A patent/CN115132602A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104321856A (en) * | 2012-03-27 | 2015-01-28 | 科磊股份有限公司 | Method and apparatus for detecting buried defects |
| US20130320549A1 (en) * | 2012-05-31 | 2013-12-05 | Hyo-Seok Lee | Semiconductor device with air gap and method for fabricating the same |
| CN205231023U (en) * | 2015-12-18 | 2016-05-11 | 中芯国际集成电路制造（天津）有限公司 | Conductive plunger resistance measurement structure |
| CN206134676U (en) * | 2016-11-03 | 2017-04-26 | 中芯国际集成电路制造(北京)有限公司 | Detect cracked test structure between metal level |
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