CN115128646A - Low-power-consumption capturing method and system applied to Beidou navigation chip - Google Patents

Low-power-consumption capturing method and system applied to Beidou navigation chip Download PDF

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Publication number
CN115128646A
CN115128646A CN202210807042.0A CN202210807042A CN115128646A CN 115128646 A CN115128646 A CN 115128646A CN 202210807042 A CN202210807042 A CN 202210807042A CN 115128646 A CN115128646 A CN 115128646A
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China
Prior art keywords
system clock
capture
unit
sampling
tracking
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Pending
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CN202210807042.0A
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Chinese (zh)
Inventor
傅东
朱佳
宋佳驹
翁秀梅
高超
丁杰
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Changsha Jinwei Information Technology Co ltd
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Changsha Jinwei Information Technology Co ltd
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Priority to CN202210807042.0A priority Critical patent/CN115128646A/en
Publication of CN115128646A publication Critical patent/CN115128646A/en
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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
    • G01S19/00—Satellite radio beacon positioning systems; Determining position, velocity or attitude using signals transmitted by such systems
    • G01S19/01—Satellite radio beacon positioning systems transmitting time-stamped messages, e.g. GPS [Global Positioning System], GLONASS [Global Orbiting Navigation Satellite System] or GALILEO
    • G01S19/13—Receivers
    • G01S19/24—Acquisition or tracking or demodulation of signals transmitted by the system
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D30/00—Reducing energy consumption in communication networks
    • Y02D30/70—Reducing energy consumption in communication networks in wireless communication networks

Abstract

The invention discloses a low-power-consumption capturing system applied to a Beidou navigation chip, which comprises a capturing engine module, a tracking engine module and a system clock circuit module, wherein the low-power-consumption capturing system also comprises an N frequency divider; the capture engine module comprises a first sampling buffer unit, a capture calculation unit and a preprocessing unit, wherein the first sampling buffer unit is connected with the capture calculation unit through the N frequency divider, a system clock of the system clock circuit module is used, a frequency-divided clock after N frequency division is performed on the system clock, the preprocessing unit is connected with the system clock circuit module, and the system clock of the system clock circuit module is used: the trace engine module comprises a trace calculation unit and a second sampling buffer unit, and the trace calculation unit and the second sampling buffer unit are connected with the system clock of the system clock circuit module. The power consumption and the area of the capture engine are greatly reduced by optimizing a clock framework and realizing frequency self-adaption.

Description

Low-power-consumption capturing method and system applied to Beidou navigation chip
Technical Field
The invention relates to the technical field of communication, in particular to a low-power-consumption capturing method and system applied to a Beidou navigation chip.
Background
Under the background of rapid development and increasingly severe competition in the satellite navigation field, the performance problem of the satellite navigation system gradually draws wide attention, and the performance of the satellite navigation system directly influences the operation and service level of the satellite navigation system. The navigation chip is an important part of the navigation system, and the performance improvement of the navigation chip is important to the performance improvement of the whole navigation system. And the power consumption is a very important performance index of the navigation chip. The Beidou navigation chip usually comprises a capture engine and a tracking engine, and the power consumption of the units accounts for a large proportion of the power consumption of the whole navigation chip, so that the low-power-consumption application scene of the navigation chip is limited.
The existing capture engine implementation has certain limitation on the application of a navigation chip, as shown in fig. 1, in the existing Beidou navigation chip clock architecture, the capture engine and the tracking engine use the same system clock. The working frequency of the capture engine is the same as that of the tracking engine; the tracking performance requirement is high, the tracking engine works in a high-frequency scene, and the capture engine passively works in a high frequency and cannot independently reduce the frequency, so that the power consumption is increased; in addition, the sample buffer of the capture engine is large, which further increases the chip power consumption. If the power consumption is reduced by simply reducing the system frequency, the high-performance application scene cannot be met.
In view of the above, a new low-power-consumption capturing method and system applied to the beidou navigation chip are needed.
Disclosure of Invention
The invention mainly aims to provide a novel low-power-consumption capturing method and system applied to a Beidou navigation chip, so as to solve the technical problems, realize the capture of an engine self-adaptive working clock, solve the contradiction between a high-performance application scene and a low-power-consumption application scene, realize the flexible switching of the two application scenes, reduce the area by sharing a cache and further reduce the power consumption.
In order to achieve the purpose, the low-power-consumption capturing system applied to the Beidou navigation chip comprises a capturing engine module, a tracking engine module and a system clock circuit module, and further comprises an N frequency divider arranged between the capturing engine module and the system clock circuit module; the capture engine module comprises a first sampling buffer unit, a capture calculation unit and a preprocessing unit, wherein the first sampling buffer unit is connected with the capture calculation unit through the N frequency divider, a system clock of the system clock circuit module is used, a frequency-divided clock after N frequency division is performed on the system clock, the preprocessing unit is connected with the system clock circuit module, and the system clock of the system clock circuit module is used: the tracking engine module comprises a tracking calculation unit and a second sampling cache unit, and the tracking calculation unit and the second sampling cache unit are connected with the system clock of the system clock circuit module.
Further, the maximum bit width of the first sample buffer unit is the number of bits of single sample data multiplied by the N value of the N divider.
Further, the second sampling cache unit is used for caching the cache data of the tracking engine module when the Beidou navigation chip is in a tracking state; when the Beidou navigation chip is in a capture state, all or part of the cache space of the second sampling cache unit is used for caching the cache data of the capture engine module.
The invention also provides a low-power-consumption capturing method for the low-power-consumption capturing system applied to the Beidou navigation chip, which comprises the following steps:
when the Beidou navigation chip is in a tracking state, the capturing engine module and the tracking engine module are controlled to simultaneously use a system clock of the system clock circuit module;
when the Beidou navigation chip is in a capture state, the first sampling cache unit is connected with the capture calculation unit through the N frequency divider, and a frequency division clock obtained after a system clock of the system clock circuit module is subjected to N frequency division is used.
Further, the method also comprises the following steps: and when the capture state is converted into the tracking state, setting the bit width of the first sampling cache unit to be equal to the number of bits of single sampling data multiplied by the N value of the N frequency divider according to the current N frequency division value of the N frequency divider so as to perform delayed reading on the data generated by the capture calculation unit.
The low-power-consumption capturing system applied to the Beidou navigation chip in the technical scheme of the invention comprises a capturing engine module, a tracking engine module and a system clock circuit module, and further comprises an N frequency divider arranged between the capturing engine module and the system clock circuit module; the capture engine module comprises a first sampling buffer unit, a capture calculation unit and a preprocessing unit, wherein the first sampling buffer unit is connected with the capture calculation unit through the N frequency divider, a system clock of the system clock circuit module is used, a frequency-divided clock after N frequency division is performed on the system clock, the preprocessing unit is connected with the system clock circuit module, and the system clock of the system clock circuit module is used: the tracking engine module comprises a tracking calculation unit and a second sampling cache unit, and the tracking calculation unit and the second sampling cache unit are connected with the system clock of the system clock circuit module. When the Beidou navigation chip is in a tracking state, controlling the capture engine module and the tracking engine module to simultaneously use a system clock of the system clock circuit module; when the Beidou navigation chip is in a capture state, the first sampling cache unit is connected with the capture calculation unit through the N frequency divider, and a frequency division clock obtained after a system clock of the system clock circuit module is subjected to N frequency division is used. The invention solves the contradiction between a high-performance application scene and a low-power consumption application scene by capturing the self-adaptive working clock of the engine, realizes the flexible switching of the two application scenes, and further reduces the power consumption by sharing the cache to reduce the area.
Drawings
FIG. 1 is a schematic diagram of a clock architecture applied to a Beidou navigation chip acquisition system in the prior art;
fig. 2 is a schematic diagram of a clock architecture applied to a low-power-consumption capturing system of a beidou navigation chip in an embodiment of the invention;
the objects, features and advantages of the present invention will be further explained with reference to the accompanying drawings.
Detailed Description
It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
In the following description, suffixes such as "module", "component", or "unit" used to denote elements are used only for facilitating the explanation of the present invention, and have no specific meaning in itself. Thus, "module", "component" or "unit" may be used mixedly.
Referring to fig. 2, in order to achieve the above object, the low power consumption capturing system applied to a beidou navigation chip according to the present invention includes a capturing engine module, a tracking engine module, a system clock circuit module, and an N-frequency divider disposed between the capturing engine module and the system clock circuit module; the capture engine module comprises a first sampling buffer unit, a capture calculation unit and a preprocessing unit, wherein the first sampling buffer unit is connected with the capture calculation unit through the N frequency divider, a system clock of the system clock circuit module is used, a frequency-divided clock after N frequency division is performed on the system clock, the preprocessing unit is connected with the system clock circuit module, and the system clock of the system clock circuit module is used: the trace engine module comprises a trace calculation unit and a second sampling buffer unit, and the trace calculation unit and the second sampling buffer unit are connected with the system clock of the system clock circuit module.
Specifically, the preprocessing unit of the capture engine module uses the same clock as the trace engine module, i.e., a system clock; the first sampling buffer unit and all the capturing calculation units of the capturing engine module use the clock after the system clock is divided by N. Different N is selected to enable the capture engine to work in different low-frequency clocks, so that flexible configuration can be achieved according to power consumption application scenarios.
Further, the maximum bit width of the first sample buffer unit is the number of bits of single sample data multiplied by the N value of the N divider.
Specifically, firstly, for the adaptive frequency division ratio, the same address buffers a plurality of sampling data; however, each address bit width is not a single sample datum multiplied by N, and the number of samples stored in each address is fixed because the supported NSHI 1-15 is variable, so that the processing under 15 frequency division can be met.
Specifically, the capture engine module supports the range of N frequency division in the clock architecture diagram to be 1-15, and the capture engine module does not sense the frequency division ratio and can be adaptive to any frequency division of 1-15 to realize the capture function. Firstly, a sampling clock is a high-frequency clock, an internal processing clock of a capture engine is N frequency division of an input sampling clock, and N is 1-15; secondly, a plurality of samples are spliced together (such as 64 samples) by an input sampling clock and latched, and the samples are written into a cache working in an N frequency division clock after reaching the bit width of the cache, so that frequency division self-adaptation is realized; in addition, there is a clock domain conversion process of the control signal.
The capture transition tracking requires that the sampling point data used by the two engines are aligned, so that the clock used by the preprocessing unit in the capture engine module is the same as the clock of the tracking engine module, and the two engines can align the position of the sampling point data during transition tracking after capture, thereby correctly completing the transition tracking function. Specifically, first, the preprocessing unit is an internal function of the capture engine, and is also operational when captured alone; secondly, in a stable tracking state, the capture engine can be turned off and then turned on when the capture engine needs to be captured again; moreover, after the acquisition engine finishes the acquisition, the code phase and frequency information are transmitted to a tracking engine to start tracking calculation; in addition, the capture engine and the trace engine use the same samples, so the capture engine will pass sample count information to the trace engine, which is implemented in the pre-processing unit, so in order for the capture and trace engines to align the sample locations, the pre-processing unit needs to use the same clock as the trace engine.
Other parts of the capture engine module, including sample buffering and capture computation, use the divided clock. Therefore, the problem that the preprocessing unit and the sampling buffer unit can store in a self-adaptive mode within the range of the clock frequency dividing ratio of 1-15 needs to be solved. The invention can buffer a plurality of sampling data by setting proper bit width of the sampling buffer, and realizes clock conversion between the preprocessing unit and the first sampling buffer unit by a method of accumulating a plurality of sampling data and then writing the sampling data into the sampling buffer, and can be self-adaptive to different clock frequency division ratios.
Further, the second sampling cache unit is used for caching the cache data of the tracking engine module when the Beidou navigation chip is in a tracking state; when the Beidou navigation chip is in a capture state, all or part of the cache space of the second sampling cache unit is used for caching the cache data of the capture engine module.
The capture engine module and the trace engine module need to buffer a large amount of sample data to realize respective functions. Considering that the cache of the tracking engine module is not fully used in real time, especially not fully used before the trace is transferred, a part of the cache of the tracking engine module can be shared with the capture engine module, and the size of the sampling cache of the capture engine can be correspondingly reduced, thereby reducing the power consumption. Because the capture engine module and the tracking engine module work at different clock frequencies, the process of clock conversion is needed. Under the condition of enabling the shared cache, the capture engine module writes the sampling points into the shared cache through the preprocessing unit, and the sampling points and the shared cache have the same working frequency and do not need special processing. The computation processing unit of the capture engine module operates under the N-division clock of the trace engine module, and thus, clock conversion is required when the capture engine module reads the sampling data from the shared cache. The method adopted by the invention is to use the low-frequency clock of the capture engine to generate a reading control signal, and register the read data in the low-frequency clock domain to match the delay time required by the capture engine, thereby realizing the conversion of the clock domain. Specifically, first, there is tracking after the prior acquisition. During capturing, the tracking engine is not started, so that partial cache of the tracking engine can be borrowed for storing more samples when needed, namely cache sharing; secondly, after the acquisition is finished, transmitting the code phase and frequency information of the acquisition result to a tracking engine; then, the tracking engine carries out tracking calculation according to the information provided by the capturing engine; moreover, when the tracking engine changes from a stable tracking state to an unlocked state, the capturing engine needs to be started to capture again, and the tracking is transferred again after the capturing is successful.
The invention also provides a low-power-consumption capturing method for the low-power-consumption capturing system applied to the Beidou navigation chip, which comprises the following steps of:
when the Beidou navigation chip is in a tracking state, controlling the capture engine module and the tracking engine module to simultaneously use a system clock of the system clock circuit module;
when the Beidou navigation chip is in a capture state, the first sampling cache unit is connected with the capture calculation unit through the N frequency divider, and a frequency division clock obtained after a system clock of the system clock circuit module is subjected to N frequency division is used.
Further, the method also comprises the following steps: and when the capture state is converted into the tracking state, setting the bit width of the first sampling cache unit to be equal to the number of bits of single sampling data multiplied by the N value of the N frequency divider according to the current N frequency division value of the N frequency divider so as to perform delayed reading on the data generated by the capture calculation unit.
The low-power-consumption capturing system applied to the Beidou navigation chip in the technical scheme of the invention comprises a capturing engine module, a tracking engine module and a system clock circuit module, and further comprises an N frequency divider arranged between the capturing engine module and the system clock circuit module; the capture engine module comprises a first sampling buffer unit, a capture calculation unit and a preprocessing unit, wherein the first sampling buffer unit is connected with the capture calculation unit through the N frequency divider, a system clock of the system clock circuit module is used, a frequency-divided clock after N frequency division is performed on the system clock, the preprocessing unit is connected with the system clock circuit module, and the system clock of the system clock circuit module is used: the tracking engine module comprises a tracking calculation unit and a second sampling cache unit, and the tracking calculation unit and the second sampling cache unit are connected with the system clock of the system clock circuit module. When the Beidou navigation chip is in a tracking state, controlling the capture engine module and the tracking engine module to simultaneously use a system clock of the system clock circuit module; when the Beidou navigation chip is in a capturing state, the first sampling cache unit is connected with the capturing calculation unit through the N frequency divider, and a frequency division clock obtained by dividing a system clock of the system clock circuit module by N frequency is used. The invention solves the contradiction between a high-performance application scene and a low-power consumption application scene by capturing the self-adaptive working clock of the engine, realizes the flexible switching of the two application scenes, and further reduces the power consumption by sharing the cache to reduce the area.
In the description herein, references to the description of the term "one embodiment," "another embodiment," or "first through xth embodiments," etc., mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, method steps, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
The above-mentioned serial numbers of the embodiments of the present invention are merely for description and do not represent the merits of the embodiments.
The above description is only a preferred embodiment of the present invention, and not intended to limit the scope of the present invention, and all modifications of equivalent structures and equivalent processes, which are made by using the contents of the present specification and the accompanying drawings, or directly or indirectly applied to other related technical fields, are included in the scope of the present invention.

Claims (5)

1. A low-power-consumption capturing system applied to a Beidou navigation chip comprises a capturing engine module, a tracking engine module and a system clock circuit module, and is characterized by further comprising an N frequency divider arranged between the capturing engine module and the system clock circuit module; the capture engine module comprises a first sampling buffer unit, a capture calculation unit and a preprocessing unit, wherein the first sampling buffer unit is connected with the capture calculation unit through the N frequency divider, a system clock of the system clock circuit module is used, a frequency-divided clock after N frequency division is performed on the system clock, the preprocessing unit is connected with the system clock circuit module, and the system clock of the system clock circuit module is used: the tracking engine module comprises a tracking calculation unit and a second sampling cache unit, and the tracking calculation unit and the second sampling cache unit are connected with the system clock of the system clock circuit module.
2. The low-power capture system applied to the Beidou navigation chip according to claim 1, wherein the maximum bit width of the first sampling buffer unit is the number of bits of single sampling data multiplied by the N value of the N divider.
3. The low-power-consumption capturing system applied to the Beidou navigation chip according to claim 1, wherein the second sampling cache unit is used for caching cache data of the tracking engine module when the Beidou navigation chip is in a tracking state; when the Beidou navigation chip is in a capture state, all or part of the cache space of the second sampling cache unit is used for caching the cache data of the capture engine module.
4. A low-power-consumption capturing method for the low-power-consumption capturing system applied to the Beidou navigation chip according to any one of claims 1 to 3, and the method is characterized by comprising the following steps of:
when the Beidou navigation chip is in a tracking state, the capturing engine module and the tracking engine module are controlled to simultaneously use a system clock of the system clock circuit module;
when the Beidou navigation chip is in a capture state, the first sampling cache unit is connected with the capture calculation unit through the N frequency divider, and a frequency division clock obtained after a system clock of the system clock circuit module is subjected to N frequency division is used.
5. The low power capture method of claim 4, further comprising the steps of: and when the capture state is converted into the tracking state, setting the bit width of the first sampling cache unit to be equal to the number of bits of single sampling data multiplied by the N value of the N frequency divider according to the current N frequency division value of the N frequency divider so as to perform delayed reading on the data generated by the capture calculation unit.
CN202210807042.0A 2022-07-07 2022-07-07 Low-power-consumption capturing method and system applied to Beidou navigation chip Pending CN115128646A (en)

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CN202210807042.0A CN115128646A (en) 2022-07-07 2022-07-07 Low-power-consumption capturing method and system applied to Beidou navigation chip

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CN115128646A true CN115128646A (en) 2022-09-30

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