CN115117150B - GaN HEMT power device and preparation method thereof - Google Patents

GaN HEMT power device and preparation method thereof Download PDF

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CN115117150B
CN115117150B CN202211015797.3A CN202211015797A CN115117150B CN 115117150 B CN115117150 B CN 115117150B CN 202211015797 A CN202211015797 A CN 202211015797A CN 115117150 B CN115117150 B CN 115117150B
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gan
substrate
power device
algan
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CN115117150A (en
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王中健
曹远迎
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Chengdu Gongcheng Semiconductor Co ltd
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Chengdu Gongcheng Semiconductor Co ltd
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Priority to CN202211616624.7A priority patent/CN115911096A/en
Priority to CN202211616618.1A priority patent/CN116013983A/en
Priority to CN202211015797.3A priority patent/CN115117150B/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
    • H01L29/7787—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT with wide bandgap charge-carrier supplying layer, e.g. direct single heterostructure MODFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0638—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for preventing surface leakage due to surface inversion layer, e.g. with channel stopper
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
    • H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Abstract

The invention discloses a GaN HEMT power device and a preparation method thereof, belonging to the technical field of semiconductors, wherein the device comprises a third substrate, a second middle layer, a buffer layer, a GaN layer and an AlGaN layer which are sequentially connected from bottom to top; a source electrode, a drain electrode and a grid electrode are arranged on the AlGaN layer, wherein the source electrode and the drain electrode are both connected into the GaN layer in an extending mode; the GaN layer is provided with a cavity, the lower end of the cavity extends into the buffer layer, and the upper end of the cavity is located below the source electrode and the drain electrode. According to the invention, the cavity is formed on the GaN layer, so that the thickness of the GaN layer below the channel is reduced, the leakage is reduced, and the two-dimensional electron gas density of the AlGaN/GaN interface is increased, and the performance of the device is improved.

Description

GaN HEMT power device and preparation method thereof
Technical Field
The invention relates to the technical field of semiconductors, in particular to a GaN HEMT power device and a preparation method thereof.
Background
The traditional GaN HEMT device needs to grow AlGaN/GaN materials on a silicon substrate, then the HEMT device is manufactured, two factors influencing the GaN HEMT device are that an AlGaN layer presents tensile strain and electric leakage of the GaN layer, wherein the working core principle of the GaN HEMT device is that the AlGaN layer presents tensile strain, the GaN layer has two polarization effects of spontaneous polarization and piezoelectric polarization, and the GaN layer only has the spontaneous polarization effect because of the difference of the polarization effects, induced two-dimensional electron gas is generated at an AlGaN/GaN interface, and the concentration of the two-dimensional electron gas determines the conductivity of the device, so that the tensile strain of the AlGaN layer is increased, the concentration of the two-dimensional electron gas is increased, and the performance of the device is improved. In addition, when AlGaN/GaN grows on a silicon substrate, because of lattice mismatch and thermal mismatch problems, after the growth is completed, a GaN layer bears huge tensile stress, so that a large number of dislocations are generated in the AlGaN/GaN layer, and the dislocations can cause electric leakage of a power device to be increased, and the performance of the device is seriously influenced.
Disclosure of Invention
The invention aims to solve the problems of insufficient concentration and electric leakage of induced two-dimensional electron gas generated at an AlGaN/GaN interface of the conventional GaN HEMT device, and provides a GaN HEMT power device and a preparation method thereof.
The purpose of the invention is realized by the following technical scheme:
in one scheme, the GaN HEMT power device comprises a third substrate, a second middle layer, a buffer layer, a GaN layer and an AlGaN layer which are sequentially connected from bottom to top; a source electrode, a drain electrode and a grid electrode are arranged on the AlGaN layer, wherein the source electrode and the drain electrode are both extended and connected into the GaN layer; the GaN layer is provided with a cavity, the lower end of the cavity extends into the buffer layer, and the upper end of the cavity is located below the source electrode and the drain electrode.
As a preferred item, the GaN HEMT power device has the thickness of a GaN layer above the cavity of 0.2 um-1um.
As a preferred option, the third substrate is a silicon substrate or an SOI wafer.
As a preferred aspect, in the GaN HEMT power device, p-type GaN is epitaxially grown on the AlGaN layer, and the gate is located on the p-type GaN.
As a preferred item, the GaN HEMT power device has an enhancement silicon MOSFET device connected to the AlGaN layer.
In another aspect, a method for fabricating a GaN HEMT power device is provided, the method comprising the steps of:
s1, sequentially extending a buffer layer, a GaN layer and an AlGaN layer on a first substrate;
s2, spin-coating or depositing a first intermediate layer on the AlGaN layer, and bonding a second substrate on the first intermediate layer;
s3, grinding and selectively etching to remove the first substrate to leak the buffer layer, spinning photoresist on the buffer layer and opening a window;
s4, etching the buffer layer and the GaN layer in sequence to form an etching groove, wherein the etching groove stops etching after extending to the inside of the GaN layer and the photoresist is removed;
s5, bonding a third substrate with a spin-coated or deposited second middle layer on the buffer layer, and enabling the second middle layer to cover the etching groove to form a cavity;
and S6, removing the first intermediate layer and the second substrate, and manufacturing a source electrode, a drain electrode and a grid electrode on the AlGaN layer to obtain the GaN HEMT power device.
As a preferred item, in the preparation method of the GaN HEMT power device, the first substrate, the second substrate and the third substrate are silicon substrates.
As a preferred option, in the step S6, a channel of the source and the drain is disposed at an upper end of the cavity.
As a preferred item, a method for manufacturing a GaN HEMT power device, the method further comprises:
p-type GaN is epitaxially grown on the AlGaN layer, and a gate is formed on the p-type GaN.
As a preferred item, a method for manufacturing a GaN HEMT power device, the method further comprises:
an enhancement silicon MOSFET device is connected to the AlGaN layer.
It should be further noted that the technical features corresponding to the above options can be combined with each other or replaced to form a new technical solution without conflict.
Compared with the prior art, the invention has the beneficial effects that:
according to the invention, the cavity is arranged in the GaN layer, the lower end of the cavity extends into the buffer layer, the upper end of the cavity is positioned below the channel of the source electrode and the drain electrode, the stress is redistributed due to the formation of the cavity, the crystal lattice of the area above the corresponding cavity is further stretched, the AlGaN laminated electrode polarization is obviously increased, and the density of two-dimensional electron gas of the AlGaN/GaN interface is increased; meanwhile, a cavity is formed below the channel of the source electrode and the drain electrode, the thickness of the GaN layer is obviously reduced, leakage channels are reduced, leakage is reduced, and the performance of the device is greatly improved.
Drawings
FIG. 1 is a block diagram of a GaN HEMT power device shown in the present invention;
FIG. 2 is a schematic diagram of the structure of the GaN HEMT power device with p-type GaN epitaxial thereon according to the present invention;
FIG. 3 is a schematic diagram of the structure of an epitaxial enhancement mode silicon MOSFET device on a GaN HEMT power device shown in the present invention;
FIG. 4 is a schematic diagram of the structure of the present invention based on FIG. 3 for epitaxial AlGaN/GaN layers on an SOI substrate;
FIG. 5 is a schematic diagram of another GaN HEMT power device based on FIG. 3 according to the present invention;
fig. 6 is a schematic view showing the present invention in which a buffer layer, a GaN layer, and an AlGaN layer are sequentially epitaxial on a first substrate;
fig. 7 is a schematic view illustrating the spin coating or deposition of a first intermediate layer on the AlGaN layer and the bonding of a second substrate on the first intermediate layer according to the present invention;
FIG. 8 is a schematic diagram of sequentially etching the buffer layer and the GaN layer to form an etching groove according to the invention;
fig. 9 is a schematic view of the present invention showing the formation of a cavity.
The reference numbers in the figures illustrate: 1. a third substrate; 2. a second intermediate layer; 3. a buffer layer; 4. a GaN layer; 5. an AlGaN layer; 6. a cavity; 7. p-type GaN; 8. a first substrate; 9. a first intermediate layer; 10. a second substrate.
Detailed Description
The technical solutions of the present invention will be described clearly and completely with reference to the accompanying drawings, and it should be understood that the described embodiments are some, but not all embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
In the description of the present invention, it should be noted that directions or positional relationships indicated by "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", and the like are directions or positional relationships described based on the drawings, and are only for convenience of description and simplification of description, but do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus, should not be construed as limiting the present invention. Furthermore, the terms "first" and "second" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
Furthermore, the technical features involved in the different embodiments of the present invention described below may be combined with each other as long as they do not conflict with each other.
According to the invention, the cavity is mainly arranged in the GaN layer, so that the polarization of the AlGaN laminated electrode is obviously increased, the two-dimensional electron gas density of the AlGaN/GaN interface is increased, the leakage channel is reduced, and the purpose of improving the performance of the device is achieved.
Example 1
In an exemplary embodiment, a GaN HEMT power device is provided, as shown in fig. 1, the device includes a third substrate 1, a second intermediate layer 2, a buffer layer 3, a GaN layer 4 and an AlGaN layer 5 connected in sequence from bottom to top; a source electrode, a drain electrode and a grid electrode are arranged on the AlGaN layer 5, wherein the source electrode and the drain electrode are both connected into the GaN layer 4 in an extending way; the GaN layer 4 is provided with a cavity 6, the lower end of the cavity 6 extends into the buffer layer 3, and the upper end of the cavity 6 is positioned below the channel of the source electrode and the drain electrode. The third substrate 1 is a silicon substrate or an SOI wafer.
Specifically, in the epitaxial growth process, because the thermal expansion coefficient of the GaN layer 4 is greater than that of the silicon substrate, the GaN layer is in a lattice expansion state when grown at a high temperature, and when the temperature is reduced to normal temperature, the silicon substrate and the lattice of the GaN layer 4 shrink simultaneously, but due to the influence of the silicon substrate, the GaN layer 4 cannot shrink to a normal lattice at normal temperature but is larger than the normal lattice, so that both the GaN layer 4 and the AlGaN layer 5 are subjected to tensile strain. The tensile strain of the GaN layer 4 is due only to thermal expansion without complete contraction, and the tensile strain of the AlGaN layer 5 is directly due to AlGaN which is very thin and grows in a eutectic lattice with the GaN layer 4, but AlGaN has a smaller lattice constant than GaN, and when the eutectic lattice grows, alGaN has the same lattice as GaN and thus exhibits a large tensile strain. Therefore, the piezoelectric polarization phenomenon of AlGaN is strong. Since the GaN layer 4 is very thick, although it has a small tensile strain, the piezoelectric polarization effect is not significant and can be ignored.
Further, the formation of the cavity 6 causes the stress to be redistributed, the region lattices at the two sides of the cavity 6 are further contracted to be close to the normal lattice state, and the region lattices above the corresponding cavity 6 are further stretched to present stronger tensile strain, so that the piezoelectric polarization of the corresponding AlGaN layer 5 is obviously increased. Although the GaN layer 4 also has piezoelectric polarization enhancement effect, the piezoelectric polarization enhancement effect is not significant because of its large film thickness. The whole effect is that piezoelectric polarization enhancement of the AlGaN layer 5 leads to increase of two-dimensional electron gas density of an AlGaN/GaN interface and increase of device performance.
Furthermore, the cavity 6 in the figure is mainly located below the source and drain channels, so that the thickness of the GaN layer 4 is obviously reduced, a leakage channel is reduced, and the leakage is reduced.
Further, the cavity 6 cannot completely etch away the GaN layer 4, otherwise the two-dimensional electron gas is not present, and the thickness of the GaN layer 4 above the cavity 6 is preferably 0.2 um-1um.
Example 2
Based on embodiment 1, a GaN HEMT power device is provided, as shown in fig. 2, a p-type GaN7 is epitaxially grown on the AlGaN layer 5, and the gate is located on the p-type GaN 7.
Specifically, the device obtained in the first embodiment is a normally-on type device (depletion mode DMODE), and most applications require a normally-off type device (enhancement mode EMODE), a layer of p-type GaN7 is required to be epitaxially grown on the AlGaN layer 5, and a gate is fabricated on the p-type GaN. In the actual fabrication of the device, the pGaN layer may optionally be epitaxial in the first step, or may optionally be epitaxial immediately prior to fabrication of the device in the structure of example one.
Example 3
Based on embodiment 1, a GaN HEMT power device is provided, as shown in fig. 3, an enhancement silicon MOSFET device is connected to the AlGaN layer 5.
In particular, the P-type GaN is very difficult to manufacture in embodiment 2, because the P-type doping element (typically magnesium) has very low activation efficiency in the GaN material, the P-type doping of the GaN material is very difficult, the quality of the P-type GaN is not ideal, and on the other hand, the threshold voltage of the EMODE device based on the structure is low, and a driving circuit needs to be designed to support during the use. Therefore, in this embodiment, another solution is provided by connecting an enhancement-mode silicon MOSFET in series with a depletion-mode GaN HEMT, with the source and gate of the silicon MOSFET serving as the source and gate of the entire device and the drain of the GaN HEMT serving as the drain of the entire device, so-called cascod mode.
Furthermore, the two devices are designed on the same substrate, and the silicon layer is separated from the lower GaN layer through the middle layer and does not influence each other. The two devices can be interconnected through a metal layer in the process, and can also be interconnected through packaging and routing after the whole device is completed, so that a CASCODE structure is realized. The SOI material is used in this step because the SOI material can define the thickness of the silicon layer very well, and the implementation process is simple. Theoretically, it is also possible to use silicon directly instead of SOI and then obtain a certain thickness of silicon by grinding and polishing processes, which can also be achieved with great difficulty.
Example 4
Based on embodiment 1, a GaN HEMT power device is provided, as shown in fig. 4, which is different from the previous device in that an SOI wafer is bonded to one side of the device, an additional silicon layer is added to the middle layer, and the SOI of the top silicon is used as the initial substrate, because the silicon layer is thinner, the dislocation of the GaN layer caused by lattice mismatch can be reduced, and the performance of the device can be further improved.
Further, in another example, as shown in fig. 5, another GaN HEMT power device is provided that is bonded to an SOI substrate while an intermediate layer is spin coated or deposited.
Example 5
Based on the same inventive concept as embodiment 1, with reference to fig. 6 to 9, there is provided a method for manufacturing a GaN HEMT power device, the method including the steps of:
s1, as shown in figure 6, sequentially extending a buffer layer 3, a GaN layer 4 and an AlGaN layer 5 on a first substrate 8;
s2, as shown in fig. 7, spin-coating or depositing a first intermediate layer 9 on the AlGaN layer 5, and bonding a second substrate 10 on the first intermediate layer 9; when the first intermediate layer 9 is deposited, the deposited material may be SiO2 or other material, and if necessary, chemical mechanical polishing is added;
s3, grinding and selectively etching to remove the first substrate 8 to leak the buffer layer 3, spin-coating photoresist on the buffer layer 3 and opening a window;
s4, as shown in FIG. 8, etching the buffer layer 3 and the GaN layer 4 in sequence to form an etching groove, wherein the etching groove stops etching after extending to the inside of the GaN layer 4, and the photoresist is removed;
s5, as shown in FIG. 9, bonding a third substrate 1 with a second intermediate layer 2 on the buffer layer 3 in a spin coating or deposition manner, and enabling the second intermediate layer 2 to cover the etching groove to form a cavity 6;
and S6, removing the first intermediate layer 9 and the second substrate 10, and manufacturing a source electrode, a drain electrode and a grid electrode on the AlGaN layer 5 to obtain the GaN HEMT power device shown in the figure 1.
Further, the first substrate 8, the second substrate 10 and the third substrate 1 are all silicon substrates. In step S6, the source and drain channels are provided at the upper end of the cavity 6.
Further, the method further comprises:
p-type GaN7 is epitaxially grown on the AlGaN layer 5, and a gate electrode is formed on the p-type GaN 7.
Further, the method further comprises:
an enhancement silicon MOSFET device is connected to the AlGaN layer 5.
The above detailed description is for the purpose of describing the invention in detail, and it should not be construed that the detailed description is limited to the description, and it will be apparent to those skilled in the art that various modifications and substitutions can be made without departing from the spirit of the invention.

Claims (6)

1. A GaN HEMT power device is characterized by comprising a third substrate (1), a second intermediate layer (2), a buffer layer (3), a GaN layer (4) and an AlGaN layer (5) which are sequentially connected from bottom to top; a source electrode, a drain electrode and a grid electrode are arranged on the AlGaN layer (5), wherein the source electrode and the drain electrode are both connected into the GaN layer (4) in an extending way; a cavity (6) is arranged in the GaN layer (4), the lower end of the cavity (6) extends into the buffer layer (3), and the upper end of the cavity (6) is positioned below the channel of the source electrode and the drain electrode;
the preparation method of the GaN HEMT power device comprises the following steps:
s1, sequentially extending a buffer layer (3), a GaN layer (4) and an AlGaN layer (5) on a first substrate (8);
s2, spin-coating or depositing a first intermediate layer (9) on the AlGaN layer (5), and bonding a second substrate (10) on the first intermediate layer (9);
s3, grinding and selectively etching to remove the first substrate (8) to leak out the buffer layer (3), spin-coating photoresist on the buffer layer (3) and opening a window;
s4, etching the buffer layer (3) and the GaN layer (4) in sequence to form an etching groove, wherein the etching groove stops etching after extending to the inside of the GaN layer (4) and the photoresist is removed;
s5, bonding a third substrate (1) with a second middle layer (2) in a spin coating or deposition mode on the buffer layer (3), and enabling the second middle layer (2) to cover the etching groove to form a cavity (6);
and S6, removing the first intermediate layer (9) and the second substrate (10), and manufacturing a source electrode, a drain electrode and a grid electrode on the AlGaN layer (5) to obtain the GaN HEMT power device.
2. The GaN HEMT power device according to claim 1, wherein the GaN layer (4) above the cavity (6) has a thickness of 0.2 um-1um.
3. A GaN HEMT power device according to claim 1, wherein said third substrate (1) is a silicon substrate or an SOI wafer.
4. The GaN HEMT power device according to claim 1, wherein the AlGaN layer (5) is epitaxially provided with p-type GaN (7), and the gate is located on the p-type GaN (7).
5. A GaN HEMT power device according to claim 1, wherein said AlGaN layer (5) is connected to an enhancement mode silicon MOSFET device.
6. The GaN HEMT power device according to claim 1, wherein the first substrate (8), the second substrate (10) and the third substrate (1) are silicon substrates.
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CN202211616624.7A CN115911096A (en) 2022-08-24 2022-08-24 GaN HEMT power device for realizing CASCODE mode
CN202211616618.1A CN116013983A (en) 2022-08-24 2022-08-24 Normally open GaN HEMT power device
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Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05291307A (en) * 1991-12-05 1993-11-05 Samsung Electron Co Ltd Compound semiconductor device and manufacture thereof
US5336626A (en) * 1992-03-18 1994-08-09 Samsung Electronics Co., Ltd. Method of manufacturing a MESFET with an epitaxial void
KR940003096A (en) * 1992-07-31 1994-02-19 김광호 High electron mobility transistor and manufacturing method
US7030428B2 (en) * 2001-12-03 2006-04-18 Cree, Inc. Strain balanced nitride heterojunction transistors
US8759877B2 (en) * 2010-06-01 2014-06-24 Ishiang Shih Stress release structures for metal electrodes of semiconductor devices
CN102569390A (en) * 2010-12-24 2012-07-11 中国科学院微电子研究所 High-breakdown gallium nitride-based field effect transistor device and manufacturing method thereof
CN102280494A (en) * 2011-08-16 2011-12-14 电子科技大学 Normally-closed field control channel GaN heterojunction diode
JP5784441B2 (en) * 2011-09-28 2015-09-24 トランスフォーム・ジャパン株式会社 Semiconductor device and manufacturing method of semiconductor device
KR20130035024A (en) * 2011-09-29 2013-04-08 삼성전자주식회사 High electron mobility transistor and method of manufacturing the same
CN105655395B (en) * 2015-01-27 2018-05-15 苏州捷芯威半导体有限公司 A kind of enhancement type high electron mobility transistor and preparation method thereof
US20200044068A1 (en) * 2017-03-31 2020-02-06 Panasonic Intellectual Property Management Co., Ltd. Semiconductor device
CN108400235B (en) * 2018-02-28 2021-06-15 中国电子科技集团公司第十三研究所 Preparation method of Si-based GaN pressure sensor
CN110137244B (en) * 2019-04-09 2022-07-12 华南师范大学 Vertical-structure HEMT device with GaN-based self-supporting substrate and preparation method
CN110459595A (en) * 2019-08-29 2019-11-15 华南理工大学 A kind of enhanced AlN/AlGaN/GaN HEMT device and preparation method thereof
US11127848B2 (en) * 2019-11-29 2021-09-21 Vanguard International Semiconductor Corporation Semiconductor structure and method for forming the same
US20230238446A1 (en) * 2020-11-06 2023-07-27 Enkris Semiconductor, Inc. Semiconductor structure and manufacturing method thereof
CN114121655B (en) * 2021-11-16 2023-08-25 西安电子科技大学芜湖研究院 Self-termination etching method and device based on enhanced device
CN114883406B (en) * 2022-07-08 2022-09-30 江苏能华微电子科技发展有限公司 Enhanced GaN power device and preparation method thereof

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