CN115114062A

CN115114062A - Method, apparatus, device and storage medium for detecting fault of instruction word line

Info

Publication number: CN115114062A
Application number: CN202210449197.1A
Authority: CN
Inventors: 强鹏
Original assignee: Tencent Technology Shenzhen Co Ltd
Current assignee: Tencent Technology Shenzhen Co Ltd
Priority date: 2022-04-27
Filing date: 2022-04-27
Publication date: 2022-09-27
Anticipated expiration: 2042-04-27
Also published as: CN115114062B

Abstract

The application relates to a fault detection method, a fault detection device, a fault detection equipment and a fault detection storage medium for an instruction word line. The method can be applied to application scenes of cloud technology and vehicle-mounted terminals, and comprises the following steps: sending an instruction word sequence to a target memory through an instruction word line so that the target memory performs instruction processing on the instruction word sequence based on an instruction processing circuit to obtain a first target instruction word sequence; reading a first target instruction word sequence in the target memory through a target data interface; performing instruction processing on the instruction word sequence based on a target algorithm to obtain a second target instruction word sequence; and detecting a line fault of the instruction word line in the instruction word transmission process based on the first target instruction word sequence and the second target instruction word sequence. The method can improve the detection capability of the transmission line fault.

Description

Fault detection method, device, equipment and storage medium for instruction word line

Technical Field

The present application relates to the field of computer technologies, and in particular, to a method, an apparatus, a device, and a storage medium for detecting a fault of an instruction word line.

Background

A High Bandwidth Memory (HBM) is a new type of High-speed and High-Bandwidth Memory, and is mainly applied to the field of artificial intelligence chips. When the control instruction of the HBM can work at the highest and then at a clock frequency of 1.8GHz, a transmission line of the control instruction is susceptible to the influence of chip technology, working voltage, ambient temperature and crosstalk between signals, so that an error occurs in the transmitted control instruction, and therefore, when the control instruction is transmitted, the fault detection needs to be performed on each transmission line of the control instruction.

The conventional fault detection is mainly to perform Parity Check by sending Parity Check information of PAR (Parity Check), however, the Parity Check can only be used to determine whether a faulty transmission line exists in each transmission line, and cannot determine which transmission line is faulty, which results in poor detection capability of transmission line fault.

Disclosure of Invention

In view of the above, it is desirable to provide a method, an apparatus, a device, and a storage medium for detecting a fault in an instruction word line, which can improve the transmission line fault detection capability.

In a first aspect, the present application provides a method of fault detection for an instruction word line. The method comprises the following steps:

sending an instruction word sequence to a target memory through an instruction word line so that the target memory performs instruction processing on the instruction word sequence based on an instruction processing circuit to obtain a first target instruction word sequence;

reading a first target instruction word sequence in the target memory through a target data interface;

performing instruction processing on the instruction word sequence based on a target algorithm to obtain a second target instruction word sequence;

and detecting a line fault of the instruction word line in the instruction word transmission process based on the first target instruction word sequence and the second target instruction word sequence.

In a second aspect, the present application further provides a fault detection apparatus for an instruction word line. The device comprises:

the instruction sending module is used for sending an instruction word sequence to a target memory through an instruction word line so that the target memory carries out instruction processing on the instruction word sequence based on an instruction processing circuit to obtain a first target instruction word sequence;

the data reading module is used for reading a first target instruction word sequence in the target memory through a target data interface;

the instruction processing module is used for carrying out instruction processing on the instruction word sequence based on a target algorithm to obtain a second target instruction word sequence;

and the fault detection module is used for detecting a line fault of the instruction word line in the instruction word transmission process based on the first target instruction word sequence and the second target instruction word sequence.

In a third aspect, the application also provides a computer device. The computer device comprises a memory storing a computer program and a processor implementing the following steps when executing the computer program:

and detecting line faults of the instruction word lines in the instruction word transmission process based on the first target instruction word sequence and the second target instruction word sequence.

In a fourth aspect, the present application further provides a computer-readable storage medium. The computer-readable storage medium having stored thereon a computer program which, when executed by a processor, performs the steps of:

sending an instruction word sequence to a target memory through an instruction word line, so that the target memory performs instruction processing on the instruction word sequence based on an instruction processing circuit to obtain a first target instruction word sequence;

In a fifth aspect, the present application further provides a computer program product. The computer program product comprising a computer program which when executed by a processor performs the steps of:

According to the fault detection method, device, equipment and storage medium of the instruction word line, the instruction word sequence is sent to the target memory through the instruction word line, so that the target memory carries out instruction processing on the instruction word sequence based on the instruction processing circuit to obtain a first target instruction word sequence; reading a first target instruction word sequence in a target memory through a target data interface; performing instruction processing on the instruction word sequence based on a target algorithm to obtain a second target instruction word sequence; based on the first target instruction word sequence and the second target instruction word sequence, the line fault of the instruction word line in the instruction word transmission process is detected, so that the specific faulted instruction word line and the wrong target instruction word in the instruction word sequence can be determined when the transmission line is faulted, and the detection capability of the transmission line fault is improved.

Drawings

FIG. 1 is a diagram of an exemplary embodiment of a method for fault detection of an instruction word line;

FIG. 2 is a flow diagram illustrating a method for fault detection of an instruction word line in one embodiment;

FIG. 3 is a diagram of a line instruction in one embodiment;

FIG. 4 is a diagram of a column instruction in one embodiment;

FIG. 5 is a diagram of a sequence of instruction words in one embodiment;

FIG. 6 is a schematic diagram of instruction processing circuitry in one embodiment;

FIG. 7 is a block diagram illustrating a target data interface in one embodiment;

FIG. 8 is a schematic diagram illustrating an example of a target data interface;

FIG. 9 is a diagram illustrating an exemplary embodiment of the function of bits of a mode configuration instruction;

FIG. 10 is a code diagram of a target algorithm in one embodiment;

FIG. 11 is a block diagram of a fault detection system for an instruction word line in one embodiment;

FIG. 12 is a schematic illustration of a sequence of instruction words transmitted in one embodiment;

FIG. 13 is a block diagram of a fault detection device for the instruction word line in one embodiment;

FIG. 14 is a block diagram showing a configuration of a fault detection apparatus of an instruction word line in another embodiment;

FIG. 15 is a diagram showing an internal structure of a computer device in one embodiment;

fig. 16 is an internal structural view of a computer device in another embodiment.

Detailed Description

In order to make the objects, technical solutions and advantages of the present application more apparent, the present application is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present application and are not intended to limit the present application.

Artificial Intelligence (AI) is a theory, method, technique and application system that uses a digital computer or a machine controlled by a digital computer to simulate, extend and expand human Intelligence, perceive the environment, acquire knowledge and use the knowledge to obtain the best results. In other words, artificial intelligence is a comprehensive technique of computer science that attempts to understand the essence of intelligence and produce a new intelligent machine that can react in a manner similar to human intelligence. Artificial intelligence is the research of the design principle and the realization method of various intelligent machines, so that the machines have the functions of perception, reasoning and decision making.

With the research and development of Artificial Intelligence technology, the Artificial Intelligence technology is developed and applied in a plurality of fields, such as common Artificial Intelligence chips (AI), smart homes, smart wearable devices, virtual assistants, smart speakers, smart marketing, unmanned, automated driving, unmanned aerial vehicles, robots, smart medical services, smart customer service, and the like.

The method for detecting the fault of the instruction word line provided by the embodiment of the application can be applied to the application environment shown in fig. 1. Wherein the terminal 102 communicates with the server 104 via a network. The fault detection method for the instruction word line may be executed by the terminal 102 or the server 104, or may be executed by the terminal 102 and the server 104 in cooperation. In some embodiments, the terminal 102 and the server 104 are provided with a memory controller, and the fault detection method of the instruction word line can be specifically executed by the memory controller. If the fault detection method of the instruction word line is executed by the terminal 102, the terminal 102 sends an instruction word sequence to the target memory through the instruction word line, so that the target memory performs instruction processing on the instruction word sequence based on the instruction processing circuit to obtain a first target instruction word sequence; reading a first target instruction word sequence in a target memory through a target data interface; performing instruction processing on the instruction word sequence based on a target algorithm to obtain a second target instruction word sequence; and detecting line faults of the instruction word lines in the instruction word transmission process based on the first target instruction word sequence and the second target instruction word sequence.

The terminal 102 may be, but is not limited to, a smart phone, a tablet computer, a notebook computer, a desktop computer, a smart speaker, a smart watch, a smart voice interaction device, a smart home appliance, a vehicle-mounted terminal, and the like, which are integrated with an AI chip. The AI chip may be a chip that combines an AI processor and memory (e.g., high bandwidth memory). The memory may include a data storage area and a controller, or the controller may exist in a separate form and control the memory.

The server 104 may be an independent physical server integrated with an AI chip, or a service node in a blockchain system, where a Peer-To-Peer (P2P, Peer To Peer) network is formed among the service nodes in the blockchain system, and the P2P Protocol is an application layer Protocol operating on a Transmission Control Protocol (TCP).

In addition, the server 104 may also be a server cluster formed by a plurality of physical servers integrated with an AI chip, and may be a cloud server providing basic cloud computing services such as a cloud service, a cloud database, cloud computing, a cloud function, a cloud storage, a web service, cloud communication, a middleware service, a domain name service, a security service, a Content Delivery Network (CDN), and a big data and artificial intelligence platform.

The terminal 102 and the server 104 may be connected through communication connection manners such as bluetooth, USB (Universal Serial Bus), or network, which is not limited herein.

In one embodiment, as shown in fig. 2, a method for detecting a fault of an instruction word line is provided, which is described by taking the method as an example applied to a computer device (terminal or server) in fig. 1, and includes the following steps:

s202, sending the instruction word sequence to the target memory through the instruction word line, so that the target memory performs instruction processing on the instruction word sequence based on the instruction processing circuit to obtain a first target instruction word sequence.

The target storage may be a High Bandwidth Memory (HBM); specifically, the instruction Word (Address Word, abort) refers to a machine Word of an instruction, specifically refers to an instruction Word of a Memory, for example, the abort of the HBM is a general name of a control signal on an HBM DRAM interface, and taking a single-channel HBM2E DRAM as an example, the following information is included:

TABLE 1 instruction word information Table

AWORD Signal name	Bit width	Function(s)
			C	9	Column command signal
R
		7	Row instruction signal
CKE
		1	Clock Enable, Clock Enable signal

The command word line is a transmission line for transmitting command words, for example, a line for transmitting a column (C) command word in the above table may be referred to as a column (C) command word line, the column (C) command word includes C0 command words to C6 command words, the command word line for transmitting a Ci command word is referred to as a Ci command word line, a line for transmitting a row (R) command word includes R0 command words to R6 command words, the command word line for transmitting a Ri command word is referred to as a Ri command word line, and a line for transmitting a clock enable signal is referred to as a Clock (CKE) command word line.

It can be understood that the HBM atomic is responsible for completing the function of sending the instruction to the HBM DRAM, and the HBM atomic can be accurately transmitted only if the instruction word line has no fault, and the accurate transmission of the HBM atomic ensures the correctness of each operation of the HBM. The instructions of the HBM AWORD can be specifically divided into two major categories: a row instruction and a column instruction.

As shown in fig. 3, the row instructions supported by the HBM2E specifically include row idle operation, activation, precharge, all precharge, single bank refresh, Power-down entry, self-refresh entry, Power-down, self-refresh exit, and the like, and each row instruction includes R0 instruction words to R6 instruction words, an instruction word line for transmitting an Ri instruction word is referred to as an Ri instruction word line, an Ri instruction word may also be referred to as an Ri instruction word combination, any Ri instruction word combination specifically includes an Ri rising edge instruction word and an Ri falling edge instruction word, and both the Ri rising edge instruction word and the Ri falling edge instruction word are transmitted through the Ri instruction word line, that is, the Ri instruction word combination corresponds to the Ri instruction word line.

As shown in fig. 4, all column instructions supported by the HBM2E specifically include column blank operation, read with auto-precharge, write with auto-precharge, mode register setting, and the like, and each column instruction includes C0 instruction words to C6 instruction words, an instruction word line for transmitting a Ci instruction word is referred to as a Ci instruction word line, a Ci instruction word may also be referred to as a Ci instruction word combination, any Ci instruction word combination may specifically include a Ci rising edge instruction word and a Ci falling edge instruction word, both the Ci rising edge instruction word and the Ci falling edge instruction word are transmitted through the Ci instruction word line, that is, the Ci instruction word combination corresponds to the Ci instruction word line.

In fig. 3 and 4, L indicates that the bit data bit has a value of 0, H indicates that the bit data bit has a value of 1, and V indicates that the bit data bit has a value of either 0 or 1, but in the prior art design, since the default value on the AWORD line is 1, V is implemented with 1 to reduce the 0 to 1 transition on the line. BAx refers to the x-th digit of the BANK address, e.g., BA4 refers to the fourth digit of the BANK address.

It should be noted that, in the existing scheme, the manner of performing fault detection on the instruction word lines corresponding to the row instruction words and the column instruction words respectively is to mainly complete parity check by sending check information of PAR (parity check), specifically, a PAR check bit may be carried in the sent instruction, and an exclusive or operation is performed on values of data bits other than the PAR check bit in the instruction to obtain an exclusive or operation result, when the exclusive or operation result is the same as the value of the PAR check bit, it is determined that no fault occurs in each instruction word line used for transmitting the instruction, and when the exclusive or operation result is different from the value of the PAR check bit, it is determined that at least one instruction word line in each instruction word line used for transmitting the instruction has a fault, but the parity check method cannot determine which instruction word line has a fault. The conventional parity check method is described by taking a row command as a refresh command as an example, and the row command is a value corresponding to each command word of one transferred refresh command as shown in table 2 below:

TABLE 2

R0	R1	R2	R3	R4	R5	R6
							Rising edge
0	0	1	1	1	1	1
							Falling edge	1	1	PAR＝0	BA4＝0	1	1	1

As can be seen from table 2, the refresh command includes a one-bit parity PAR 0, and the exclusive or operation shown in the following formula is performed on the values of the data bits of other bits except the PAR parity in the refresh command to obtain an exclusive or operation result 0, where the exclusive or operation result is the same as the PAR value, so that it can be determined that each command word line of the refresh command has not failed, where "^" represents exclusive or.

0^0^1^1^1^1^1^1^1^0^1^1^1＝0

Table 3 below shows values corresponding to respective command words of a refresh command in another embodiment, where a transmission error of 0 to 1 occurs in a rising edge command word of R1, a transmission error of 1 to 0 occurs in a rising edge command word of R3, and a transmission error of 1 to 0 occurs in a rising edge command word of R6:

TABLE 3

R0

R1

R2

R3

R4

R5

R6

Rising edge

0

0->1

1

1->0

1

1->0

Falling edge

1

PAR＝0

BA4＝0

1

The exclusive-or operation shown in the following formula is performed on the values of data bits of other bits except the PAR check bit in the refresh command shown in table 3, so that the result of the exclusive-or operation is 1, and the result of the exclusive-or operation is different from the PAR value, so that it can be determined that at least one command word line in each command word line of the refresh command has a fault, but it cannot be determined which specific command word lines have faults in each command word line, where a' represents an exclusive-or.

0^1^1^0^1^0^1^1^1^0^1^1^1＝1

Table 4 below shows values corresponding to respective command words of a refresh command in another embodiment, where a transmission error of 1 to 0 occurs in a rising edge command word of R3, and a transmission error of 1 to 0 occurs in a rising edge command word of R4:

TABLE 4

R0	R1	R2	R3	R4	R5	R6
							Rising edge
0	0	1	1->0	1->0	1	1
							Falling edge	1	1	PAR＝0	BA4＝0	1	1	1

And performing exclusive-or operation shown in the following formula on the values of data bits of other bits except the PAR check bit in the refresh instruction shown in the table 4 to obtain that the exclusive-or operation result is 0, and the exclusive-or operation result is the same as the PAR value, so that it is determined that each instruction word line of the refresh instruction does not fail, wherein 'A' represents exclusive-or.

0^0^1^0^0^1^1^1^1^0^1^1^1＝0

As can be seen from the above example, when the number of the command word lines with faults is an odd number, the parity check can detect that the command word lines have faults, but cannot determine which specific command word lines with faults exist in each command word line; when the number of faulty command word lines is an even number, the parity check cannot detect that a command word line is faulty.

The instruction word sequence refers to an instruction word set formed by arranging a plurality of instruction words according to a certain sequence, and specifically, the instruction word sequence comprises a row instruction word, a clock cycle instruction word and a column instruction word. In this embodiment of the present application, the instruction word sequence includes a plurality of instruction word combinations, where, for any one row (R) instruction word combination, column (C) instruction word combination, or clock cycle CKE instruction word combination, each instruction word combination includes a rising edge instruction word and a falling edge instruction word, and specifically, a row instruction word combination includes a row rising edge instruction word and a row falling edge instruction word; a clock cycle instruction word combination comprises a rising edge clock cycle instruction word and a falling edge clock cycle instruction word; a column instruction word combination includes a column rising edge instruction word and a column falling edge instruction word.

Since each combination of instruction words is transmitted via its respective line of instruction words, the number of lines of instruction words used for transmitting the sequence of instruction words is the same as the number of combinations of instruction words contained in the sequence of instruction words.

It will be appreciated that each instruction word in the sequence of instruction words corresponds to a respective instruction word data bit, and the sequence of instruction words may correspond to a plurality of instruction word data bits, which may specifically include a row instruction word data bit, a clock cycle instruction word data bit, and a column instruction word data bit.

As shown in fig. 5, the sequence of instruction words of the HBM in one embodiment is arranged, and the sequence of instruction words includes 34 bits of instruction word data bits, which are sequentially from left side to right side: the data bits of the falling edge instruction words and the rising edge instruction words of R5-R0, the data bits of the falling edge instruction words and the rising edge instruction words of R6, the data bits of the falling edge instruction words and the rising edge instruction words of C7-C4, the data bits of the falling edge instruction words and the rising edge instruction words of CKE, the data bits of the falling edge instruction words and the rising edge instruction words of C3-C0, and the data bits of the falling edge instruction words and the rising edge instruction words of C8. Where F represents a rising edge instruction word data bit and R represents a falling edge instruction word data bit. It will be appreciated that for any one data bit, its value may be 0 or 1.

The instruction processing may only include shift processing, the shift processing is abbreviated as shift, or may also include compression processing and shift processing at the same time, the shift processing may be abbreviated as shift, the compression processing may be abbreviated as compression, the compression processing refers to compressing a plurality of instruction word sequences into one instruction word sequence, and the shift processing refers to shifting the instruction word sequence to obtain a new instruction word sequence. It is understood that the instruction word sequence sent by the computer device to the target memory may be one or more, and in the case of one instruction word sequence, the instruction word sequence may be shifted to obtain a first target instruction word sequence, and in the case of multiple instruction words, the instruction word sequences may be compressed and shifted to obtain a first target instruction word sequence.

Specifically, the computer device generates an instruction word sequence, and sends each instruction word combination in the instruction word sequence to the target memory in the target mode through an instruction word line corresponding to each instruction word, and after receiving the instruction word sequence, the target memory in the target mode processes the instruction word sequence based on an instruction processing circuit corresponding to the target mode to obtain a first target instruction word sequence.

The number of data bits of the first target instruction word sequence is the same as the number of data bits of the instruction word sequence, for example, if the instruction word sequence includes 34 instruction word data bits, the first target instruction word sequence also includes 34 instruction word data bits. The test mode refers to an operating mode of the target memory when the target memory is tested, the test mode may be multiple, the target mode may be one of multiple test modes, for example, the target mode may be a Multiple Input Shift Register (MISR) mode, or may be a normal Register mode, and the instruction processing circuit corresponding to the test mode is a Multiple Input Shift Register (MISR) circuit.

It is noted that a Multiple Input Shift Register (MISR) circuit may include a plurality of flip-flops and a plurality of input selectors alternately coupled in series to each other, and the plurality of input selectors may respectively correspond to the plurality of flip-flops. Referring to fig. 4, which is a schematic diagram of a MISR circuit in an embodiment showing 4 flip-flops and 4 input selectors to store and output 4 bits of data, when both input control signals M0 and M1 are 1, i.e., when both input control signals M0 and M1 are input at logic high level, the MISR circuit corresponds to a multiple input shift register mode (MISR mode), i.e., the MISR circuit can perform the function of a multiple input shift register; when the input control signal M0 is 0 in bit and M1 is 1, i.e., the input control signal M0 is input at a logic low level and M1 is input at a logic high level, the MISR circuit corresponds to a simple Register mode, i.e., the MISR circuit can perform a simple Register function; when the input control signal M0 is bit 1 and M1 is 10, i.e., the input control signal M0 is input at a logic high level and M1 is input at a logic low level, the MISR circuit corresponds to a linear feedback shift register mode (LFSR mode), i.e., the MISR circuit can perform a Linear Feedback Shift Register (LFSR) function.

It is understood that when the instruction word data bits of the instruction word sequence are 34 bits, the corresponding MISR circuit may comprise 34 flip-flops and 34 input selectors to store and output the 34 bits, and the 34 bits MISR circuit can be described mathematically by the following polynomial:

f(X)＝X ³⁴ +X ²⁷ +X ² +1

it is understood that, after the instruction processing circuit performs the instruction processing on the instruction word sequence to obtain the first target instruction word sequence, the target memory may store the processed first target instruction word sequence in a corresponding memory unit of the instruction processing circuit, for example, in an AWORD MISR register unit. In the embodiment of the present application, if the input command word sequence is 34 data bits, the first target command word sequence obtained by performing command processing on the input command word sequence is also 34 data bits.

S204, reading a first target instruction word sequence in the target memory through the target data interface.

The target data interface is a data reading interface based on a target protocol standard, the target protocol standard may be IEEE standard 1500, as shown in fig. 7, a schematic structural diagram of the data reading interface defined by the IEEE1500 standard is shown, and fig. 8 shows functional description information of each interface in fig. 7.

It should be noted that the data stored in the target memory in the target mode can be read through the target data interface.

Specifically, after obtaining the first target instruction word sequence, the target memory stores the first target instruction word sequence in an internal register unit of the target storage, for example, in an AWORD MISR register unit, and the terminal may read the first target instruction word sequence stored in the internal register unit through the target data interface.

And S206, performing instruction processing on the instruction word sequence based on the target algorithm to obtain a second target instruction word sequence.

The target algorithm may be an algorithm matched with the instruction processing circuit, that is, the effect of performing instruction processing on the instruction word sequence by the target algorithm is the same as the effect of performing instruction processing on the instruction word sequence by the instruction processing circuit. The number of data bits of the second target instruction word sequence is the same as the number of data bits of the instruction word sequence, for example, if the instruction word sequence includes 34 instruction word data bits, the second target instruction word sequence also includes 34 instruction word data bits.

The instruction processing may specifically include only shift processing, or may include both compression processing and shift processing, where the compression processing is to compress a plurality of instruction word sequences into one instruction word sequence, and the shift processing is to shift the instruction word sequence to obtain a new instruction word sequence. It is understood that the instruction word sequence sent by the computer device to the target memory may be one or more, and in the case of one instruction word sequence, the instruction word sequence may be shifted to obtain a second target instruction word sequence, and in the case of multiple instruction words, the instruction word sequences may be compressed and shifted to obtain a second target instruction word sequence.

Specifically, after the computer device generates the command word sequence, on one hand, the generated command word sequence is sent to the target memory, on the other hand, a preset target algorithm is obtained, and the generated command word sequence is subjected to command processing by using the target algorithm to obtain a second target command word sequence.

And S208, detecting a line fault of the instruction word line in the instruction word transmission process based on the first target instruction word sequence and the second target instruction word sequence.

Specifically, after obtaining the first target instruction word sequence and the second target instruction word sequence, the computer device compares corresponding instruction words in the first target instruction word sequence and the second target instruction word sequence in sequence to obtain comparison results of the corresponding instruction words, and determines a line fault occurring in an instruction word transmission process of an instruction word line according to the corresponding comparison results, that is, whether each instruction word line has a fault.

In one embodiment, S208 specifically includes the following steps: comparing the instruction word of each data bit in the first target instruction word sequence with the instruction word of the corresponding data bit in the second target instruction word sequence in sequence to obtain a comparison result; when the comparison result shows that the instruction words are the same, determining that no path fault occurs in the instruction word line in the instruction word transmission process; and when the comparison result shows that the instruction words of the target data bits are different, determining that a line fault occurs in the instruction word line in the instruction word transmission process.

The comparison result indicates that the instruction words are the same, which means that the values of the corresponding instruction words are the same.

For example, the command word sequence has 34 data bits from 0-bit data bit to 33-bit data bit, the 0-bit data bit to 33-bit data bit from right to left, the command word of the 0-bit data bit is command word 1, the command word of the 1-bit data bit is command word 2, and so on, the command word of the 32-bit data bit is command word 33, the command word of the 33-bit data bit is command word 34, each command word of the command word sequence has a corresponding value, the corresponding first target command word sequence also has 34 data bits from the 0-bit data bit to the 33-bit data bit, the second target command word sequence also has 34 data bits from the 0-bit data bit to the 33-bit data bit, then the 0-bit data bit of the first target command word sequence corresponds to the 0-bit data bit of the second target command word sequence, the 1 st bit data bit of the first target instruction word sequence corresponds to the 1 st bit data bit of the second target instruction word sequence, and so on, the 33 th bit data bit of the first target instruction word sequence corresponds to the 33 th bit data bit of the second target instruction word sequence, in other words, instruction word 1 of the first target instruction word sequence corresponds to instruction word 1 of the second target instruction word sequence, instruction word 2 of the first target instruction word sequence corresponds to instruction word 2 of the second target instruction word sequence, and so on, instruction word 34 of the first target instruction word sequence corresponds to instruction word 34 of the second target instruction word sequence, and after obtaining the first target instruction word sequence and the second target instruction word sequence, the computer device compares the value of instruction word 1 of the first target instruction word sequence with the value of instruction word 1 of the second target instruction word sequence, compares the value of instruction word 2 of the first target instruction word sequence with the value of instruction word 2 of the second target instruction word sequence Comparing the values of the instruction words 34 of the first target instruction word sequence with the values of the instruction words 34 of the second target instruction word sequence by analogy to obtain comparison results of the instruction words of the corresponding data bits, determining that no line fault occurs in the instruction word transmission process of the instruction word line when the values of the corresponding instruction words in the comparison results are the same, and determining that the line fault occurs in the instruction word transmission process of the instruction word line when the comparison results indicate that the instruction words of the target data bits are different, if the value of the ith bit data bit instruction word i of the first target instruction word sequence is different from the value of the instruction word i of the ith bit data bit of the second target instruction word sequence, determining that the line fault occurs in the instruction word transmission process of the instruction word line.

In the above embodiment, the computer device obtains the comparison result by sequentially comparing the instruction word of each data bit in the first target instruction word sequence with the instruction word of the corresponding data bit in the second target instruction word sequence, so as to determine the specific faulty instruction word line when the transmission line is faulty according to the comparison result, thereby improving the detection capability for the transmission line fault.

In one embodiment, the number of instruction word lines is the same as the number of instruction word combinations in the sequence of instruction words; each instruction word combination comprises a rising edge instruction word and a falling edge instruction word; when the comparison result shows that the instruction words of the target data bits are different, the process of determining that the line fault occurs in the instruction word line in the instruction word transmission process is specifically as follows: when the comparison result shows that the instruction words with the target data bits are different, determining a target instruction word line corresponding to the target data bits in the instruction word lines with the number; and determining that the line fault of the target instruction word line occurs in the transmission process of the instruction word.

For example, referring to fig. 5, the command word sequence has 34 data bits from 0-bit data bit to 33-bit data bit, from right to left, the 0-bit data bit to 33-bit data bit, the command word of the 0-bit data bit is a C8 rising edge command word, the command word of the 1-bit data bit is a C8 falling edge command word, and so on, the command word of the 32-bit data bit is a R5 rising edge command word, the command word of the 33-bit data bit is a R5 falling edge command word, each command word of the command word sequence has a corresponding value, the corresponding first target command word sequence also has 34 data bits from 0-bit data bit to 33-bit data bit, the second target command word sequence also has 34 data bits from 0-bit data bit to 33-bit data bit, the 0-bit data bit of the first target command word sequence corresponds to the 0-bit data bit of the second target command word sequence, the 1 st bit data bit of the first target sequence of instruction words corresponds to the 1 st bit data bit of the second target sequence of instruction words, and so on, the 33 th bit data bit of the first target sequence of instruction words corresponds to the 33 th bit data bit of the second target sequence of instruction words, in other words, the C8 rising edge instruction word of the first target sequence of instruction words corresponds to the C8 rising edge instruction word of the second target sequence of instruction words, the C8 falling edge instruction word of the first target sequence of instruction words corresponds to the C8 falling edge instruction word of the second target sequence of instruction words, and so on, the R5 falling edge instruction word of the first target sequence of instruction words corresponds to the R5 falling edge instruction word of the second target sequence of instruction words, the computer apparatus comparing the C8 rising edge instruction word of the first target sequence of instruction words with the C8 rising edge instruction word of the second target sequence of instruction words after obtaining the first target sequence of instruction words and the second target sequence of instruction words, comparing the values of C8 falling edge instruction words of a first target instruction word sequence with the values of C8 falling edge instruction words of a second target instruction word sequence, and so on, comparing R5 falling edge instruction words of the first target instruction word sequence with the values of R5 falling edge instruction words of the second target instruction word sequence to obtain the comparison result of each corresponding data bit instruction word, when the values of the corresponding instruction words in the comparison result are the same, determining that no line fault occurs in the instruction word line in the process of transmitting the instruction words, and when the comparison result shows that the instruction words of the target data bits are different, determining that the line fault occurs in the instruction word line in the process of transmitting the instruction words, for example, the value of the C8 rising edge instruction word of the 0 th bit data bit of the first target instruction word sequence is different from the value of the C8 rising edge instruction word of the 0 th bit data bit of the second target instruction word sequence, it indicates that the line of the C8 command word corresponding to the C8 rising edge command word has a line fault during the transmission of the C8 rising edge command word.

In the above embodiment, when the comparison result indicates that the instruction words with the target data bits are different, the target instruction word line corresponding to the target data bit is determined among the number of instruction word lines, so that a line fault of the target instruction word line in the instruction word transmission process is accurately determined, and the detection capability of the transmission line fault is improved.

In one embodiment, the sequence of instruction words comprises a row instruction word, a clock cycle instruction word and a column instruction word, the column instruction word comprising a parity instruction word, the computer apparatus further determines whether the instruction word of the target data bit is a parity instruction word when it is determined that the instruction words of the target data bit are not identical, and determines that a line of the instruction word corresponding to the parity instruction word fails in performing instruction word transmission when the instruction word of the target data bit is a parity instruction word.

For example, as shown in fig. 3 and 4, the R2 falling edge instruction word may also be referred to as a parity instruction word (PAR), and the C2 falling edge instruction word may also be referred to as a parity instruction word (PAR). Referring to fig. 5, the command word sequence has 34 data bits from the 0 th bit data bit to the 33 th bit data bit, and as can be seen from fig. 3 and 4, the command word of the 7 th bit data bit in fig. 5 is a parity command word, the command word of the 27 th bit data bit is a parity command word, and assuming that the computer device determines that the target data bit is the ith bit data bit, when i is equal to 7 or 27, the command word of the target data bit is determined to be a parity command word, and thus it is determined that a command word line corresponding to the parity command word fails in the command word transmission process.

In the above embodiment, when the instruction word of the target data bit is the parity instruction word, the computer device determines that the instruction word line corresponding to the parity instruction word fails in the instruction word transmission process, which solves the problem that in the conventional PAR-based fault detection method, if the PAR bit itself has an instruction word line transmission fault, the PAR-based fault detection method fails to detect the instruction word line fault, and a false-report fault or a false-report fault may occur.

In one embodiment, when the computer device determines that the instruction words of the target data bits are different according to the comparison result, the computer device may further determine the position of the target data bits in the instruction word sequence and the number of the lines of the instruction words corresponding to the target data bits.

For example, referring to the instruction word sequence shown in fig. 5, if the computer device determines that the target data bits are respectively a 2 nd bit data bit, a 3 rd bit data bit and a 28 th bit data bit, where the instruction word of the 2 nd bit data bit is a C0 rising edge instruction word, the instruction word of the 3 rd bit data bit is a C0 falling edge instruction word, the instruction word of the 28 th bit data bit is a R3 rising edge instruction word, that is, the 2 nd bit data bit and the 3 rd bit data bit both correspond to a C0 instruction word line, and the 28 th bit data bit corresponds to a R3 instruction word line, the number of the target data bit corresponding to the instruction word line is determined to be 2, that is, the number of the instruction word line in which the line fault occurs is determined to be 2.

In the above embodiment, when the comparison result indicates that the instruction words of the target data bits are different, the computer device may further determine the positions of the target data bits in the instruction word sequence and the number of the instruction word lines corresponding to the target data bits, that is, all the instruction word line faults may be detected, and may locate the position of the fault of each instruction word line at the several bits, thereby improving the detection capability of the transmission line fault.

It can be understood that, when there is no fault in the instruction word line used for transmitting the instruction word sequence, the instruction word sequence sent by the terminal is the same as the instruction word sequence received by the target memory, and in the case that the target algorithm is an algorithm matched with the instruction processing circuit, a first target instruction word sequence obtained by performing instruction processing on the instruction word sequence based on the instruction processing circuit is the same as a second target instruction word sequence obtained by performing instruction processing on the instruction word sequence based on the target algorithm; when the instruction word line for transmitting the instruction word sequence has a fault, the instruction word sequence sent by the terminal is different from the instruction word sequence received by the target memory, and under the condition that the target algorithm is an algorithm matched with the instruction processing circuit, a first target instruction word sequence obtained by performing instruction processing on the received instruction word sequence based on the instruction processing circuit is different from a second target instruction word sequence obtained by performing instruction processing on the instruction word sequence based on the target algorithm. It is therefore possible to determine whether the instruction word line has failed during transmission of the instruction word by determining whether the values of the instruction words of the corresponding bits in the first and second target instruction word sequences are the same.

In the fault detection method of the instruction word line, an instruction word sequence is sent to a target memory through the instruction word line, so that the target memory performs instruction processing on the instruction word sequence based on an instruction processing circuit to obtain a first target instruction word sequence; reading a first target instruction word sequence in a target memory through a target data interface; performing instruction processing on the instruction word sequence based on a target algorithm to obtain a second target instruction word sequence; based on the first target instruction word sequence and the second target instruction word sequence, the line fault of the instruction word line in the instruction word transmission process is detected, so that the specific faulted instruction word line and the wrong target instruction word in the instruction word sequence can be determined when the transmission line is faulted, and the detection capability of the transmission line fault is improved.

In one embodiment, before sending the sequence of instruction words to the target memory, the computer device further needs to configure the test pattern of the target memory, and the process of configuring the test pattern of the target memory specifically includes the following steps: sending a mode configuration instruction to the target memory so that the target memory configures the test mode into a first register mode and a second register mode based on the mode configuration instruction; when the target memory is in the first register mode, sending a sequence of instruction words to the target memory through the instruction word line; when the target memory is in the second register mode, a first sequence of target instruction words is read from the target memory based on the target data interface.

The first Register mode is a multiple input shift Register mode (MISR mode), and the second Register mode is a simple Register mode (Register mode).

Specifically, after configuring the target memory in a multiple input shift Register mode (MISR mode), the computer device sends a sequence of instruction words to the target memory through the instruction word line, the target Register in the multiple input shift Register mode (MISR mode) may perform instruction processing on the received sequence of instruction words to obtain a first sequence of target instruction words, and store the first sequence of target instruction words in the Register unit, and then the computer device configures the target memory in a simple Register mode (Register mode), and the computer device may read the first sequence of target instruction words stored in the Register unit through the target data interface.

In the above embodiment, the computer device sends the mode configuration instruction to the target memory, so that the target memory configures the test mode as the first register mode and the second register mode based on the mode configuration instruction, so that the target memory in the first register mode can perform instruction word processing on the received instruction word sequence to obtain the first target instruction word sequence, so that the target memory in the second register mode can output the first target instruction word sequence to the computer device through the target data interface, so that the computer device can detect a line fault occurring in the instruction word line during instruction word transmission based on the first target instruction word sequence and the second target instruction word sequence, thereby determining a specific faulty instruction word line and a faulty target instruction word occurring in the instruction word sequence when a transmission line has a fault, the capability of detecting transmission line faults is improved.

In one embodiment, the mode configuration instructions include a first mode configuration instruction and a second mode configuration instruction, and the process of the target memory configuring the test mode into the first register mode and the second register mode based on the mode configuration instructions includes the following steps: initializing an instruction processing circuit; configuring a test mode of the instruction processing circuit into a first register mode based on a first mode configuration instruction; the test mode of the instruction processing circuit is configured to be the second register mode based on the second mode configuration instruction.

The mode configuration instruction comprises 8bit data bits, and different mode configuration instructions are generated by changing the values of the different bit data bits.

For example, after initialization is completed, the AWORD _ MISR _ CONFIG Wrapper Data Register unit inside the HBM DRAM needs to complete configuration of the AWORD _ MISR _ CONFIG Wrapper Data Register, so that the AWORD MISR mode can be entered. As shown in fig. 9, the function description corresponds to each bit data bit of the mode configuration instruction of the HBM DRAM, where the 7 th bit data bit is used to select the number of polynomial bits supported by the MISR circuit, the 3 rd bit data bit is used to select whether to enable the gated MISR, and the 2 nd to 0 th bit data bits are used to set the target mode.

Specifically, the computer device generates an initialization instruction and sends the initialization instruction to the target memory, the target memory initializes the instruction processing circuit based on the initialization instruction after receiving the initialization instruction, then the computer device sends a first mode configuration instruction to the target memory, the initialized target memory configures the test mode of the instruction processing circuit of the target memory to be the first register mode based on the first mode configuration instruction, after sending an instruction word sequence to the target memory of the first register mode, the computer device sends a second mode configuration instruction to the target memory of the first register mode, the target memory of the first register mode configures the test mode of the instruction processing circuit to be the second register mode based on the second mode configuration instruction.

In the above embodiment, the target memory is initialized by initializing the instruction processing circuit; configuring a test mode of the instruction processing circuit into a first register mode based on a first mode configuration instruction; the instruction is configured based on the second mode, the test mode of the instruction processing circuit is configured to be the second register mode, so that the target memory in the first register mode can perform instruction word processing on the received instruction word sequence to obtain a first target instruction word sequence, and the target memory in the second register mode can output the first target instruction word sequence to the computer equipment through the target data interface.

In one embodiment, the process of sending a sequence of instruction words to the target memory by the computer device through the instruction word line, so that the target memory obtains a first sequence of target instruction words based on the instruction processing circuit performing instruction processing on the sequence of instruction words comprises the steps of: sending an instruction word sequence to a target memory through an instruction word line so that the target memory shifts the instruction word sequence based on an instruction processing circuit to obtain a first target instruction word sequence; or at least two instruction word sequences are sent to the target memory through the instruction word line, so that the target memory compresses the at least two instruction word sequences, and the compressed instruction word sequences are shifted based on the instruction processing circuit to obtain a first target instruction word sequence.

Specifically, the instruction word sequence sent by the computer device to the target memory may be one or more, and it is understood that when the sent instruction word sequence is one, the target memory shifts the instruction word sequence based on the instruction processing circuit to obtain a first target instruction word sequence; when the sequence of the transmitted instruction words is at least two, the target memory may compress the at least two sequences of instruction words into a new sequence of instruction words, and shift the compressed new sequence of instruction words based on the instruction processing circuit to obtain the first target sequence of instruction words.

The target memory may compress at least two instruction word sequences by using a compression algorithm, the compression algorithm may be an exclusive-or algorithm, and the exclusive-or algorithm is used to perform an exclusive-or operation on corresponding data bits of the instruction word sequences, so as to obtain a new instruction word sequence.

For example, there are an instruction word sequence 1 and an instruction word sequence 2, the instruction word sequence 1 has 34 data bits from the 0 th bit data bit to the 33 rd bit data bit, the instruction word sequence 2 also has 34 data bits from the 0 th bit data bit to the 33 rd bit data bit, the 0 th bit data bit of the instruction word sequence 1 corresponds to the 0 th bit data bit of the instruction word sequence 2, the 1 st bit data bit of the instruction word sequence 1 corresponds to the 1 st bit data bit of the instruction word sequence 2, and so on, the 33 th bit data bit of the instruction word sequence 1 corresponds to the 33 th bit data bit of the instruction word sequence 2, the computer device performs an exclusive or operation on the values of the 0 th bit data bits in the instruction word sequence 1 and the instruction word sequence 2 to obtain an operation result of the 0 th bit data bit, performs an exclusive or operation on the values of the 1 st bit data bits in the instruction word sequence 1 and the instruction word sequence 2, and obtaining the operation result of the 1 st bit data bit, performing exclusive-or operation on the values of the 33 th bit data bits in the instruction word sequence 1 and the instruction word sequence 2 by analogy to obtain the operation result of the 33 th bit data bit, and then arranging according to the bit data bit sequence from the operation result of the 0 th bit data bit to the operation result of the 33 th bit data bit based on the operation result of the 0 th bit data bit to obtain an instruction word sequence 3.

The instruction processing circuit used in the target memory may be a Multiple Input Shift Register (MISR) mode MISR circuit as shown in fig. 6, and the MISR circuit in the Multiple Input Shift Register (MISR) mode can shift the compressed instruction word sequence to obtain the first target instruction word sequence. The instruction processing circuit used in the target memory may be a MISR circuit of a linear feedback shift register mode (LFSR mode).

In the above embodiment, the computer device sends a sequence of instruction words to the target memory through the instruction word line, so that the target memory shifts the sequence of instruction words based on the instruction processing circuit to obtain a first sequence of target instruction words; or at least two instruction word sequences are sent to the target memory through the instruction word line, so that the target memory compresses the at least two instruction word sequences, and the compressed instruction word sequences are shifted based on the instruction processing circuit to obtain a first target instruction word sequence, so that the computer equipment can detect line faults occurring in the instruction word transmission process of the instruction word line based on the first target instruction word sequence and the second target instruction word sequence, and can determine a specific faulted instruction word line and a wrong target instruction word in the instruction word sequence when the transmission line has faults, and the detection capability of the transmission line faults is improved.

In one embodiment, the target algorithm comprises at least one of a compression algorithm and a shift algorithm; the process that the computer equipment carries out instruction processing on the instruction word sequence based on the target algorithm to obtain a second target instruction word sequence comprises the following steps: when the command word sequence is sent, shifting the command word sequence based on a shifting algorithm to obtain a second target command word sequence; and when at least two instruction word sequences are sent, compressing the at least two instruction word sequences based on a compression algorithm, and shifting the compressed instruction word sequences based on a shifting algorithm to obtain a second target instruction word sequence.

The target algorithm may be an algorithm matched with the instruction processing circuit, that is, the effect of performing instruction processing on the instruction word sequence by the target algorithm is the same as the effect of performing instruction processing on the instruction word sequence by the instruction processing circuit. The target algorithm comprises a compression algorithm and a shift algorithm, wherein the compression algorithm is used for compressing a plurality of instruction word sequences to obtain an instruction word sequence, and the shift algorithm is used for shifting an input instruction word sequence to obtain a new instruction word sequence.

Specifically, the instruction word sequence sent by the computer device to the target memory may be one or more, and it can be understood that, when the sent instruction word sequence is one, the computer device performs shift processing on the instruction word sequence by using a shift algorithm to obtain a second target instruction word sequence; when the sent instruction word sequence is at least two, the computer equipment compresses the at least two instruction word sequences into a new instruction word sequence based on a compression algorithm, and shifts the new instruction word sequence obtained by compression based on a shift algorithm to obtain a second target instruction word sequence.

In one embodiment, the compression algorithm may be an exclusive-or algorithm, and the exclusive-or algorithm is used to perform an exclusive-or operation on corresponding data bits of the instruction word sequences, so as to obtain a new instruction word sequence.

For example, there are an instruction word sequence 1 and an instruction word sequence 2, the instruction word sequence 1 has 34bit data bits from the 0 th bit data bit to the 33 rd bit data bit, the instruction word sequence 2 also has 34bit data bits from the 0 th bit data bit to the 33 rd bit data bit, the 0 th bit data bit of the instruction word sequence 1 corresponds to the 0 th bit data bit of the instruction word sequence 2, the 1 st bit data bit of the instruction word sequence 1 corresponds to the 1 st bit data bit of the instruction word sequence 2, and so on, the 33 rd bit data bit of the instruction word sequence 1 corresponds to the 33 th bit data bit of the instruction word sequence 2, the computer device performs an exclusive or operation on the values of the 0 th bit data bits in the instruction word sequence 1 and the instruction word sequence 2 to obtain an operation result of the 0 th bit data bit, performs an exclusive or operation on the values of the 1 st bit data bits in the instruction word sequence 1 and the instruction word sequence 2, and obtaining the operation result of the 1 st bit data bit, performing exclusive-or operation on the values of the 33 th bit data bits in the instruction word sequence 1 and the instruction word sequence 2 by analogy to obtain the operation result of the 33 th bit data bit, and then arranging according to the bit data bit sequence from the operation result of the 0 th bit data bit to the operation result of the 33 th bit data bit based on the operation result of the 0 th bit data bit to obtain an instruction word sequence 3.

In one embodiment, the shift algorithm may be a MISR algorithm, and fig. 10 is a code diagram of the shift algorithm in one embodiment, and a computer device may generate a new sequence of instruction words by running the code.

For example, after compressing the instruction word sequence 1 and the instruction word sequence 2 to obtain the instruction word sequence 3, the computer device may obtain the instruction word sequence 4 by executing the code shown in fig. 10 with the instruction word sequence 3 as an input of the shift algorithm shown in fig. 10.

In the above embodiment, when a command word sequence is sent, the computer device shifts the command word sequence based on a shift algorithm to obtain a second target command word sequence; when at least two instruction word sequences are sent, the computer device compresses the at least two instruction word sequences based on a compression algorithm, and shifts the compressed instruction word sequences based on a shift algorithm to obtain a second target instruction word sequence, so that the computer device can detect line faults occurring in instruction word transmission processes of instruction word lines based on the first target instruction word sequence and the second target instruction word sequence, and can determine specific faulted instruction word lines and target instruction words with errors in the instruction word sequences when the transmission lines have faults, and the detection capability of the transmission line faults is improved.

The application also provides an application scenario, and the application scenario applies a fault detection method for the instruction word line. Specifically, the application of the fault detection method for the instruction word line in the application scenario is as follows:

step one, initialization of a target memory

Specifically, the HBM Host sends an initialization instruction to the target register, so that the target memory completes initialization based on the initialization instruction.

Wherein, the initialization instruction includes 8 bits, and with reference to the function description corresponding to each bit data bit shown in fig. 9, the bit7 multiple _ SELECT bit can be specifically configured to be 1, and a 34-bit mode is selected; note that the HBM2 DRAM device should select the 30-bit mode, the HBM2E DRAM device should select the 34-bit mode; meanwhile, bit3 ENABLE bit is configured to be 1, so that the AWORD MISR mode is enabled; three bits of bits 2 to 0 are configured to be 000, and the initial value of the AWORD MISR is set to 0x2AAAAAAAh, thereby completing the initialization of the target memory.

Step two, setting the MISR mode of the target memory

Specifically, the HBM Host sends a MISR mode configuration instruction to the target register to cause the target memory to complete the MISR mode setting of the target memory based on the MISR mode configuration instruction.

The MISR mode configuration instruction includes 8 bits, and the specific configurable bits 2 to 03 are 011 and set as the MISR mode, with reference to the functional description corresponding to each bit data bit shown in fig. 9.

Step three, sending a plurality of instruction word sequences to the target memory of the MISR mode

Specifically, referring to the block diagram shown in fig. 11, the HBM Host sends an AWORD to the target memory (HBM DRAM), where at least 1 set of AWORD data is sent.

As shown in FIG. 12, the pattern number of the Write AWORD is 4 sets.

Step four, setting Register mode of the target memory

Specifically, the HBM Host sends a Register mode configuration instruction to the target Register, so that the target memory completes the target memory Register mode setting based on the Register mode configuration instruction.

The Register mode configuration instruction includes 8 bits, and the function description corresponding to each bit data bit shown in fig. 9 is referred to, where specifically configurable bits 2 to 03 are 010, and are set as Register mode.

Step five, reading the first target instruction word sequence from the target memory

Referring to fig. 11, in particular, the HBM Host initiates a read abort request to the target register, and reads out a first target instruction word sequence (MISR pattern) through the IEEE1500 interface.

As shown in fig. 12, the number of patterns of the Write AWORD is 4, the target memory processes the 4 sets of Write AWORD to obtain a set of MISR patterns, and the HBM Host reads the set of MISR patterns as Read AWORD through the IEEE1500 interface.

Step five, detecting the fault of the instruction word line

Referring to fig. 11, specifically, the HBM Host performs instruction processing on the AWORD sent to the target memory to obtain a second target instruction word sequence, and compares the second target instruction word sequence with the first target instruction word sequence, thereby determining the correctness of the AWORD line.

The instruction processing on the aware sent to the target memory may specifically adopt a MISR algorithm to perform instruction processing on the aware.

By the fault detection method of the instruction word line, the following technical effects can be achieved: 1. all command word line faults can be detected, and each command word line fault can be positioned at the position of the bit number; 2. the method can detect the number of faults of any number of command word lines, and completely solves the problem that the odd number of faults can only be found by parity check, but the even number of faults can not be detected; 3. the method solves the problems that in the traditional PAR-based fault detection method, if the PAR bit has a transmission fault of the instruction word line, the PAR-based fault detection method fails in the detection of the fault of the instruction word line, and a fault of false report or a fault of false report may occur.

It should be understood that, although the steps in the flowcharts related to the embodiments as described above are sequentially displayed as indicated by arrows, the steps are not necessarily performed sequentially as indicated by the arrows. The steps are not performed in the exact order shown and described, and may be performed in other orders, unless explicitly stated otherwise. Moreover, at least a part of the steps in the flowcharts related to the embodiments described above may include multiple steps or multiple stages, which are not necessarily performed at the same time, but may be performed at different times, and the execution order of the steps or stages is not necessarily sequential, but may be rotated or alternated with other steps or at least a part of the steps or stages in other steps.

Based on the same inventive concept, the embodiment of the present application further provides a fault detection apparatus for an instruction word line, which is used for implementing the fault detection method for the instruction word line. The implementation scheme for solving the problem provided by the apparatus is similar to the implementation scheme described in the above method, so the specific limitations in the following embodiments of the apparatus for detecting faults of one or more instruction word lines may refer to the limitations on the method for detecting faults of instruction word lines, and are not described herein again.

In one embodiment, as shown in fig. 13, there is provided a fault detection apparatus of an instruction word line, including: an instruction sending module 1302, a data reading module 1304, an instruction processing module 1306, and a fault detection module 1308, where:

the instruction sending module 1302 is configured to send an instruction word sequence to the target memory through an instruction word line, so that the target memory performs instruction processing on the instruction word sequence based on the instruction processing circuit to obtain a first target instruction word sequence.

A data reading module 1304, configured to read the first target instruction word sequence in the target memory through the target data interface.

And the instruction processing module 1306 is configured to perform instruction processing on the instruction word sequence based on a target algorithm to obtain a second target instruction word sequence.

A fault detecting module 1308, configured to detect a line fault occurring in a transmission process of an instruction word in an instruction word line, based on the first target instruction word sequence and the second target instruction word sequence.

In the above embodiment, the instruction word sequence is sent to the target memory through the instruction word line, so that the target memory performs instruction processing on the instruction word sequence based on the instruction processing circuit to obtain a first target instruction word sequence; reading a first target instruction word sequence in a target memory through a target data interface; performing instruction processing on the instruction word sequence based on a target algorithm to obtain a second target instruction word sequence; based on the first target instruction word sequence and the second target instruction word sequence, the line fault of the instruction word line in the instruction word transmission process is detected, so that the specific faulted instruction word line and the wrong target instruction word in the instruction word sequence can be determined when the transmission line is faulted, and the detection capability of the transmission line fault is improved.

In one embodiment, the failure detection module 1308 is further configured to: comparing the instruction word of each data bit in the first target instruction word sequence with the instruction word of the corresponding data bit in the second target instruction word sequence in sequence to obtain a comparison result; when the comparison result shows that the instruction words are the same, determining that no path fault occurs in the instruction word transmission process of the instruction word line; and when the comparison result shows that the instruction words of the target data bits are different, determining that a line fault occurs in the instruction word line in the instruction word transmission process.

In one embodiment, the number of instruction word lines is the same as the number of instruction word combinations in the sequence of instruction words; each instruction word combination comprises a rising edge instruction word and a falling edge instruction word; a fault detection module 1308, further configured to: when the comparison result shows that the instruction words with the target data bits are different, determining a target instruction word line corresponding to the target data bits in the instruction word lines; and determining that the line fault of the target instruction word line occurs in the transmission process of the instruction word.

In one embodiment, the instruction word combinations include a row instruction word combination, a clock cycle instruction word combination, and a column instruction word combination, the column instruction word combination including a parity instruction word; a fault detection module 1308, further configured to: and when the command word of the target data bit is a parity command word, determining that a command word line corresponding to the parity command word has a fault in the command word transmission process.

In one embodiment, the combination of line instruction words includes a line rising edge instruction word and a line falling edge instruction word; the clock cycle instruction word combination comprises a rising edge clock cycle instruction word and a falling edge clock cycle instruction word; the column instruction word combination includes a column rising edge instruction word and a column falling edge instruction word.

In one embodiment, the failure detection module 1308 is further configured to: and when the comparison result shows that the instruction words of the target data bits are different, determining the position of the target data bits in the instruction word sequence and the number of the instruction word lines corresponding to the target data bits.

In one embodiment, as shown in fig. 14, the apparatus further comprises: a mode configuration module 1310, configured to send a mode configuration instruction to the target memory, so that the target memory configures the test mode into a first register mode and a second register mode based on the mode configuration instruction; the sending module is also used for sending a command word sequence to the target memory through the command word line when the target memory is in the first register mode; a data reading module 1304 that is further configured to: when the target memory is in the second register mode, a first sequence of target instruction words is read from the target memory based on the target data interface.

In one embodiment, the mode configuration instructions include a first mode configuration instruction and a second mode configuration instruction; a mode configuration module 1310, further configured to: initializing an instruction processing circuit; configuring a test mode of the instruction processing circuit into a first register mode based on a first mode configuration instruction; the test mode of the instruction processing circuit is configured to be the second register mode based on the second mode configuration instruction.

In one embodiment, the instruction sending module 1302 is further configured to: sending an instruction word sequence to a target memory through an instruction word line so that the target memory shifts the instruction word sequence based on an instruction processing circuit to obtain a first target instruction word sequence; or at least two instruction word sequences are sent to the target memory through the instruction word line, so that the target memory compresses the at least two instruction word sequences, and the compressed instruction word sequences are shifted based on the instruction processing circuit to obtain a first target instruction word sequence.

In one embodiment, the target algorithm comprises at least one of a compression algorithm and a shift algorithm; the instruction processing module 1306 is further configured to: when the command word sequence is sent, shifting the command word sequence based on a shifting algorithm to obtain a second target command word sequence; and when at least two instruction word sequences are sent, compressing the at least two instruction word sequences based on a compression algorithm, and shifting the compressed instruction word sequences based on a shifting algorithm to obtain a second target instruction word sequence.

In one embodiment, the target storage is high bandwidth memory; the target data interface is a data reading interface based on a target protocol standard.

The respective modules in the fault detection apparatus of the instruction word line described above may be implemented in whole or in part by software, hardware, and a combination thereof. The modules can be embedded in a hardware form or independent from a processor in the computer device, and can also be stored in a memory in the computer device in a software form, so that the processor can call and execute operations corresponding to the modules.

In one embodiment, a computer device is provided, which may be a server, and its internal structure diagram may be as shown in fig. 15. The computer device includes a processor, a memory, an Input/Output interface (I/O for short), and a communication interface. The processor, the memory and the input/output interface are connected through a system bus, and the communication interface is connected to the system bus through the input/output interface. Wherein the processor of the computer device is configured to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system, a computer program, and a database. The internal memory provides an environment for the operation of an operating system and computer programs in the non-volatile storage medium. The database of the computer device is used for storing instruction word data. The input/output interface of the computer device is used for exchanging information between the processor and an external device. The communication interface of the computer device is used for connecting and communicating with an external terminal through a network. The computer program is executed by a processor to implement a method of fault detection for an instruction word line.

In one embodiment, a computer device is provided, which may be a terminal, and its internal structure diagram may be as shown in fig. 16. The computer apparatus includes a processor, a memory, an input/output interface, a communication interface, a display unit, and an input device. The processor, the memory and the input/output interface are connected by a system bus, and the communication interface, the display unit and the input device are connected by the input/output interface to the system bus. Wherein the processor of the computer device is configured to provide computing and control capabilities. The memory of the computer device comprises a nonvolatile storage medium and an internal memory. The non-volatile storage medium stores an operating system and a computer program. The internal memory provides an environment for the operation of an operating system and computer programs in the non-volatile storage medium. The input/output interface of the computer device is used for exchanging information between the processor and an external device. The communication interface of the computer device is used for communicating with an external terminal in a wired or wireless manner, and the wireless manner can be realized through WIFI, a mobile cellular network, NFC (near field communication) or other technologies. The computer program is executed by a processor to implement a method of fault detection for an instruction word line. The display unit of the computer equipment is used for forming a visual picture, and can be a display screen, a projection device or a virtual reality imaging device, the display screen can be a liquid crystal display screen or an electronic ink display screen, the input device of the computer equipment can be a touch layer covered on the display screen, a key, a track ball or a touch pad arranged on a shell of the computer equipment, and can also be an external keyboard, a touch pad or a mouse and the like.

It will be appreciated by those skilled in the art that the configurations shown in fig. 15 or 16 are block diagrams of only some of the configurations relevant to the present application, and do not constitute a limitation on the computing devices to which the present application may be applied, and that a particular computing device may include more or less components than those shown, or may combine certain components, or have a different arrangement of components.

In one embodiment, a computer device is further provided, which includes a memory and a processor, the memory stores a computer program, and the processor implements the steps of the above method embodiments when executing the computer program.

In an embodiment, a computer-readable storage medium is provided, on which a computer program is stored which, when being executed by a processor, carries out the steps of the above-mentioned method embodiments.

In an embodiment, a computer program product is provided, comprising a computer program which, when executed by a processor, carries out the steps in the method embodiments described above.

It should be noted that, the user information (including but not limited to user equipment information, user personal information, etc.) and data (including but not limited to data for analysis, stored data, displayed data, etc.) referred to in the present application are information and data authorized by the user or sufficiently authorized by each party, and the collection, use and processing of the related data need to comply with the relevant laws and regulations and standards of the relevant country and region.

It will be understood by those skilled in the art that all or part of the processes of the methods of the embodiments described above can be implemented by hardware instructions of a computer program, which can be stored in a non-volatile computer-readable storage medium, and when executed, can include the processes of the embodiments of the methods described above. Any reference to memory, database, or other medium used in the embodiments provided herein may include at least one of non-volatile and volatile memory. The nonvolatile Memory may include Read-Only Memory (ROM), magnetic tape, floppy disk, flash Memory, optical Memory, high-density embedded nonvolatile Memory, resistive Random Access Memory (ReRAM), Magnetic Random Access Memory (MRAM), Ferroelectric Random Access Memory (FRAM), Phase Change Memory (PCM), graphene Memory, and the like. Volatile Memory can include Random Access Memory (RAM), external cache Memory, and the like. By way of illustration and not limitation, RAM can take many forms, such as Static Random Access Memory (SRAM) or Dynamic Random Access Memory (DRAM), among others. The databases referred to in various embodiments provided herein may include at least one of relational and non-relational databases. The non-relational database may include, but is not limited to, a block chain based distributed database, and the like. The processors referred to in the various embodiments provided herein may be, without limitation, general purpose processors, central processing units, graphics processors, digital signal processors, programmable logic devices, quantum computing-based data processing logic devices, or the like.

The technical features of the above embodiments can be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the above embodiments are not described, but should be considered as the scope of the present specification as long as there is no contradiction between the combinations of the technical features.

The above-mentioned embodiments only express several embodiments of the present application, and the description thereof is specific and detailed, but not construed as limiting the scope of the present application. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the concept of the present application, which falls within the scope of protection of the present application. Therefore, the protection scope of the present application shall be subject to the appended claims.

Claims

1. A method of fault detection for a line of instruction words, the method comprising:

2. The method of claim 1, wherein said detecting a line fault occurring in the transmission of an instruction word by the line of instruction words based on the first sequence of target instruction words and the second sequence of target instruction words comprises:

comparing the instruction word of each data bit in the first target instruction word sequence with the instruction word of the corresponding data bit in the second target instruction word sequence in sequence to obtain a comparison result;

when the comparison result shows that the instruction words are the same, determining that no path fault occurs in the instruction word transmission process of the instruction word line;

and when the comparison result shows that the instruction words of the target data bits are different, determining that a line fault occurs in the instruction word line in the instruction word transmission process.

3. A method according to claim 2, characterized in that the number of instruction word lines is the same as the number of instruction word combinations in the instruction word sequence; each of the instruction word combinations comprises a rising edge instruction word and a falling edge instruction word;

when the comparison result indicates that the instruction words of the target data bits are different, determining that a line fault occurs in the instruction word line in the instruction word transmission process includes:

when the comparison result shows that the instruction words with target data bits are different, determining a target instruction word line corresponding to the target data bits in the number of instruction word lines;

and determining that the line fault of the target instruction word line occurs in the instruction word transmission process.

4. The method of claim 2, wherein the combination of instruction words comprises a combination of row instruction words, a combination of clock cycle instruction words, and a combination of column instruction words, the combination of column instruction words comprising a parity instruction word; the method further comprises the following steps:

and when the command word of the target data bit is the parity command word, determining that a command word line corresponding to the parity command word has a fault in the command word transmission process.

5. The method of claim 4, wherein the combination of line instruction words includes a line rising edge instruction word and a line falling edge instruction word;

the clock cycle instruction word combination comprises a rising edge clock cycle instruction word and a falling edge clock cycle instruction word;

the column instruction word combination includes a column rising edge instruction word and a column falling edge instruction word.

6. The method of claim 2, further comprising:

and when the comparison result shows that the instruction words of the target data bits are different, determining the positions of the target data bits in the instruction word sequence and the number of the instruction word lines corresponding to the target data bits.

7. The method of claim 1, further comprising:

sending a mode configuration instruction to a target memory to enable the target memory to configure a test mode into a first register mode and a second register mode based on the mode configuration instruction;

the sending of the sequence of instruction words to the target memory via the instruction word line comprises:

sending a sequence of instruction words to a target memory through an instruction word line when the target memory is in the first register mode;

the reading of the first target instruction word sequence in the target memory through the target data interface comprises:

reading the first sequence of target instruction words from the target memory based on a target data interface when the target memory is in the second register mode.

8. The method of claim 7, wherein the mode configuration instructions comprise a first mode configuration instruction and a second mode configuration instruction;

the configuring a test mode into a first register mode and a second register mode based on the mode configuration instruction includes:

initializing the instruction processing circuit;

configuring a test mode of the instruction processing circuit to be a first register mode based on the first mode configuration instruction;

configuring a test mode of the instruction processing circuit to a second register mode based on the second mode configuration instruction.

9. The method of claim 7, wherein sending a sequence of instruction words to a target memory via an instruction word line, so that the target memory performs instruction processing on the sequence of instruction words based on an instruction processing circuit to obtain a first sequence of target instruction words comprises:

sending an instruction word sequence to a target memory through an instruction word line so that the target memory shifts the instruction word sequence based on an instruction processing circuit to obtain a first target instruction word sequence; alternatively, the first and second electrodes may be,

at least two instruction word sequences are sent to a target memory through an instruction word line, so that the target memory compresses the at least two instruction word sequences, and the compressed instruction word sequences are shifted based on an instruction processing circuit to obtain a first target instruction word sequence.

10. The method of claim 9, wherein the target algorithm comprises at least one of a compression algorithm and a shift algorithm; the instruction processing of the instruction word sequence based on the target algorithm to obtain a second target instruction word sequence includes:

when an instruction word sequence is sent, shifting the instruction word sequence based on the shifting algorithm to obtain a second target instruction word sequence;

and when at least two instruction word sequences are sent, compressing the at least two instruction word sequences based on the compression algorithm, and shifting the compressed instruction word sequences based on the shifting algorithm to obtain a second target instruction word sequence.

11. The method of any one of claims 1 to 10, wherein the target storage is a high bandwidth memory; the target data interface is a data reading interface based on a target protocol standard.

12. An apparatus for fault detection of a command word line, the apparatus comprising:

13. A computer device comprising a memory and a processor, the memory storing a computer program, characterized in that the processor realizes the steps of the method of any one of claims 1 to 11 when executing the computer program.

14. A computer-readable storage medium, on which a computer program is stored, which, when being executed by a processor, carries out the steps of the method of any one of claims 1 to 11.

15. A computer program product comprising a computer program, characterized in that the computer program realizes the steps of the method of any one of claims 1 to 11 when executed by a processor.