CN115346593A

CN115346593A - Memory fault repairing method and device, computer equipment and storage medium

Info

Publication number: CN115346593A
Application number: CN202210968981.3A
Authority: CN
Inventors: 强鹏
Original assignee: Tencent Technology Shenzhen Co Ltd
Current assignee: Tencent Technology Shenzhen Co Ltd
Priority date: 2022-08-12
Filing date: 2022-08-12
Publication date: 2022-11-15

Abstract

The application relates to a memory failure recovery method, a memory failure recovery device, a computer device, a storage medium and a computer program product. The application relates to artificial intelligence technology. The method comprises the following steps: acquiring target remapping information corresponding to a current fault interface in a memory; the target remapping information is obtained by reallocating mapping relations between each instruction signal bit corresponding to the memory access instruction and the instruction transmission interfaces in the normal interface and the redundant interface based on the position relation between the current fault interface and other instruction transmission interfaces, and the instruction transmission interfaces are used for transmitting signal data corresponding to corresponding instruction signal bits in the memory access instruction; and generating a fault repairing instruction carrying the target remapping information, and sending the fault repairing instruction to the memory so that the memory receives a memory access instruction through the normal interface and the redundant interface based on the target remapping information, thereby ensuring that the memory correctly receives the memory access instruction.

Description

Memory fault repairing method and device, computer equipment and storage medium

Technical Field

The present application relates to the field of computer technologies, and in particular, to a method and an apparatus for repairing a memory failure, a computer device, a storage medium, and a computer program product.

Background

With the development of computer technology, various memories, such as a High Bandwidth Memory (HBM), have appeared, and the HBM is a new type of High-speed High-Bandwidth Memory. The device may send memory access instructions to the memory, which may receive the memory access instructions through the instruction transmission interface.

In the conventional technology, if a command transmission interface of a memory fails, the memory cannot normally receive a memory access command.

Disclosure of Invention

In view of the foregoing, it is necessary to provide a memory fault repairing method, apparatus, computer device, computer readable storage medium and computer program product capable of normally receiving a memory access instruction in case of a fault of an instruction transmission interface.

The application provides a memory fault repairing method. The method comprises the following steps:

acquiring target remapping information corresponding to a current fault interface in a memory; the target remapping information is obtained by reallocating mapping relations between each instruction signal bit corresponding to the memory access instruction and the instruction transmission interfaces in the normal interface and the redundant interface based on the position relation between the current fault interface and other instruction transmission interfaces, wherein the instruction transmission interfaces are used for transmitting signal data corresponding to corresponding instruction signal bits in the memory access instruction;

and generating a fault repairing instruction carrying the target remapping information, and sending the fault repairing instruction to the memory so that the memory receives a memory access instruction through the normal interface and the redundant interface based on the target remapping information.

The application also provides a device for repairing the memory fault. The device comprises:

the remapping information acquisition module is used for acquiring target remapping information corresponding to a current fault interface in the memory; the target remapping information is obtained by reallocating mapping relations between each instruction signal bit corresponding to the memory access instruction and the instruction transmission interfaces in the normal interface and the redundant interface based on the position relation between the current fault interface and other instruction transmission interfaces, wherein the instruction transmission interfaces are used for transmitting signal data corresponding to corresponding instruction signal bits in the memory access instruction;

and the fault repairing instruction sending module is used for generating a fault repairing instruction carrying the target remapping information and sending the fault repairing instruction to the memory so that the memory receives a memory access instruction through the normal interface and the redundant interface based on the target remapping information.

A computer device comprising a memory and a processor, the memory storing a computer program, the processor implementing the steps of the memory fault recovery method when executing the computer program.

A computer-readable storage medium, on which a computer program is stored which, when being executed by a processor, carries out the steps of the above-mentioned memory fault recovery method.

A computer program product comprising a computer program which, when executed by a processor, carries out the steps of the above-mentioned memory fail-over method.

According to the memory fault repairing method, the memory fault repairing device, the computer equipment, the storage medium and the computer program product, the target remapping information corresponding to the current fault interface in the memory is obtained, the fault repairing instruction carrying the target remapping information is generated, and the fault repairing instruction is sent to the memory, so that the memory receives the memory access instruction through the normal interface and the redundant interface based on the target remapping information. The target remapping information is obtained by reallocating mapping relations between each instruction signal bit corresponding to the memory access instruction and the instruction transmission interfaces in the normal interface and the redundant interface based on the position relation between the current fault interface and other instruction transmission interfaces, and the instruction transmission interfaces are used for transmitting signal data corresponding to corresponding instruction signal bits in the memory access instruction. Therefore, if the instruction transmission interface in the memory fails, the mapping relation between each instruction signal bit corresponding to the memory access instruction and the instruction transmission interface is redistributed in the normal interface and the redundant interface, so that the memory can skip the current failed interface when receiving the memory access instruction, and the signal data corresponding to each instruction signal bit in the memory access instruction is received through the normal interface and the redundant interface, so that the memory can correctly receive the memory access instruction. And when the mapping relation is redistributed, the mapping relation between the normal interface and the redundant interface and the command signal bit is redistributed based on the position relation between the current fault interface and other command transmission interfaces, so that the memory can intelligently skip the current fault interface when receiving the memory access command, and orderly receive the signal data corresponding to each command signal bit in the memory access command through the normal interface and the redundant interface, thereby the memory can quickly and accurately receive the memory access command. And sending a fault repairing instruction carrying target remapping information which corresponds to the current fault interface and is determined by the mapping relation between the redistribution instruction signal bit and the instruction transmission interface to the memory, wherein the memory can quickly repair the fault, and thus, the memory access instruction is quickly and accurately received.

acquiring a fault repairing instruction; the fault repairing instruction carries target remapping information corresponding to a current fault interface in a memory, the target remapping information is obtained by reallocating mapping relations between each instruction signal bit corresponding to a memory access instruction and the instruction transmission interfaces in a normal interface and a redundant interface based on the position relation between the current fault interface and other instruction transmission interfaces, and the instruction transmission interfaces are used for transmitting signal data corresponding to corresponding instruction signal bits in the memory access instruction;

receiving a memory access instruction through the normal interface and the redundant interface based on the target remapping information.

the fault repairing instruction acquisition module is used for acquiring a fault repairing instruction; the fault repairing instruction carries target remapping information corresponding to a current fault interface in a memory; the target remapping information is obtained by reallocating mapping relations between each instruction signal bit corresponding to the memory access instruction and the instruction transmission interface in the normal interface and the redundant interface based on the position relation between the current fault interface and other instruction transmission interfaces, and the instruction transmission interface is used for transmitting signal data corresponding to the corresponding instruction signal bit in the memory access instruction;

and the memory access instruction receiving module is used for receiving a memory access instruction through the normal interface and the redundant interface based on the target remapping information.

A computer program product comprising a computer program which, when executed by a processor, carries out the steps of the above-mentioned memory fault repair method.

The memory fault repairing method, the memory fault repairing device, the computer equipment, the storage medium and the computer program product obtain the fault repairing instruction and receive the memory access instruction through the normal interface and the redundant interface based on the target remapping information. The fault repairing instruction carries target remapping information corresponding to a current fault interface in the memory, the target remapping information is obtained by reallocating mapping relations between each instruction signal bit corresponding to the memory access instruction and the instruction transmission interfaces in the normal interface and the redundant interface based on the position relation between the current fault interface and other instruction transmission interfaces, and the instruction transmission interfaces are used for transmitting signal data corresponding to corresponding instruction signal bits in the memory access instruction. Therefore, if the instruction transmission interface in the memory fails, the mapping relation between each instruction signal bit corresponding to the memory access instruction and the instruction transmission interface is redistributed in the normal interface and the redundant interface, so that the memory can skip the current failed interface when receiving the memory access instruction, and the signal data corresponding to each instruction signal bit in the memory access instruction is received through the normal interface and the redundant interface, so that the memory can correctly receive the memory access instruction. And when the mapping relation is redistributed, the mapping relation between the normal interface and the redundant interface and the command signal bit is redistributed based on the position relation between the current fault interface and other command transmission interfaces, so that the memory can intelligently skip the current fault interface when receiving the memory access command, and orderly receive the signal data corresponding to each command signal bit in the memory access command through the normal interface and the redundant interface, so that the memory can quickly and accurately receive the memory access command. And sending a fault repairing instruction carrying target remapping information which corresponds to the current fault interface and is determined by the mapping relation between the redistribution instruction signal bit and the instruction transmission interface to the memory, wherein the memory can quickly repair the fault, and thus, the memory access instruction is quickly and accurately received.

Drawings

FIG. 1 is a diagram of an embodiment of a memory failover method;

FIG. 2 is a flow diagram illustrating a method for memory failover in one embodiment;

FIG. 3 is a schematic diagram illustrating various line instructions in one embodiment;

FIG. 4 is a diagram illustrating various column instructions in one embodiment;

FIG. 5A is a diagram illustrating an exemplary activation command issue timing sequence;

FIG. 5B is a timing diagram illustrating refresh command issue in one embodiment;

FIG. 5C is a timing diagram illustrating the issue of a read command in one embodiment;

FIG. 6A is a diagram illustrating remapping relationships and remapping codes associated with a line command transport interface, according to an embodiment;

FIG. 6B is a diagram illustrating remapping relationships and remapping encodings corresponding to a column command transport interface, according to an embodiment;

FIG. 7 is a flow chart illustrating a method for memory failover in another embodiment;

FIG. 8 is a flow chart illustrating a method for memory failover in another embodiment;

FIG. 9 is a graphical illustration of the effect of voltage change, temperature change on clock delay in one embodiment;

FIG. 10 is a flow chart illustrating a method for memory failover in another embodiment;

FIG. 11 is a block diagram of a memory fail recovery apparatus in one embodiment;

FIG. 12 is a block diagram showing the construction of a memory fail recovery apparatus according to another embodiment;

FIG. 13 is a diagram showing an internal structure of a computer device in one embodiment;

fig. 14 is an internal structural diagram of a computer device in another embodiment.

Detailed Description

In order to make the objects, technical solutions and advantages of the present application more apparent, the present application is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present application and are not intended to limit the present application.

The embodiment of the invention can be applied to various scenes including but not limited to cloud technology, artificial intelligence, intelligent traffic, driving assistance and the like.

The artificial intelligence technology is a comprehensive subject and relates to the field of extensive technology, namely the technology of a hardware level and the technology of a software level. The artificial intelligence infrastructure generally includes technologies such as sensors, dedicated artificial intelligence chips, cloud computing, distributed storage, big data processing technologies, operation/interaction systems, mechatronics, and the like. The artificial intelligence software technology mainly comprises a computer vision technology, a voice processing technology, a natural language processing technology, machine learning/deep learning and the like.

The scheme provided by the embodiment of the application relates to the technologies of artificial intelligence chips, big data processing and the like, and is specifically explained by the following embodiments:

the memory failure recovery method provided by the embodiment of the application can be applied to the application environment shown in fig. 1. Wherein the terminal 102 communicates with the server 104 via a network. The data storage system may store data that the server 104 needs to process. The data storage system may be integrated on the server 104, or may be placed on the cloud or other server. The terminal 102 may be, but is not limited to, various desktop computers, notebook computers, smart phones, tablet computers, internet of things devices, and portable wearable devices, and the internet of things devices may be smart speakers, smart televisions, smart air conditioners, smart car-mounted devices, and the like. The portable wearable device can be a smart watch, a smart bracelet, a head-mounted device, and the like. The server 104 may be implemented as a stand-alone server or a server cluster composed of a plurality of servers or a cloud server.

The server 104 acquires target remapping information corresponding to a current failure interface in the memory; the target remapping information is obtained by reallocating mapping relations between each instruction signal bit corresponding to the memory access instruction and the instruction transmission interfaces in the normal interface and the redundant interface based on the position relation between the current fault interface and other instruction transmission interfaces, and the instruction transmission interfaces are used for transmitting signal data corresponding to corresponding instruction signal bits in the memory access instruction. The server 104 generates a fault repairing instruction carrying the target remapping information, and sends the fault repairing instruction to the memory, so that the memory receives a memory access instruction through the normal interface and the redundant interface based on the target remapping information.

The terminal 102 may obtain target remapping information corresponding to a current faulty interface in the memory; the target remapping information is obtained by reallocating mapping relations between each instruction signal bit corresponding to the memory access instruction and the instruction transmission interfaces in the normal interface and the redundant interface based on the position relation between the current fault interface and other instruction transmission interfaces, and the instruction transmission interfaces are used for transmitting signal data corresponding to corresponding instruction signal bits in the memory access instruction. The terminal 102 generates a fault repairing instruction carrying the target remapping information, and sends the fault repairing instruction to the memory, so that the memory receives a memory access instruction through the normal interface and the redundant interface based on the target remapping information.

In one embodiment, as shown in fig. 2, a memory failure recovery method is provided, and the method can be applied to a computer device, where the computer device can be a terminal or a server, and is executed by the terminal or the server itself separately, or can be implemented through interaction between the terminal and the server. The embodiment is described by taking the method applied to the computer device as an example, and comprises the following steps:

step S202, obtaining target remapping information corresponding to a current fault interface in a memory; the target remapping information is obtained by reallocating mapping relations between each instruction signal bit corresponding to the memory access instruction and the instruction transmission interfaces in the normal interface and the redundant interface based on the position relation between the current fault interface and other instruction transmission interfaces, and the instruction transmission interfaces are used for transmitting signal data corresponding to corresponding instruction signal bits in the memory access instruction.

The instruction transmission interface is an interface provided by the memory and is used for transmitting signal data corresponding to corresponding instruction signal bits in the memory access instruction, so that the memory can receive the memory access instruction sent from the outside. The current fault interface is an instruction transmission interface which has faults and is appointed with an initial instruction signal bit. The normal interface is an instruction transmission interface which does not have a fault at present and has designated an initial instruction signal bit. Redundant interfaces refer to redundant command transfer interfaces that do not specify the original command signal bits.

The memory access instruction is an instruction for accessing the memory to implement corresponding operation control on the memory, that is, by sending the memory access instruction to the memory, corresponding operation control on the memory can be implemented. For example, the memory access instruction may be an activation instruction for activating the memory; the memory access instruction may be a refresh instruction for refreshing data stored by the memory; and so on. It will be appreciated that a memory access instruction may comprise a plurality of instruction signal bits, each for storing corresponding signal data. For example, a memory access instruction includes six bits of data, any one bit of data representing a signal data, and any one bit of data corresponding to a command signal bit.

In the memory, except for the redundant interface, each instruction transmission interface has a corresponding initial instruction signal bit, that is, except for the redundant interface, an initial mapping relationship exists between each instruction transmission interface and each instruction signal bit. The initial instruction signal bit refers to an instruction signal bit corresponding to the beginning of each instruction transmission interface, and each instruction transmission interface defaults to a corresponding instruction signal bit. The initial mapping relationship is a mapping relationship between the command transmission interface and the corresponding initial command signal bit. For example, assume that the memory includes eight command transmission interfaces, which are command transmission interfaces a-H, respectively, where the command transmission interface H is a redundant interface, the memory access command includes seven bits of data, and the memory access command corresponds to seven command signal bits, which are command signal bits a-g, respectively. The initial instruction signal bit corresponding to the instruction transmission interface A is a, the initial instruction signal bit corresponding to the instruction transmission interface B is B, the initial instruction signal bit corresponding to the instruction transmission interface C is C, the initial instruction signal bit corresponding to the instruction transmission interface D is D, the initial instruction signal bit corresponding to the instruction transmission interface E is E, the initial instruction signal bit corresponding to the instruction transmission interface F is F, and the initial instruction signal bit corresponding to the instruction transmission interface G is G. The redundant interface temporarily has no corresponding initial command signal bit. If the instruction transmission interface A has a fault, the current fault interface is the instruction transmission interface A, the normal interface is the instruction transmission interface B-H, and the redundant interface is the instruction transmission interface H.

The instruction transmission interfaces respectively have corresponding remapping information, and the remapping information is used for performing corresponding fault repair on the memory when the corresponding instruction transmission interface has a fault. The target remapping information refers to remapping information corresponding to a current fault interface. The remapping information is obtained by reallocating mapping relations between each instruction signal bit corresponding to the memory access instruction and the instruction transmission interface in the normal interface and the redundant interface based on the position relation of the fault interface and other instruction transmission interfaces. The target remapping information is obtained by reallocating mapping relations between each instruction signal bit corresponding to the memory access instruction and the instruction transmission interface in the normal interface and the redundant interface based on the position relation between the current fault interface and other instruction transmission interfaces.

And on the basis of the position relationship between the current fault interface and other instruction transmission interfaces, redistributing the mapping relationship between each instruction signal bit corresponding to the memory access instruction and the instruction transmission interface in the normal interface and the redundant interface, so that when the memory receives the memory access instruction, signal data on the corresponding instruction signal bit in the memory access instruction are transmitted through the normal interface and the redundant interface on the basis of the mapping relationship obtained by redistribution, and the memories sort according to the positions of the instruction transmission interfaces and sequentially read the signal data transmitted by the normal interface and the redundant interface, thereby obtaining a complete memory access instruction. When the memory receives the memory access instruction, the signal data are not required to be read first and then arranged, the signal data transmitted by the normal interface and the signal data transmitted by the redundant interface are read in sequence according to the position sequence of the instruction transmission interface, and the complete memory access instruction can be obtained quickly.

It is understood that there may be at least one redundant interface in the memory.

In one embodiment, a memory test instruction is sent to memory; acquiring an instruction response signal returned by the memory; the command response signal comprises a check signal; determining an operating state of the memory based on the check signal; and when the working state is the fault state, determining the current fault interface by detecting the working state corresponding to each instruction transmission interface.

Specifically, in determining the currently failed interface, the computer device may determine whether the memory failed, and then determine which instruction transmission interface failed. The computer device can send a memory test instruction to the memory, the memory can return an instruction response signal to the computer device, and the computer device determines the working state of the memory based on a verification signal in the instruction response signal returned by the memory. If the check signal is a preset signal, the working state of the memory is determined to be a normal state, the memory does not have a command transmission interface with a fault at present, and the memory can normally receive a memory access command. If the check signal is not the preset signal, the working state of the memory is determined to be a fault state, a command transmission interface with a fault exists in the memory at present, and the memory cannot receive the memory access command correctly at present. When the working state of the memory is a fault state, further determining which instruction transmission interface fails, and determining the current fault interface by detecting the working state corresponding to each instruction transmission interface by the computer device. For example, the operating state corresponding to each instruction transmission interface may be detected in an EXTEST test mode (also referred to as an external test), and the instruction transmission interface whose operating state is a fault state is used as the current fault interface.

And step S204, generating a fault repairing instruction carrying the target remapping information, and sending the fault repairing instruction to the memory so that the memory receives a memory access instruction through the normal interface and the redundant interface based on the target remapping information.

The failure recovery instruction is an instruction for instructing the memory to perform failure recovery.

Specifically, the computer device determines a current failure interface in the memory, obtains target remapping information corresponding to the current failure interface in the memory locally or from other devices, generates a failure repairing instruction carrying the target remapping information, and sends the failure repairing instruction to the memory. The memory may skip the currently failing interface and receive memory access instructions through the normal interface and the redundant interface based on the target remapping information.

In one embodiment, a high bandwidth memory system is deployed in a computer device, the high bandwidth memory system including a host and a storage. The computer equipment can acquire target remapping information corresponding to a current fault interface in the memory through the host, generate a fault repairing instruction carrying the target remapping information through the host, and send the fault repairing instruction to the memory through the host.

In one embodiment, the memory may be a dynamic random access memory, a random access memory, or other types of memory.

In one embodiment, the memory access instructions include a row instruction and a column instruction. Correspondingly, the memory comprises a row instruction transmission interface used for transmitting the signal data corresponding to the row instruction signal bit corresponding to the row instruction and a column instruction transmission interface used for transmitting the signal data corresponding to the column instruction signal bit corresponding to the column instruction. And if the current fault interface is a line instruction fault interface, the target remapping information is obtained by reallocating the mapping relation between each line instruction signal bit corresponding to the memory access instruction and the line instruction transmission interface in the normal line instruction interface and the redundant line instruction interface based on the position relation between the line instruction fault interface and other line instruction transmission interfaces. And if the current fault interface is the column instruction fault interface, the target remapping information is obtained by reallocating the mapping relation between each column instruction signal bit corresponding to the memory access instruction and the column instruction transmission interface in the normal column instruction interface and the redundant column instruction interface based on the position relation between the column instruction fault interface and other column instruction transmission interfaces.

In one embodiment, as shown in fig. 3, the line instruction may specifically include a line No Operation instruction (Row No Operation instruction), an Activate instruction (active instruction), a Precharge instruction (Precharge instruction), a Precharge All instruction (Precharge All instruction), a Single Bank Refresh instruction (Single Bank Refresh instruction), a Refresh instruction (Refresh instruction), a Power-Down Entry instruction (Power-Down Entry instruction), a Self Refresh Entry instruction (Self Refresh Entry instruction), and a Power-Down instruction/auto Refresh Exit instruction (Power-Down/Self Refresh Exit instruction). The line instruction corresponds to seven line instruction signal bits R0 to R7, i.e., the line instruction includes seven fields. Wherein, the H field represents 1,L field represents 0,V field may represent 1 or 0, the PAR (Party) field represents an instruction check field, the BA (Bank Address) field represents a Bank Address, the RA (Row Address) field represents a Row Address, and the SID (Stack ID) represents an identification number of the Stack.

In one embodiment, as shown in fig. 4, the Column instruction may specifically include a Column No Operation instruction (Column No Operation instruction), a Read instruction (Read instruction), a Read instruction with Auto-Precharge (Read w/AP), a Write instruction (Write instruction), a Write instruction with Auto-Precharge (Write w/AP), and a Mode Register configuration instruction (Mode Register Set instruction). The column instruction corresponds to nine column instruction signal bits C0-C8, i.e., the column instruction includes nine fields. Wherein the H field represents 1,L field represents 0,V field may represent 1 or 0, PAR field represents instruction check field, BA field represents Bank Address, CA (Column Address) field represents Column Address, SID represents stack identification number, OP field represents operation code.

It should be understood that, for the number of the row instruction signal bits and the column instruction signal bits, the embodiments of the present application are only for illustration, and do not specifically limit the number of the row instruction signal bits and the column instruction signal bits.

The computer device needs to transmit the corresponding signal data at the timing to be followed by the respective instructions. For example, as shown in fig. 5A, referring to the details of the Activate instruction (i.e., activate instruction) in fig. 3, the fields (corresponding to R0 to R6) in the Activate instruction are to be sent at the corresponding timings. The activate instruction is a two-cycle instruction, occupying two clock cycles in total. As shown in fig. 5B, referring to the details of the Refresh command (i.e., refresh command) in fig. 3, each field (corresponding to R0 to R6) in the Refresh command is sent at a corresponding timing. The refresh command is a single cycle command, occupying one clock cycle. As shown in fig. 5C, referring to the details of the Read instruction (i.e., read instruction) in fig. 4, the fields (corresponding to C0 to C8) in the Read instruction are sent at the corresponding timing. Where clock 1 and clock 2 are two differential clocks. EN AP (Enable Auto Precharge) indicates that Auto Precharge is enabled. DIS AP (Disable Auto Precharge) indicates that Auto Precharge is disabled.

The transmission of the memory access command is easily affected by the environment change of PVT (process voltage Temperature) and the crosstalk between signals, which causes the command transmission interface to malfunction or damage during the operation of the memory. According to the memory fault repairing method, when operation faults occur in some instruction transmission channels of the memory, the mapping relation between each instruction signal bit corresponding to the memory access instruction and the instruction transmission interface is redistributed in the normal interface and the redundant interface, repairing can be conducted quickly, and the memory can be guaranteed to receive the memory access instruction correctly.

In the memory fault repairing method, the target remapping information corresponding to the current fault interface in the memory is obtained, the fault repairing instruction carrying the target remapping information is generated, and the fault repairing instruction is sent to the memory, so that the memory receives the memory access instruction through the normal interface and the redundant interface based on the target remapping information. The target remapping information is obtained by reallocating mapping relations between each instruction signal bit corresponding to the memory access instruction and the instruction transmission interfaces in the normal interface and the redundant interface based on the position relation between the current fault interface and other instruction transmission interfaces, and the instruction transmission interfaces are used for transmitting signal data corresponding to corresponding instruction signal bits in the memory access instruction. Therefore, if the instruction transmission interface in the memory fails, the mapping relation between each instruction signal bit corresponding to the memory access instruction and the instruction transmission interface is redistributed in the normal interface and the redundant interface, so that the memory can skip the current failed interface when receiving the memory access instruction, and the signal data corresponding to each instruction signal bit in the memory access instruction is received through the normal interface and the redundant interface, so that the memory can correctly receive the memory access instruction. And when the mapping relation is redistributed, the mapping relation between the normal interface and the redundant interface and the command signal bit is redistributed based on the position relation between the current fault interface and other command transmission interfaces, so that the memory can intelligently skip the current fault interface when receiving the memory access command, and orderly receive the signal data corresponding to each command signal bit in the memory access command through the normal interface and the redundant interface, so that the memory can quickly and accurately receive the memory access command. And sending the fault repairing instruction carrying the target remapping information corresponding to the current fault interface and determined by the mapping relation between the redistribution instruction signal bit and the instruction transmission interface to the memory, wherein the memory can quickly repair the fault, so that the memory access instruction is quickly and accurately received.

In one embodiment, the memory fault recovery method further comprises:

acquiring interface position sequencing information; determining candidate fault interfaces from each instruction transmission interface; generating remapping information corresponding to the candidate fault interface based on the interface position sorting information and the interface position corresponding to the candidate fault interface; the remapping information is used for indicating and keeping the initial mapping relation between the forward interface of the candidate fault interface and the initial instruction signal bit unchanged, and establishing the mapping relation between the initial instruction signal bit corresponding to the candidate fault interface and the backward interface of the candidate fault interface and the respective corresponding adjacent backward non-fault interface; and taking the next instruction transmission interface as a candidate fault interface, returning to the interface position corresponding to the candidate fault interface based on the interface position sequencing information and the candidate fault interface, and executing the step of generating the remapping information corresponding to the candidate fault interface until the remapping information corresponding to each instruction transmission interface is obtained.

The interface position ordering information is used for representing the interface position ordering of each instruction transmission interface. The candidate failing interface refers to the instruction transport interface that is supposed to fail. The forward interface refers to the command transfer interface that is arranged before the candidate failing interface. The backward interface refers to an instruction transfer interface arranged after the candidate failed interface. The initial mapping relationship refers to a mapping relationship between the command transmission interface and the corresponding initial command signal bit. The initial command signal bit refers to a command signal bit corresponding to the beginning of each command transmission interface, and each command transmission interface defaults to the corresponding command signal bit. The adjacent backward non-fault interface is an interface which is adjacent to a certain command transmission interface, is arranged behind the command transmission interface and has no fault.

Specifically, the computer device may obtain the interface position sorting information, and generate remapping information corresponding to each instruction transmission interface based on the interface position sorting information. The computer device may randomly select one instruction transmission interface from the instruction transmission interfaces as a candidate fault interface, and generate remapping information corresponding to the candidate fault interface based on the interface position sorting information and the interface position corresponding to the candidate fault interface. The remapping information is used for indicating and keeping the initial mapping relation between the forward interface of the candidate fault interface and the instruction signal bit unchanged, and establishing a new mapping relation between the initial instruction signal bit corresponding to the candidate fault interface and the backward interface of the candidate fault interface and the adjacent backward non-fault interface corresponding to each.

For example, suppose the memory includes eight command transmission interfaces, namely, command transmission interfaces a-E, wherein the command transmission interface E is a redundant interface and the interface ordering information is a-B-C-D-E. The memory access instruction corresponds to four instruction signal bits, instruction signal bits a-c, respectively. The initial instruction signal bit corresponding to the instruction transmission interface A is a, the initial instruction signal bit corresponding to the instruction transmission interface B is B, the initial instruction signal bit corresponding to the instruction transmission interface C is C, the initial instruction signal bit corresponding to the instruction transmission interface D is D, and the corresponding initial instruction signal bit does not exist in the redundant interface temporarily. If the command transmission interface B has a fault, in the normal interface and the redundant interface, the mapping relation between the command transmission interface A and the command signal bit a is unchanged, a new mapping relation is established between the command transmission interface C and the command signal bit B, a new mapping relation is established between the command transmission interface D and the command signal bit C, and a new mapping relation is established between the command transmission interface E and the command signal bit D. The remapping information corresponding to the command transmission interface B is used for instructing the memory to sequentially transmit signal data corresponding to the command signal bits a-c through the command transmission interface A, C, D, E.

The generation mode of the remapping information corresponding to each instruction transmission interface is similar, and the computer device may use the next instruction transmission interface as a new candidate fault interface, and generate the remapping information corresponding to the candidate fault interface based on the interface position sorting information and the interface position corresponding to the candidate fault interface. Finally, the computer device can obtain the remapping information corresponding to each instruction transmission interface.

In an embodiment, the interface position sorting information may be sorted in an ascending order or in a descending order, and may be specifically determined according to factory interface configuration of a memory or according to actual needs.

In one embodiment, the command transfer interface includes a row command transfer interface and a column command transfer interface. The row command transmission interface and the column command transmission interface independently generate corresponding remapping information.

In the above embodiment, remapping information corresponding to the candidate fault interface is generated based on the interface position sorting information and the interface position corresponding to the candidate fault interface; the remapping information is used for indicating and keeping the initial mapping relation between the forward interface of the candidate fault interface and the initial instruction signal bit unchanged, and establishing the mapping relation between the initial instruction signal bit corresponding to the candidate fault interface and the backward interface of the candidate fault interface and the adjacent backward non-fault interface corresponding to each initial instruction signal bit. Therefore, the mapping relation is not required to be modified for all the normal interfaces and the redundant interfaces, and the mapping relation is only required to be modified for the candidate fault interfaces and the backward interfaces of the candidate fault interfaces, so that the modification efficiency can be guaranteed. Furthermore, the memory sequentially reads the signal data transmitted by the normal interface and the redundant interface according to the interface position sequencing information, so that a complete memory access instruction can be quickly obtained, and the reading efficiency of the memory access instruction is improved.

In one embodiment, generating remapping information corresponding to the candidate failed interface based on the interface position sorting information and the interface position corresponding to the candidate failed interface includes:

determining a remapping relation corresponding to the candidate fault interface based on the interface position sorting information and the interface position corresponding to the candidate fault interface; the remapping relation comprises a redetermined mapping relation between other instruction transmission interfaces and instruction signal bits under the condition that the candidate fault interface fails; and generating a remapping code corresponding to the remapping relation, and obtaining remapping information corresponding to the candidate fault interface based on the remapping code.

The remapping coding is the abbreviation representation of the remapping relation, and the complex remapping relation is referred to by simple coding data, so that the transmission data volume between the computer equipment and the memory can be effectively reduced.

Specifically, in order to reduce the amount of data to be sent, the computer device may agree in advance with the memory about a remapping relationship between another instruction transmission interface and an instruction signal bit when any instruction transmission interface fails, and specifically, the remapping relationship may be referred to by a remapping code.

When the remapping information is generated, the computer device may determine a remapping relationship corresponding to the candidate failed interface based on the interface position ordering information and the interface position corresponding to the candidate failed interface, where the remapping relationship includes a re-determined mapping relationship between other instruction transmission interfaces and the instruction signal bit in the case where the candidate failed interface fails. Further, the computer device may generate a remapping code corresponding to the remapping relationship, and obtain remapping information corresponding to the candidate failed interface based on the remapping code, where the remapping information includes the remapping code. The computer equipment sends the fault repairing instruction carrying the remapping codes to the memory, the memory can quickly determine the remapping relation corresponding to the remapping codes based on the remapping codes, signal data on corresponding instruction signal bits indicated by the remapping relation are transmitted through the normal interface and the redundant interface, and the signal data transmitted by the normal interface and the redundant interface are sequentially read, so that a complete memory access instruction can be obtained.

In one embodiment, the remapping code includes an interface identification corresponding to the candidate failing interface. After the memory receives the fault repairing instruction, the current fault instruction transmission interface can be quickly determined based on the fault interface identification carried by the fault repairing instruction, the corresponding remapping relation is determined, and the memory access instruction is correctly received through the normal interface and the redundant interface.

In the above embodiment, based on the interface position sorting information and the interface positions corresponding to the candidate faulty interfaces, the remapping relationship corresponding to the candidate faulty interfaces is determined, the remapping codes corresponding to the remapping relationship are generated, and the remapping information corresponding to the candidate faulty interfaces is obtained based on the remapping codes. Therefore, when the memory fails to have the command transmission interface, the fault can be repaired quickly by sending the remapping codes to the memory, and the repairing efficiency is effectively improved.

In one embodiment, the remapping codes are coded data with preset coding length, and different instruction transmission interfaces correspond to different remapping codes; in each candidate encoding data corresponding to the preset encoding length, except for the remapping encoding corresponding to each instruction transmission interface, other encoding data are used for representing and keeping the initial mapping relation between the instruction transmission interface and the instruction signal bit unchanged.

Specifically, the computer device and the memory may agree to use the encoded data with a predetermined encoding length as the remapped encoding. In order to distinguish different command transmission interfaces, different command transmission interfaces correspond to different remapping codes. In order to avoid that the memory cannot identify or identify errors, in each candidate encoding data corresponding to the preset encoding length, except for the remapping encoding corresponding to each instruction transmission interface, the rest encoding data is used for representing and keeping the initial mapping relation between the instruction transmission interface and the initial instruction signal bit unchanged.

In one embodiment, the command transfer interface comprises a line command transfer interface. Referring to fig. 6a, rx0 through RRx denote the row instruction transmission interfaces, and RRx denotes a redundant interface in the row instruction transmission interface. X in Rx0 through RRx represents the xth instruction lane, it being understood that the memory may include at least one instruction lane. XX in fig. 6A indicates that the corresponding line instruction transmission interface is malfunctioning. If Rx0 fails, the corresponding remap code is 0000; if Rx1 fails, the corresponding remap code is 0001; if Rx2 fails, the corresponding remap code is 0010; if Rx3 fails, the corresponding remapping code is 0011; if Rx4 fails, the corresponding remap code is 0100; if Rx5 fails, the corresponding remap code is 0101; if Rx6 fails, the corresponding remap code is 0110.

Taking Rx0 as an example, if Rx0 fails, the corresponding remapping relationship is used to indicate whether the signal data on the initial command signal bit corresponding to Rx6 is transmitted through Rx6, the signal data on the initial command signal bit corresponding to Rx0 is transmitted through Rx1, the signal data on the initial command signal bit corresponding to Rx1 is transmitted through Rx2, the signal data on the initial command signal bit corresponding to Rx2 is transmitted through Rx3, the signal data on the initial command signal bit corresponding to Rx3 is transmitted through Rx4, the signal data on the initial command signal bit corresponding to Rx4 is transmitted through Rx5, and the signal data on the initial command signal bit corresponding to Rx5 is transmitted through RRx.

If the line instruction transmission interface has no fault, the corresponding coded data is 1111, and the corresponding mapping relation is used for representing and keeping the initial mapping relation unchanged. If the line command transmission interface has no fault, the redundant interface RRx is idle. The remaining encoded data 0111 to 1110 is temporarily reserved, limited by the number of line command transmission interfaces. In order to avoid that the memory cannot identify or identify errors, the coded data 0111 to 1110 may have a corresponding remapping relationship, and the remapping relationship corresponding to the coded data 0111 to 1110 is used to represent that the initial mapping relationship is kept unchanged. Thus, even if the memory receives any of the data 0111 through 1110, the memory will not be unrecognized or recognized as another remapping relationship.

In one embodiment, the command transfer interface comprises a column command transfer interface. Referring to fig. 6b, cx0 to RCx denote column instruction transfer interfaces, and RCx denotes a redundant interface among the column instruction transfer interfaces. X in Cx0 through RCx represents the xth instruction channel. XX in fig. 6B indicates that the corresponding line instruction transmission interface is malfunctioning. If Cx0 fails, the corresponding remap code is 0000; if Cx1 fails, the corresponding remap code is 0001; if Cx2 fails, the corresponding remap code is 0010; if Cx3 fails, the corresponding remap code is 0011; if Cx4 fails, the corresponding remap code is 0100; if Cx5 fails, the corresponding remap code is 0101; if Cx6 fails, the corresponding remap code is 0110; if Cx7 fails, the corresponding remap code is 0111; if Cx8 fails, the corresponding remapping code is 1000.

It will be appreciated that with the increase in command transfer interfaces, the remaining encoded data may also be used as remapping encoding. With the increase of the instruction transmission interfaces, the coding length of the coded data can also be increased. Fig. 6A and 6B are only for illustration, and do not form a specific limitation on the value of the remap code corresponding to each instruction transfer interface, for example, the remap code corresponding to Rx0 may be set to 1110.

In the above embodiment, the remapping codes are coded data with a preset coding length, different instruction transmission interfaces correspond to different remapping codes, and the instruction transmission interfaces with faults can be effectively distinguished through the remapping codes. Furthermore, in each candidate encoding data corresponding to the preset encoding length, except for the remapping encoding corresponding to each instruction transmission interface, other encoding data are used for representing and keeping the initial mapping relation between the instruction transmission interface and the instruction signal bit unchanged, and other encoding data can avoid the memory from being unidentified or identified wrongly, thereby avoiding the memory from being repaired wrongly.

In one embodiment, the memory fault recovery method further comprises: and sending the remapping relation and the remapping code respectively corresponding to each instruction transmission interface to a memory so that the memory stores the remapping relation and the remapping code.

Generating a fault repairing instruction carrying target remapping information, and sending the fault repairing instruction to a memory, wherein the fault repairing instruction comprises the following steps: and generating a fault repairing instruction carrying a target remapping code corresponding to the current fault interface, sending the fault repairing instruction to a memory so that the memory acquires a target remapping relation corresponding to the target remapping code, and receiving a memory access instruction through a normal interface and a redundant interface based on the target remapping relation.

Specifically, after determining the remapping relationship and the remapping code corresponding to each instruction transmission interface, the computer device may send the remapping relationship and the remapping code corresponding to each instruction transmission interface to the memory, and the memory stores the remapping relationship and the remapping code corresponding to each instruction transmission interface. Therefore, when the subsequent memory receives the fault repairing instruction carrying the target remapping code corresponding to the current fault interface, the target remapping relation corresponding to the target remapping code can be rapidly obtained, and the memory access instruction is rapidly received through the normal interface and the redundant interface based on the target remapping relation.

In the above embodiment, the remapping relationship and the remapping code corresponding to each instruction transmission interface are sent to the memory, so that the memory stores the remapping relationship and the remapping code, and thus when the memory subsequently receives the remapping code corresponding to the failed interface, the failure repair can be quickly performed based on the remapping relationship, so as to correctly receive the failure repair instruction.

In one embodiment, as shown in fig. 7, generating a failure repair instruction carrying target remapping information, and sending the failure repair instruction to a memory includes:

step S702, generating the updating configuration information corresponding to the target register in the memory based on the target remapping information; the target register is used for indicating the receiving mode of the memory access instruction.

Step S704, generating a fault repairing instruction carrying the updated configuration information, and sending the fault repairing instruction to the memory, so that the memory updates the current configuration information corresponding to the target register based on the updated configuration information.

The memory may include a target register, where the target register is used to indicate a receiving mode of the memory for receiving the memory access instruction, that is, the target register is used to indicate a transmission mode and a transmission mode of the memory for transmitting signal data through the instruction transmission interface.

The current configuration information refers to current configuration information of the target register, and the updated configuration information refers to new configuration information of the target register and is used for updating the current configuration information.

Specifically, a target register for determining a reception manner of receiving the memory access instruction is provided in the memory, and the memory may determine the reception manner of receiving the memory access instruction based on configuration information of the target register. Accordingly, the target remapping information may be used to modify the configuration information of the target memory, so as to achieve the purpose of adjusting the receiving mode of receiving the memory access instruction. After the computer device obtains the target remapping information corresponding to the current failure interface, the computer device may generate the update configuration information corresponding to the target register based on the target remapping information. And then, the computer equipment generates a fault repairing instruction carrying the updated configuration information and sends the fault repairing instruction to the memory. After the memory receives the fault repairing instruction, the current configuration information corresponding to the target register can be updated based on the updated configuration information, so that when the memory receives the memory access instruction subsequently, the memory can know that the signal data on the corresponding instruction signal bit needs to be transmitted through the currently known normal interface and the currently known redundant interface based on the latest configuration information of the target register, and the memory access instruction can be correctly received.

In the above embodiment, the update configuration information corresponding to the target register in the memory is generated based on the target remapping information, the fault repairing instruction carrying the update configuration information is generated, and the fault repairing instruction is sent to the memory, so that the memory updates the current configuration information corresponding to the target register based on the update configuration information. In this way, once the current failed interface is determined, the configuration information of the target register in the memory is modified, so that the memory can determine how to correctly receive the memory access instruction based on the configuration information of the target register, and finally when the memory access instruction is received, the current failed interface can be successfully skipped to correctly receive the memory access instruction. The special target register is arranged to indicate the receiving mode of the memory for receiving the memory access instruction, so that the memory can be guaranteed to correctly receive the memory access instruction at any time and any place.

In one embodiment, the memory includes a row command transmission interface for transmitting signal data corresponding to row command signal bits, and a column command transmission interface for transmitting signal data corresponding to column command signal bits. The updated configuration information comprises target remapping information and interface type information corresponding to the current fault interface; the interface type information is used for indicating the memory to modify field information matched with the interface type corresponding to the current fault interface in the current configuration information based on the target remapping information; the configuration information of the target register comprises a first field used for determining the mapping relation corresponding to the row instruction transmission interface and a second field used for determining the mapping relation corresponding to the column instruction transmission interface.

Specifically, the memory comprises a row instruction transmission interface used for transmitting signal data corresponding to row instruction signal bits and a column instruction transmission interface used for transmitting signal data corresponding to column instruction signal bits. In order to effectively distinguish whether the current fault interface is a row instruction transmission interface or a column instruction transmission interface and ensure that the memory can correctly repair the fault instruction transmission interface, the updated configuration information can include interface type information corresponding to the current fault interface in addition to the target remapping information. The interface type information may identify the interface type corresponding to the currently failed interface.

Further, in order to effectively distinguish whether the current failed interface is a row instruction transmission interface or a column instruction transmission interface, and to ensure that the memory can correctly repair the failed instruction transmission interface, the configuration information of the target memory includes a first field for determining a mapping relationship corresponding to the row instruction transmission interface, and a second field for determining a mapping relationship corresponding to the column instruction transmission interface. And the interface type information in the updated configuration information is used for indicating the memory to modify the field information matched with the interface type corresponding to the current fault interface in the current configuration information based on the target remapping information. And if the current fault interface is a row instruction transmission interface, updating target remapping information in the configuration information to update the field information of the first field, and if the current fault interface is a column instruction transmission interface, updating the target remapping information in the configuration information to update the field information of the second field.

For example, the configuration information of the destination register is shown in table 1. Bits 36-39 of the configuration information are the first field for remapping the line instruction transport interface. Bits 32-35 of the configuration information are a second field used for remapping of the column instruction transport interface.

If the field information of the first field is h0, the current fault interface is a ROW instruction interface ROW0; if the field information of the first field is h1, the current fault interface is a ROW instruction interface ROW1; if the field information of the first field is h2, the current fault interface is a ROW instruction interface ROW2; if the field information of the first field is h3, the current fault interface is a ROW instruction interface ROW3; if the field information of the first field is h4, the current fault interface is a ROW instruction interface ROW4; if the field information of the first field is h5, the current fault interface is a ROW instruction interface ROW5; if the field information of the first field is h6, the current fault interface is a ROW instruction interface ROW6; and if the field information of the first field is hF, no fault interface exists currently. h7 to hE temporarily has no specific role, and if the row command interface is increased, h7 to hE can be utilized.

Correspondingly, if the field information of the second field is h0 to h8, the current fault interface is the column instruction interfaces COL0 to COL8; and if the field information of the second field is hF, no fault interface exists currently. h9 to hE temporarily has no specific role, and if the number of command interfaces is increased, h7 to hE can be utilized. Wherein h represents hexadecimal.

TABLE 1

For example, if Rx2 (i.e., ROW 2) is damaged, the configuration table corresponding to the updated configuration information is shown in table 2.

TABLE 2

Bit	Domain	Description of the invention
			71:40	Reserved (Reserved)	32’hFFFFFFFF
39:36	AWORD_ROW[3:0]	4’h2
			35:32	AWORD_COL[3:0]	4’hF
31:0	Reserved	32’hFFFFFFFF

If Cx8 (i.e., COL 8) is damaged, the configuration table corresponding to the updated configuration information is shown in table 3.

TABLE 3

Bit	Domain	Description of the preferred embodiment
			71:40	Reserved	32’hFFFFFFFF
39:36	AWORD_ROW[3:0]	4’hF
			35：32	AWORD_COL[3:0]	4’h8
31:0	Reserved	32’hFFFFFFFF

It will be appreciated that the updated configuration information may include all of the data in bits 0-71, and then the memory need only replace the current configuration information as a whole based on the updated configuration information. The updated configuration information may include only data on bits 32-35 or bits 36-39, and the memory may need to replace the field information of the second field or the first field in the current configuration information based on the updated configuration information.

In the above embodiment, the configuration information of the target register includes a first field for determining a mapping relationship corresponding to the row instruction transmission interface, and a second field for determining a mapping relationship corresponding to the column instruction transmission interface. The updated configuration information comprises target remapping information and interface type information corresponding to the current fault interface, and the interface type information is used for indicating the memory to modify field information matched with the interface type corresponding to the current fault interface in the current configuration information based on the target remapping information. In this way, the memory can quickly determine which instruction transmission interface fails based on the first field and the second field in the updated configuration information of the target register, and quickly perform targeted fault repair on the instruction transmission interface, so as to correctly receive the memory access instruction.

In one embodiment, generating a fault repairing instruction carrying updated configuration information, and sending the fault repairing instruction to a memory, so that the memory updates current configuration information corresponding to a target register based on the updated configuration information, includes:

acquiring a channel identifier corresponding to an instruction channel of a current fault interface in a memory; and generating a fault repairing instruction carrying the channel identifier and the updating configuration information, sending the fault repairing instruction to a memory so that the memory determines a target register matched with the instruction channel corresponding to the channel identifier, and updating the current configuration information corresponding to the target register based on the updating configuration information.

The memory may include at least one instruction channel, and different instruction channels are used to transmit memory access instructions for accessing different memory areas in the memory. The channel identifier is an identifier for uniquely identifying the instruction channel, and may specifically include a character string of at least one character of letters, numbers or symbols. Each instruction channel comprises a respective instruction transmission interface, and each instruction channel has a respective corresponding register.

Specifically, since at least one instruction channel exists in the memory, each instruction channel includes an instruction transmission interface, in order to ensure that the memory can correctly repair a failed instruction transmission interface, after the current failed interface is determined, the instruction channel to which the current failed interface belongs needs to be further determined. The computer device can obtain a channel identifier corresponding to an instruction channel of a current fault interface in the memory, generate a fault repairing instruction carrying the channel identifier and the updated configuration information, and send the fault repairing instruction to the memory. Each instruction channel in the memory has a corresponding register, and each register is used for indicating a receiving mode of the memory for receiving the memory access instruction corresponding to the corresponding instruction channel. After the memory receives the fault repairing instruction, the register matched with the instruction channel corresponding to the channel identifier carried by the fault repairing instruction is used as a target register from the register corresponding to each instruction channel, and the current configuration information corresponding to the target register is updated based on the updated configuration information, so that when the memory receives the memory access instruction corresponding to the channel identifier subsequently, the memory can know that the signal data on the corresponding instruction signal bit needs to be transmitted through the known normal interface and the known redundant interface in the corresponding instruction channel based on the latest configuration information of the target register, and the memory access instruction corresponding to the channel identifier can be received correctly.

In the above embodiment, a channel identifier corresponding to an instruction channel to which a current fault interface belongs in a memory is obtained; and generating a fault repairing instruction carrying the channel identifier and the updating configuration information, sending the fault repairing instruction to a memory so that the memory determines a target register matched with the instruction channel corresponding to the channel identifier, and updating the current configuration information corresponding to the target register based on the updating configuration information. Therefore, the memory can realize correct fault repair on the command transmission interface with the fault in the command channel with the fault based on the channel identification and the updated configuration information, so that the memory access command can be correctly received subsequently.

In one embodiment, generating a failure recovery instruction carrying a channel identifier and updating configuration information, and sending the failure recovery instruction to a memory includes:

generating target configuration information corresponding to a shared register in a memory based on the channel identifier, and generating a channel repairing instruction carrying the target configuration information; the target configuration information is used for updating current configuration information corresponding to the shared register, and the configuration information of the shared register is used for indicating the memory to carry out fault repair on the faulted instruction channel; generating an interface repair instruction carrying updated configuration information; obtaining a fault repairing instruction based on the channel repairing instruction and the interface repairing instruction; and sending the fault repairing instruction to the memory through a test interface provided by the memory.

The shared register refers to a register shared among instruction channels. In the memory, various registers have respective purposes, the shared register is used for indicating the memory to carry out fault repair on a faulted instruction channel, the dedicated register of the instruction channel is used for indicating the faulted instruction transmission interface in the instruction channel of the memory to carry out fault repair, and specific fault repair is carried out based on the remapping relation corresponding to the faulted instruction transmission interface.

The test interface is an interface provided by the memory for completing testing, boundary scanning and repairing of the memory.

Specifically, in order to ensure that the memory can correctly repair the failed instruction transmission interface, after the current failed interface and the instruction channel to which the current failed interface belongs are determined, the computer device may generate target configuration information corresponding to the shared register in the memory based on the channel identifier corresponding to the instruction channel to which the current failed interface belongs, and generate a channel repair instruction carrying the target configuration information. The channel repairing instruction is used for updating the current configuration information of the shared register based on the target configuration information so as to indicate that the memory needs to perform fault repairing on the instruction channel corresponding to the channel identifier currently. The computer device may generate an interface repair instruction carrying the update configuration information, where the interface repair instruction is used to update, based on the update configuration information, current configuration information of a target register corresponding to an instruction channel to which a current failed interface belongs, so as to instruct the memory how to perform fault repair on a currently failed instruction transmission interface in the instruction channel. The computer equipment can obtain a fault repairing instruction based on the channel repairing instruction and the interface repairing instruction, the channel repairing instruction and the interface repairing instruction form the fault repairing instruction, and finally the fault repairing instruction is sent to the memory through a testing interface provided by the memory. After the memory receives the fault repairing instruction, the memory may update the current configuration information of the shared register based on the target configuration information to determine an instruction channel that needs to be subjected to fault repairing currently, start fault repairing for the instruction channel, update the current configuration information of the target register corresponding to the instruction channel to which the current fault interface belongs based on the updated configuration information to determine an instruction transmission interface that needs to be subjected to fault repairing currently, and start fault repairing for the instruction transmission interface.

In one embodiment, the test interface provided by the memory is an IEEE1500 interface based on IEEE1500 (also referred to as IEEE Std 1500) test standard, the shared Register is a test shell instruction Register (WIR) based on IEEE1500 test standard, and the Register specific to the instruction channel is a test shell data Register (WDR) based on IEEE Std 1500 test standard. The channel repair instruction may be referred to as a WIR instruction, and is used to modify the configuration information of the WIR register, and part of the configuration contents of the WIR instruction are shown in table 4. WIR [ 11. WIR [7:0] represents bits 0 through 7 in an instruction, and the data on bits 0 through 7 is used to represent the effect of the WIR instruction. When WIR [7:0] is 12h, it indicates that the WIR instruction is used for soft repair. Soft repair is a software repair approach.

The interface repair instruction may be referred to as a WDR instruction, which modifies the configuration information of the WDR register, the configuration contents of the WDR instruction being as shown in Table 1.

TABLE 4

In the above embodiment, the fault repairing instruction includes a channel repairing instruction carrying target configuration information corresponding to the shared register and an interface repairing instruction carrying updated configuration information corresponding to the target register, the memory may modify the configuration information of the shared register based on the channel repairing instruction to start fault repairing on a corresponding instruction channel, and determine that the target register configured needs to be modified based on the updated configuration information, and the memory may modify the configuration information of the corresponding target register based on the interface repairing instruction to start fault repairing on a corresponding instruction transmission interface. The fault repairing instruction can be rapidly sent to the memory through the testing interface provided by the memory, and fault repairing can be rapidly started.

In one embodiment, the target remapping information is automatically cleared after the memory is powered down, and the memory fault repairing method further comprises:

and after the memory is restarted, re-determining the current fault interface in the memory, and executing the step of acquiring the target remapping information corresponding to the current fault interface in the memory.

In particular, the transmission of the memory access command is easily affected by the environment change of PVT (process voltage Temperature) and the crosstalk between signals, which causes the command transmission interface to malfunction or damage during the operation of the memory. The failure of the command transmission interface is usually a soft failure, and if the memory is restarted after power failure, the environment in which the command transmission interface fails is obviously changed, for example, the temperature changes after the memory is restarted, and then the command transmission interface is likely to have no failure. Thus, the target remapping information may be automatically cleared after power is lost to the memory. After the memory is restarted, the command transmission interface which has failed may not exist or be changed, and in order to ensure the accuracy of the fault repair, the computer device needs to execute the memory fault repair method again. After the memory is restarted, the computer device needs to re-determine the current faulty interface in the memory, further acquire target remapping information corresponding to the current faulty interface in the memory, generate a fault repairing instruction carrying the target remapping information, and send the fault repairing instruction to the memory, so that the memory receives a memory access instruction through the current normal interface and the redundant interface based on the target remapping information.

In the above embodiment, the target remapping information is lost after the power failure of the memory, and after the memory is restarted, the current failed interface in the memory is redetermined to perform the fault repair, so as to ensure the accuracy of the fault repair.

In one embodiment, the memory fault recovery method further comprises:

acquiring the number of redundant interfaces of a redundant interface in a memory and the number of fault interfaces of a current fault interface; when the number of the fault interfaces is less than or equal to the number of the redundant interfaces, the step of obtaining the target remapping information corresponding to the current fault interface in the memory is carried out; and when the number of the fault interfaces is larger than that of the redundant interfaces, generating fault prompt information.

In particular, to maintain the manufacturing cost of the memory and guarantee the utilization of the instruction transmission interface, the number of redundant interfaces in the memory may be limited. Therefore, under the condition that the number of the redundant interfaces in the memory is greater than or equal to the number of the fault interfaces of the current fault interfaces, the computer device can acquire the target remapping information corresponding to each current fault interface in the memory, generate a fault repairing instruction carrying each target remapping information, and send the fault repairing instruction to the memory to rapidly repair the fault. Under the condition that the number of the redundant interfaces in the memory is less than the number of the fault interfaces of the current fault interfaces, the computer equipment can generate fault prompt information to prompt that the memory has serious faults at present and carry out fault repair in other modes. The computer device can display the fault prompt information locally, and can also send the fault prompt information to a preset terminal, for example, a terminal held by an operation and maintenance person, so as to quickly notify the relevant person.

In the above embodiment, if the number of the failed interfaces is less than or equal to the number of the redundant interfaces, the failure repair is automatically performed based on the target remapping information corresponding to the current failed interface, so as to achieve the rapid repair, and if the number of the failed interfaces is greater than the number of the redundant interfaces, the failure prompt information is generated to prompt that other methods are adopted for performing the failure repair, so as to achieve the correct repair.

In one embodiment, as shown in fig. 8, a method for repairing a memory failure is provided, which is described by taking a memory as an example, and includes the following steps:

step S802, acquiring a fault repairing instruction; the fault repairing instruction carries target remapping information corresponding to a current fault interface in the memory, the target remapping information is obtained by reallocating mapping relations between each instruction signal bit corresponding to the memory access instruction and the instruction transmission interfaces in the normal interface and the redundant interface based on the position relation between the current fault interface and other instruction transmission interfaces, and the instruction transmission interfaces are used for transmitting signal data corresponding to corresponding instruction signal bits in the memory access instruction.

Step S804, receiving a memory access command through the normal interface and the redundant interface based on the target remapping information.

Specifically, the memory may receive a fault repair instruction sent from the outside, perform fault repair based on target remapping information in the fault repair instruction, skip a current fault interface, and correctly receive a memory access instruction through the normal interface and the redundant interface.

It can be understood that the contents of the foregoing embodiments may be referred to in the specific processes of generating the target remapping information, generating the fault repairing instruction, and the like, and are not described herein again.

According to the memory fault repairing method, if the command transmission interface in the memory has a fault, the mapping relation between each command signal bit corresponding to the memory access command and the command transmission interface is redistributed in the normal interface and the redundant interface, so that the memory can skip the current fault interface when receiving the memory access command, and the signal data corresponding to each command signal bit in the memory access command is received through the normal interface and the redundant interface, so that the memory can correctly receive the memory access command. And when the mapping relation is redistributed, the mapping relation between the normal interface and the redundant interface and the command signal bit is redistributed based on the position relation between the current fault interface and other command transmission interfaces, so that the memory can intelligently skip the current fault interface when receiving the memory access command, and orderly receive the signal data corresponding to each command signal bit in the memory access command through the normal interface and the redundant interface, thereby the memory can quickly and accurately receive the memory access command. And sending the fault repairing instruction carrying the target remapping information corresponding to the current fault interface and determined by the mapping relation between the redistribution instruction signal bit and the instruction transmission interface to the memory, wherein the memory can quickly repair the fault, so that the memory access instruction is quickly and accurately received.

In a specific embodiment, the Memory fault repairing method of the present application may be applied to repair a fault in a transmission channel of an atomic WORD (ADDRESS WORD) of a High Bandwidth Memory (HBM) DRAM.

In a chip using HBM, metal interconnects are typically used to connect the various modules. With the development of modern technologies, the line width between interconnection wires is becoming narrower and narrower, and the influence of coupling effect and interference noise between wires is increasing. Meanwhile, because the HBM supports data reading, writing and storage with very high bandwidth, the heat dissipation problem of the HBM chip has higher challenge. Since the AWORD of the HBM can operate at a clock frequency of 1.8GHz at most, the transmission of the AWORD is easily affected by the change of the PVT environment, and the influence of crosstalk between signals causes the transmission channel of the AWORD to malfunction or be damaged during the operation of the HBM, for example, referring to fig. 9, when there is a drift in the temperature of the HBM chip, the delay inside the HBM PHY (High Bandwidth Memory Physical layer) may change at the same time, and such a change may change the value of the delay, thereby affecting the original alignment relationship between the clock and the data. When a failure occurs in the channel of the AWORD during operation, if the failure is not repaired, an error may occur in the operation of the Host on the HBM DRAM, and in a serious case, the loss of the storage data of the HBM DRAM may be caused. The memory fault repairing method can carry out soft repairing on the AWORD channel, ensures that HBM AWORD can carry out repairing processing quickly when certain channels have operation faults, and ensures the correctness of sending the HBM instruction words.

The HBM AWORD is responsible for completing the function of sending instructions to the HBM DRAM, and the correctness of each operation of the HBM can be ensured only by the accurate sending of the HBM AWORD. The instructions of HBM AWORD fall into two broad categories: a row instruction and a column instruction. The HBM2 protocol supports a column instruction of 8 bits, namely C7:0, and a row instruction of 6 bits, namely R5:0. The HBM2E protocol supports a column instruction of 9 bits, namely C [8:0], and a row instruction of 7 bits, namely R [6:0]. The memory fault repairing method supports compatible versions of HBM2 and HBM2E protocols, and supports both HBM2 protocol and HBM2E protocol.

The interior of the HBM contains a total of 8 sets of channels. HBM DRAM provides a redundant interface for remapping AWORD. As shown in table 5, the AWORD of HBM DRAM for a single channel and its redundant interface.

TABLE 5

As can be seen from table 5, in the atomic word of HBM, a row instruction word (i.e., a row instruction signal bit) and a column instruction word (i.e., a column instruction signal bit) can be remapped independently, the row instruction word can be mapped to the RR pin, and the column instruction word can be mapped to the RC pin.

As shown in fig. 10, fig. 10 is a schematic flow chart of soft repair for the AWORD channel of the HBM DRAM. Firstly, the computer equipment determines a current failure interface, reads the current configuration information of a WDR register corresponding to the current failure interface in the HBM DRAM through the host, and records the current configuration information of the WDR register. Then, the computer device configures the updated configuration information of the WDR register through the host, specifically, configures the register code (i.e., remap code) corresponding to the currently failed interface when configuring the updated configuration information, for example, the register code corresponding to the currently failed interface may be queried from the tables shown in fig. 6A and 6B. The computer device generates a soft repair remap table of the WDR register according to the update configuration information by the host, where the information of the soft repair remap table may refer to table 1. The computer equipment sends an IEEE1500 instruction to the HBM DRAM through the host, and sends the soft repair remapping table to the HBM DRAM through the IEEE1500 instruction so as to update the configuration information of the WDR register corresponding to the current failure interface. And the computer equipment judges whether the IEEE1500 instruction is sent to the end or not, and if the IEEE1500 instruction is sent to the end, the soft repair aiming at the current fault interface is ended.

The host and the HBM agree in advance on the remapping relation corresponding to each register code. When the HBM DRAM receives a memory access instruction, the corresponding remapping relation is determined based on the latest configuration information of the WDR register, a current fault interface is skipped based on the remapping relation, signal data on a corresponding instruction signal bit in the memory access instruction are transmitted through the normal interface and the redundant interface, and the signal data transmitted by the normal interface and the redundant interface are sequentially read, so that a complete memory access instruction can be obtained. And the remapping relation is obtained by reallocating the mapping relation between each instruction signal bit corresponding to the memory access instruction and the instruction transmission interface in the normal interface and the redundant interface based on the position relation between the current fault interface and other instruction transmission interfaces. For example, referring to fig. 6A, the fault exists on the interface Rx0, the redundant interface RRx is used to repair the fault, and after the repair, the Rx6, rx1, rx2, rx3, rx4, rx5, and RRx interfaces respectively transmit data on bits R6, R0, R1, R2, R3, R4, and R5 in the memory access command sent to the x command channel.

It should be understood that, although the steps in the flowcharts related to the embodiments described above are shown in sequence as indicated by the arrows, the steps are not necessarily performed in sequence as indicated by the arrows. The steps are not performed in the exact order shown and described, and may be performed in other orders, unless explicitly stated otherwise. Moreover, at least a part of the steps in the flowcharts related to the embodiments described above may include multiple steps or multiple stages, which are not necessarily performed at the same time, but may be performed at different times, and the execution order of the steps or stages is not necessarily sequential, but may be rotated or alternated with other steps or at least a part of the steps or stages in other steps.

Based on the same inventive concept, the embodiment of the present application further provides a memory fault repairing apparatus for implementing the above-mentioned memory fault repairing method. The implementation scheme for solving the problem provided by the apparatus is similar to the implementation scheme described in the above method, so specific limitations in one or more embodiments of the memory failure recovery apparatus provided below can be referred to the limitations of the above memory failure recovery method, and are not described herein again.

In one embodiment, as shown in FIG. 11, there is provided a memory fail repair apparatus 1100, comprising: a remapping information obtaining module 1102 and a failure repair instruction sending module 1104, wherein:

a remapping information obtaining module 1102, configured to obtain target remapping information corresponding to a current faulty interface in a memory; the target remapping information is obtained by reallocating mapping relations between each instruction signal bit corresponding to the memory access instruction and the instruction transmission interfaces in the normal interface and the redundant interface based on the position relation between the current fault interface and other instruction transmission interfaces, and the instruction transmission interfaces are used for transmitting signal data corresponding to corresponding instruction signal bits in the memory access instruction.

And a failure repair instruction sending module 1104, configured to generate a failure repair instruction carrying the target remapping information, and send the failure repair instruction to the memory, so that the memory receives a memory access instruction through the normal interface and the redundant interface based on the target remapping information.

According to the memory fault repairing device, if the command transmission interface in the memory fails, the mapping relation between each command signal bit corresponding to the memory access command and the command transmission interface is redistributed in the normal interface and the redundant interface, so that the memory can skip the current fault interface when receiving the memory access command, and the signal data corresponding to each command signal bit in the memory access command is received through the normal interface and the redundant interface, so that the memory can correctly receive the memory access command. And when the mapping relation is redistributed, the mapping relation between the normal interface and the redundant interface and the command signal bit is redistributed based on the position relation between the current fault interface and other command transmission interfaces, so that the memory can intelligently skip the current fault interface when receiving the memory access command, and orderly receive the signal data corresponding to each command signal bit in the memory access command through the normal interface and the redundant interface, so that the memory can quickly and accurately receive the memory access command. And sending the fault repairing instruction carrying the target remapping information corresponding to the current fault interface and determined by the mapping relation between the redistribution instruction signal bit and the instruction transmission interface to the memory, wherein the memory can quickly repair the fault, so that the memory access instruction is quickly and accurately received.

In one embodiment, the memory failure repair apparatus further includes:

the remapping information generating module is used for acquiring interface position sequencing information; determining candidate fault interfaces from each instruction transmission interface; generating remapping information corresponding to the candidate fault interface based on the interface position sorting information and the interface position corresponding to the candidate fault interface; the remapping information is used for indicating and keeping the initial mapping relation between the forward interface of the candidate fault interface and the initial instruction signal bit unchanged, and establishing the mapping relation between the initial instruction signal bit corresponding to the candidate fault interface and the backward interface of the candidate fault interface and the respective corresponding adjacent backward non-fault interface; and taking the next instruction transmission interface as a candidate fault interface, returning to the interface position corresponding to the candidate fault interface based on the interface position sorting information and the candidate fault interface, and executing the step of generating the remapping information corresponding to the candidate fault interface until the remapping information corresponding to each instruction transmission interface is obtained.

In one embodiment, the remapping information generating module is further configured to determine a remapping relationship corresponding to the candidate failed interface based on the interface position sorting information and the interface position corresponding to the candidate failed interface; the remapping relation comprises a redetermined mapping relation between other instruction transmission interfaces and instruction signal bits under the condition that the candidate fault interface fails; and generating a remapping code corresponding to the remapping relation, and obtaining remapping information corresponding to the candidate fault interface based on the remapping code.

In one embodiment, the remapping codes are coded data with preset coding length, and different instruction transmission interfaces correspond to different remapping codes; in each candidate encoding data corresponding to the preset encoding length, except for the remapping encoding corresponding to each instruction transmission interface, other encoding data are used for representing and keeping the initial mapping relation between the instruction transmission interface and the initial instruction signal bit unchanged.

In an embodiment, the remapping information generating module is further configured to send the remapping relationship and the remapping code respectively corresponding to each instruction transmission interface to the memory, so that the memory stores the remapping relationship and the remapping code. The fault repairing instruction sending module is further used for generating a fault repairing instruction carrying the target remapping codes corresponding to the current fault interface, sending the fault repairing instruction to the memory so that the memory can obtain the target remapping relation corresponding to the target remapping codes, and receiving the memory access instruction through the normal interface and the redundant interface based on the target remapping relation.

In one embodiment, the failure repair instruction sending module is further configured to generate update configuration information corresponding to the target register in the memory based on the target remapping information; the target register is used for indicating a receiving mode of the memory for receiving the memory access instruction; and generating a fault repairing instruction carrying the updated configuration information, and sending the fault repairing instruction to the memory so that the memory updates the current configuration information corresponding to the target register based on the updated configuration information.

In one embodiment, the memory includes a row command transfer interface for transferring signal data corresponding to row command signal bits, and a column command transfer interface for transferring signal data corresponding to column command signal bits. The updating configuration information comprises target remapping information and interface type information corresponding to the current fault interface; the interface type information is used for indicating the memory to modify field information matched with the interface type corresponding to the current fault interface in the current configuration information based on the target remapping information; the configuration information of the target register comprises a first field used for determining the mapping relation corresponding to the row instruction transmission interface and a second field used for determining the mapping relation corresponding to the column instruction transmission interface.

In one embodiment, the fault repairing instruction sending module is further configured to obtain a channel identifier corresponding to an instruction channel to which a current fault interface belongs in the memory; and generating a fault repairing instruction carrying the channel identifier and the updating configuration information, sending the fault repairing instruction to a memory so that the memory determines a target register matched with the instruction channel corresponding to the channel identifier, and updating the current configuration information corresponding to the target register based on the updating configuration information.

In one embodiment, the fault repairing instruction sending module is further configured to generate target configuration information corresponding to a shared register in the memory based on the channel identifier, and generate a channel repairing instruction carrying the target configuration information; the target configuration information is used for updating current configuration information corresponding to the shared register, and the configuration information of the shared register is used for indicating the memory to carry out fault repair on the faulted instruction channel; generating an interface repair instruction carrying updated configuration information; obtaining a fault repairing instruction based on the channel repairing instruction and the interface repairing instruction; and sending the fault repairing instruction to the memory through a test interface provided by the memory.

In one embodiment, the target remapping information is automatically cleared after power is lost to the memory. The memory fault repair device is further configured to:

after the memory is restarted, the current fault interface in the memory is redetermined, and the step of obtaining the target remapping information corresponding to the current fault interface in the memory is carried out.

In one embodiment, as shown in fig. 12, there is provided a memory fail-over apparatus including: a failover instruction acquisition module 1202 and a memory access instruction receiving module 1204, wherein:

a failure recovery instruction obtaining module 1202, configured to obtain a failure recovery instruction; the fault repairing instruction carries target remapping information corresponding to a current fault interface in a memory; the target remapping information is obtained by reallocating mapping relations between each instruction signal bit corresponding to the memory access instruction and the instruction transmission interfaces in the normal interface and the redundant interface based on the position relation between the current fault interface and other instruction transmission interfaces, and the instruction transmission interfaces are used for transmitting signal data corresponding to corresponding instruction signal bits in the memory access instruction.

A memory access instruction receiving module 1204, configured to receive a memory access instruction through the normal interface and the redundant interface based on the target remapping information.

According to the memory fault repairing device, if the command transmission interface in the memory fails, the mapping relation between each command signal bit corresponding to the memory access command and the command transmission interface is redistributed in the normal interface and the redundant interface, so that the memory can skip the current fault interface when receiving the memory access command, and the signal data corresponding to each command signal bit in the memory access command is received through the normal interface and the redundant interface, so that the memory can correctly receive the memory access command. And when the mapping relation is redistributed, the mapping relation between the normal interface and the redundant interface and the command signal bit is redistributed based on the position relation between the current fault interface and other command transmission interfaces, so that the memory can intelligently skip the current fault interface when receiving the memory access command, and orderly receive the signal data corresponding to each command signal bit in the memory access command through the normal interface and the redundant interface, so that the memory can quickly and accurately receive the memory access command. And sending a fault repairing instruction carrying target remapping information which corresponds to the current fault interface and is determined by the mapping relation between the redistribution instruction signal bit and the instruction transmission interface to the memory, wherein the memory can quickly repair the fault, and thus, the memory access instruction is quickly and accurately received.

The respective modules in the above memory failure recovery apparatus may be wholly or partially implemented by software, hardware, and a combination thereof. The modules can be embedded in a hardware form or independent from a processor in the computer device, and can also be stored in a memory in the computer device in a software form, so that the processor can call and execute operations corresponding to the modules.

In one embodiment, a computer device is provided, which may be a server, and its internal structure diagram may be as shown in fig. 13. The computer device includes a processor, a memory, an Input/Output interface (I/O for short), and a communication interface. The processor, the memory and the input/output interface are connected through a system bus, and the communication interface is connected to the system bus through the input/output interface. Wherein the processor of the computer device is configured to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system, a computer program, and a database. The internal memory provides an environment for the operation of an operating system and computer programs in the non-volatile storage medium. The database of the computer device is used for storing data such as remapping information, remapping codes and the like. The input/output interface of the computer device is used for exchanging information between the processor and an external device. The communication interface of the computer device is used for connecting and communicating with an external terminal through a network. The computer program is executed by a processor to implement a memory fail-over method.

In one embodiment, a computer device is provided, which may be a terminal, and its internal structure diagram may be as shown in fig. 14. The computer apparatus includes a processor, a memory, an input/output interface, a communication interface, a display unit, and an input device. The processor, the memory and the input/output interface are connected through a system bus, and the communication interface, the display unit and the input device are connected to the system bus through the input/output interface. Wherein the processor of the computer device is configured to provide computing and control capabilities. The memory of the computer device comprises a nonvolatile storage medium and an internal memory. The non-volatile storage medium stores an operating system and a computer program. The internal memory provides an environment for the operation of an operating system and computer programs in the non-volatile storage medium. The input/output interface of the computer device is used for exchanging information between the processor and an external device. The communication interface of the computer device is used for carrying out wired or wireless communication with an external terminal, and the wireless communication can be realized through WIFI, a mobile cellular network, NFC (near field communication) or other technologies. The computer program is executed by a processor to implement a memory fail-over method. The display unit of the computer equipment is used for forming a visual and visible picture, and can be a display screen, a projection device or a virtual reality imaging device, the display screen can be a liquid crystal display screen or an electronic ink display screen, the input device of the computer equipment can be a touch layer covered on the display screen, a key, a track ball or a touch pad arranged on the shell of the computer equipment, and can also be an external keyboard, a touch pad or a mouse and the like.

It will be appreciated by those skilled in the art that the configurations shown in fig. 13 and 14 are block diagrams of only some of the configurations relevant to the present application, and do not constitute a limitation on the computing devices to which the present application may be applied, and that a particular computing device may include more or fewer components than shown in the figures, or may combine certain components, or have a different arrangement of components.

In one embodiment, a computer device is further provided, which includes a memory and a processor, the memory stores a computer program, and the processor implements the steps of the above method embodiments when executing the computer program.

In an embodiment, a computer-readable storage medium is provided, in which a computer program is stored which, when being executed by a processor, carries out the steps of the above-mentioned method embodiments.

In one embodiment, a computer program product or computer program is provided that includes computer instructions stored in a computer readable storage medium. The computer instructions are read by a processor of a computer device from a computer-readable storage medium, and the computer instructions are executed by the processor to cause the computer device to perform the steps in the above-mentioned method embodiments.

It should be noted that, the user information (including but not limited to user equipment information, user personal information, etc.) and data (including but not limited to data for analysis, stored data, displayed data, etc.) referred to in the present application are information and data authorized by the user or sufficiently authorized by each party, and the collection, use and processing of the related data need to comply with the relevant laws and regulations and standards of the relevant country and region.

It will be understood by those skilled in the art that all or part of the processes of the methods of the embodiments described above can be implemented by hardware instructions of a computer program, which can be stored in a non-volatile computer-readable storage medium, and when executed, can include the processes of the embodiments of the methods described above. Any reference to memory, database, or other medium used in the embodiments provided herein may include at least one of non-volatile and volatile memory. The nonvolatile Memory may include a Read-Only Memory (ROM), a magnetic tape, a floppy disk, a flash Memory, an optical Memory, a high-density embedded nonvolatile Memory, a resistive Random Access Memory (ReRAM), a Magnetic Random Access Memory (MRAM), a Ferroelectric Random Access Memory (FRAM), a Phase Change Memory (PCM), a graphene Memory, and the like. Volatile Memory can include Random Access Memory (RAM), external cache Memory, and the like. By way of illustration and not limitation, RAM can take many forms, such as Static Random Access Memory (SRAM) or Dynamic Random Access Memory (DRAM), among others. The databases involved in the embodiments provided herein may include at least one of relational and non-relational databases. The non-relational database may include, but is not limited to, a block chain based distributed database, and the like. The processors referred to in the embodiments provided herein may be general purpose processors, central processing units, graphics processors, digital signal processors, programmable logic devices, quantum computing based data processing logic devices, etc., without limitation.

The technical features of the above embodiments can be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the above embodiments are not described, but should be considered as the scope of the present specification as long as there is no contradiction between the combinations of the technical features.

The above-mentioned embodiments only express several embodiments of the present application, and the description thereof is more specific and detailed, but not construed as limiting the scope of the present application. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the concept of the present application, which falls within the scope of protection of the present application. Therefore, the protection scope of the present application should be subject to the appended claims.

Claims

1. A method of memory fault recovery, the method comprising:

2. The method of claim 1, further comprising:

acquiring interface position sequencing information;

determining candidate fault interfaces from each instruction transmission interface;

generating remapping information corresponding to the candidate fault interface based on the interface position sorting information and the interface position corresponding to the candidate fault interface; the remapping information is used for indicating and keeping the initial mapping relation between the forward interface of the candidate fault interface and the initial instruction signal bit unchanged, and establishing the mapping relation between the initial instruction signal bit corresponding to the candidate fault interface and the backward interface of the candidate fault interface and the adjacent backward non-fault interface corresponding to each initial instruction signal bit;

and taking the next instruction transmission interface as a candidate fault interface, returning to the interface position based on the interface position sorting information and the candidate fault interface, and executing the step of generating the remapping information corresponding to the candidate fault interface until the remapping information corresponding to each instruction transmission interface is obtained.

3. The method according to claim 2, wherein the generating remapping information corresponding to the candidate failing interface based on the interface position ordering information and the interface position corresponding to the candidate failing interface comprises:

determining a remapping relation corresponding to the candidate fault interface based on the interface position sequencing information and the interface position corresponding to the candidate fault interface; the remapping relation comprises a redetermined mapping relation between other instruction transmission interfaces and instruction signal bits under the condition that the candidate fault interface has a fault;

and generating a remapping code corresponding to the remapping relation, and obtaining remapping information corresponding to the candidate fault interface based on the remapping code.

4. The method of claim 3, wherein the remapping coding is coding data with a preset coding length, and different command transmission interfaces correspond to different remapping codings; in each candidate encoding data corresponding to the preset encoding length, except for the remapping encoding corresponding to each instruction transmission interface, other encoding data are used for representing and keeping the initial mapping relation between the instruction transmission interface and the initial instruction signal bit unchanged.

5. The method of claim 3, further comprising:

sending the remapping relation and the remapping code respectively corresponding to each instruction transmission interface to the memory so that the memory stores the remapping relation and the remapping code;

the generating a fault repairing instruction carrying the target remapping information and sending the fault repairing instruction to the memory includes:

and generating a fault repairing instruction carrying a target remapping code corresponding to the current fault interface, sending the fault repairing instruction to the memory so that the memory acquires a target remapping relation corresponding to the target remapping code, and receiving a memory access instruction through the normal interface and the redundant interface based on the target remapping relation.

6. The method according to any one of claims 1 to 5, wherein the generating a failover instruction carrying the target remapping information, and sending the failover instruction to the memory, comprises:

generating updating configuration information corresponding to a target register in the memory based on the target remapping information; the target register is used for indicating a receiving mode of the memory for receiving the memory access instruction;

and generating a fault repairing instruction carrying the updated configuration information, and sending the fault repairing instruction to the memory so that the memory updates the current configuration information corresponding to the target register based on the updated configuration information.

7. The method of claim 6, wherein the memory includes a row command transmission interface for transmitting signal data corresponding to row command signal bits, a column command transmission interface for transmitting signal data corresponding to column command signal bits;

the updating configuration information comprises the target remapping information and the interface type information corresponding to the current fault interface; the interface type information is used for indicating the memory to modify field information matched with the interface type corresponding to the current fault interface in the current configuration information based on the target remapping information; the configuration information of the target register comprises a first field used for determining the mapping relation corresponding to the row instruction transmission interface and a second field used for determining the mapping relation corresponding to the column instruction transmission interface.

8. The method according to claim 6, wherein the generating a fault repairing instruction that carries the updated configuration information, and sending the fault repairing instruction to the memory, so that the memory updates the current configuration information corresponding to the target register based on the updated configuration information includes:

acquiring a channel identifier corresponding to the instruction channel of the current fault interface in the memory;

and generating a fault repairing instruction carrying the channel identifier and the updated configuration information, and sending the fault repairing instruction to the memory so that the memory determines a target register matched with the instruction channel corresponding to the channel identifier, and updating the current configuration information corresponding to the target register based on the updated configuration information.

9. The method according to claim 8, wherein the generating a failure recovery instruction carrying the channel identifier and the update configuration information, and sending the failure recovery instruction to the memory includes:

generating target configuration information corresponding to a shared register in the memory based on the channel identifier, and generating a channel repairing instruction carrying the target configuration information; the target configuration information is used for updating current configuration information corresponding to the shared register, and the configuration information of the shared register is used for indicating the memory to carry out fault repair on a faulted instruction channel;

generating an interface repair instruction carrying the update configuration information;

obtaining the fault repairing instruction based on the channel repairing instruction and the interface repairing instruction;

and sending the fault repairing instruction to the memory through a test interface provided by the memory.

10. The method of claim 1, wherein the target remapping information is automatically cleared after the power down of the memory, the method further comprising:

11. A method of memory fault recovery, the method comprising:

12. A memory fault repair apparatus, the apparatus comprising:

13. A memory fault repair apparatus, the apparatus comprising:

14. A computer device comprising a memory and a processor, the memory storing a computer program, characterized in that the processor realizes the steps of the method of any one of claims 1 to 11 when executing the computer program.

15. A computer-readable storage medium, on which a computer program is stored which, when being executed by a processor, carries out the steps of the method according to any one of claims 1 to 11.

16. A computer program product comprising a computer program, characterized in that the computer program realizes the steps of the method of any one of claims 1 to 11 when executed by a processor.