CN115114062B

CN115114062B - Fault detection method, device, equipment and storage medium for instruction word line

Info

Publication number: CN115114062B
Application number: CN202210449197.1A
Authority: CN
Inventors: 强鹏
Original assignee: Tencent Technology Shenzhen Co Ltd
Current assignee: Tencent Technology Shenzhen Co Ltd
Priority date: 2022-04-27
Filing date: 2022-04-27
Publication date: 2024-04-30
Anticipated expiration: 2042-04-27
Also published as: CN115114062A

Abstract

The application relates to a fault detection method, device, equipment and storage medium for an instruction word line. The method can be applied to cloud technology and application scenes of the vehicle-mounted terminal, and comprises the following steps: transmitting an instruction word sequence to a target memory through an instruction word line, so that the target memory carries out instruction processing on the instruction word sequence based on an instruction processing circuit to obtain a first target instruction word sequence; reading a first target instruction word sequence in the target memory through a target data interface; performing instruction processing on the instruction word sequence based on a target algorithm to obtain a second target instruction word sequence; and detecting line faults of the instruction word line in the process of transmitting the instruction word based on the first target instruction word sequence and the second target instruction word sequence. The method can improve the detection capability of the fault of the transmission line.

Description

Fault detection method, device, equipment and storage medium for instruction word line

Technical Field

The present application relates to the field of computer technologies, and in particular, to a fault detection method, apparatus, device, and storage medium for an instruction word line.

Background

The high-bandwidth memory (High Bandwidth Memory, HBM) is a novel high-speed high-bandwidth memory, and is mainly applied to the field of artificial intelligent chips. Under the clock frequency that the control command of the HBM can work at most and 1.8GHz, the transmission line of the control command is easily affected by chip technology, working voltage, ambient temperature and signal crosstalk to cause errors in the transmitted control command, so that when the control command is transmitted, fault detection is needed for each transmission line of the control command.

The conventional fault detection mainly performs parity check by transmitting the check information of PAR (PARITY CHECK ), however, the parity check can only be used for determining whether a faulty transmission line exists in each transmission line, but cannot determine which transmission line is faulty, resulting in poor capability of detecting the fault of the transmission line.

Disclosure of Invention

In view of the foregoing, it is desirable to provide a fault detection method, apparatus, device, and storage medium for an instruction word line that can improve the capability of detecting a transmission line fault.

In a first aspect, the present application provides a fault detection method for an instruction word line. The method comprises the following steps:

transmitting an instruction word sequence to a target memory through an instruction word line, so that the target memory carries out instruction processing on the instruction word sequence based on an instruction processing circuit to obtain a first target instruction word sequence;

reading a first target instruction word sequence in the target memory through a target data interface;

Performing instruction processing on the instruction word sequence based on a target algorithm to obtain a second target instruction word sequence;

and detecting line faults of the instruction word line in the process of transmitting the instruction word based on the first target instruction word sequence and the second target instruction word sequence.

In a second aspect, the application further provides a fault detection device of the command word line. The device comprises:

The instruction sending module is used for sending an instruction word sequence to the target memory through an instruction word line so that the target memory can process the instruction word sequence based on the instruction processing circuit to obtain a first target instruction word sequence;

the data reading module is used for reading a first target instruction word sequence in the target memory through a target data interface;

the instruction processing module is used for carrying out instruction processing on the instruction word sequence based on a target algorithm to obtain a second target instruction word sequence;

the fault detection module is used for detecting line faults of the instruction word line in the process of transmitting the instruction word based on the first target instruction word sequence and the second target instruction word sequence.

In a third aspect, the present application also provides a computer device. The computer device comprises a memory storing a computer program and a processor which when executing the computer program performs the steps of:

In a fourth aspect, the present application also provides a computer-readable storage medium. The computer readable storage medium having stored thereon a computer program which when executed by a processor performs the steps of:

In a fifth aspect, the present application also provides a computer program product. The computer program product comprises a computer program which, when executed by a processor, implements the steps of:

The fault detection method, the fault detection device, the fault detection equipment and the fault detection storage medium of the instruction word line send the instruction word sequence to the target memory through the instruction word line so that the target memory carries out instruction processing on the instruction word sequence based on the instruction processing circuit to obtain a first target instruction word sequence; reading a first target instruction word sequence in a target memory through a target data interface; performing instruction processing on the instruction word sequence based on a target algorithm to obtain a second target instruction word sequence; based on the first target instruction word sequence and the second target instruction word sequence, line faults of the instruction word lines in the process of transmitting the instruction words are detected, so that the specific faulty instruction word line and the faulty target instruction word in the instruction word sequence can be determined when the transmission line breaks down, and the detection capability of the transmission line faults is improved.

Drawings

FIG. 1 is an application environment diagram of a fault detection method for an instruction word line in one embodiment;

FIG. 2 is a flow diagram of a method of fault detection of an instruction word line in one embodiment;

FIG. 3 is a schematic diagram of a row instruction in one embodiment;

FIG. 4 is a schematic diagram of a column instruction in one embodiment;

FIG. 5 is a schematic diagram of a sequence of instruction words in one embodiment;

FIG. 6 is a schematic diagram of instruction processing circuitry in one embodiment;

FIG. 7 is a schematic diagram of a target data interface in one embodiment;

FIG. 8 is a diagram illustrating an introduction of a target data interface in one embodiment;

FIG. 9 is a schematic diagram illustrating the functional introduction of bits of a mode configuration instruction in one embodiment;

FIG. 10 is a code schematic of a target algorithm in one embodiment;

FIG. 11 is a schematic diagram of an architecture of a fault detection system for an instruction word line in one embodiment;

FIG. 12 is a diagram of transmission of a sequence of instruction words in one embodiment;

FIG. 13 is a block diagram of a fault detection device for an instruction word line in one embodiment;

FIG. 14 is a block diagram of another embodiment fault detection device for an instruction word line;

FIG. 15 is an internal block diagram of a computer device in one embodiment;

Fig. 16 is an internal structural view of a computer device in another embodiment.

Detailed Description

The present application will be described in further detail with reference to the drawings and examples, in order to make the objects, technical solutions and advantages of the present application more apparent. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the application.

Artificial intelligence (ARTIFICIAL INTELLIGENCE, AI) is the theory, method, technique, and application system that simulates, extends, and extends human intelligence using a digital computer or a machine controlled by a digital computer, perceives the environment, obtains knowledge, and uses the knowledge to obtain optimal results. In other words, artificial intelligence is an integrated technology of computer science that attempts to understand the essence of intelligence and to produce a new intelligent machine that can react in a similar way to human intelligence. Artificial intelligence, i.e. research on design principles and implementation methods of various intelligent machines, enables the machines to have functions of sensing, reasoning and decision.

With the research and advancement of artificial intelligence technology, the research and application of artificial intelligence technology is being developed in various fields, such as common artificial intelligence chips (ARTIFICIAL INTELLIGENCE, AI), smart homes, smart wearable devices, virtual assistants, smart speakers, smart marketing, unmanned, autopilot, unmanned, robotic, smart medical, smart customer service, etc., and it is believed that with the development of technology, artificial intelligence technology will be applied in more fields and will have increasingly important values.

The fault detection method of the instruction word line provided by the embodiment of the application can be applied to an application environment shown in fig. 1. Wherein the terminal 102 communicates with the server 104 via a network. The fault detection method of the command word line may be executed by the terminal 102 or the server 104, or may be executed in cooperation by the terminal 102 and the server 104. In some embodiments, the terminal 102 and the server 104 are provided with memory controllers, and the fault detection method of the command word line may be specifically executed by the memory controllers. If the fault detection method of the instruction word line is executed by the terminal 102, the terminal 102 sends an instruction word sequence to the target memory through the instruction word line, so that the target memory performs instruction processing on the instruction word sequence based on the instruction processing circuit to obtain a first target instruction word sequence; reading a first target instruction word sequence in a target memory through a target data interface; performing instruction processing on the instruction word sequence based on a target algorithm to obtain a second target instruction word sequence; and detecting line faults of the command word line in the process of command word transmission based on the first target command word sequence and the second target command word sequence.

The terminal 102 may be, but is not limited to, a smart phone, a tablet computer, a notebook computer, a desktop computer, a smart speaker, a smart watch, a smart voice interaction device, a smart home appliance, a vehicle-mounted terminal, etc. integrated with an AI chip. The AI chip may be a chip combining an AI processor and memory (e.g., high bandwidth memory). The memory may include a data storage area and a controller, or the controller may exist in a separate form and control the memory.

The server 104 may be a stand-alone physical server with an integrated AI chip or a service node in a blockchain system, where a Peer-To-Peer (P2P) network is formed between service nodes, and the P2P protocol is an application layer protocol running on top of a transmission control protocol (TCP, transmission Control Protocol) protocol.

The server 104 may be a server cluster formed by a plurality of physical servers integrated with AI chips, and may be a cloud server providing cloud services, cloud databases, cloud computing, cloud functions, cloud storage, network services, cloud communication, middleware services, domain name services, security services, content delivery networks (Content Delivery Network, CDN), and basic cloud computing services such as big data and artificial intelligence platforms.

The terminal 102 and the server 104 may be connected by a communication connection manner such as bluetooth, USB (Universal Serial Bus ) or a network, which is not limited in this disclosure.

In one embodiment, as shown in fig. 2, there is provided a fault detection method of an instruction word line, which is described by taking a computer device (terminal or server) in fig. 1 as an example, including the steps of:

S202, sending an instruction word sequence to a target memory through an instruction word line so that the target memory can perform instruction processing on the instruction word sequence based on an instruction processing circuit to obtain a first target instruction word sequence.

The target memory may be a high bandwidth memory (High Bandwidth Memory, HBM); specifically, the HBM DRAM (Dynamic Random Access Memory ), the instruction Word (AWORD) refers to a machine Word of an instruction, specifically refers to an instruction Word of a memory, for example, the AWORD of the HBM, the AWORD of the HBM is a generic term of a control signal on the HBM DRAM interface, and the following information is included in the HBM2E DRAM with a single channel as an example:

TABLE 1 Instructionword information Table

AWORD signal name	Bit width	Function of
			C	9	Column command signal
R	7	Row instruction signal
			CKE	1	Clock Enable signal

The command word line is a transmission line for transmitting command words, for example, a line for transmitting a column (C) command word in the above table may be referred to as a column (C) command word line, the column (C) command word includes C0 command words to C6 command words, a command word line for transmitting Ci command words is referred to as a Ci command word line for any one of Ci command words, a line for transmitting a row (R) command word may be referred to as a row (R) command word line, a row command word includes R0 command words to R6 command words, a command word line for transmitting Ri command words is referred to as a Ri command word line, and a line for transmitting a clock enable signal may be referred to as a Clock (CKE) command word line.

It can be understood that HBM AWORD is responsible for completing the function of sending instructions to HBM DRAM, HBM AWORD can be accurately transmitted only in the case of no failure of the instruction word line, and the accuracy of HBM AWORD ensures the accuracy of each operation of HBM. The instructions of HBM AWORD can be specifically divided into two main categories: a row instruction and a column instruction.

As shown in fig. 3, all row instructions supported by HBM 2E include row idle operation, activation, precharge, full precharge, single bank refresh, power-down entry, and self-refresh exit, and various row instructions include R0 to R6 instruction words, and for any Ri instruction word, the instruction word line for transmitting the Ri instruction word is called a Ri instruction word line, the Ri instruction word may also be called a Ri instruction word combination, and any Ri instruction word combination may include a Ri rising edge instruction word and a Ri falling edge instruction word, where the Ri rising edge instruction word and the Ri falling edge instruction word are all transmitted through the Ri instruction word line, that is, the Ri instruction word combination corresponds to the Ri instruction word line.

As shown in fig. 4, all column instructions supported by HBM 2E include, in particular, instructions such as column idle operation, read with auto-precharge, write with auto-precharge, and mode register setting, and various column instructions include C0 to C6 instruction words, and for any one Ci instruction word, an instruction word line for transmitting the Ci instruction word is called a Ci instruction word line, and the Ci instruction word may also be called a Ci instruction word combination, and any one Ci instruction word combination may include, in particular, a Ci rising edge instruction word and a Ci falling edge instruction word, where the Ci rising edge instruction word and the Ci falling edge instruction word are all transmitted through the Ci instruction word line, that is, the Ci instruction word combination corresponds to the Ci instruction word line.

In fig. 3 and 4, L refers to the value of the bit data bit being 0, h refers to the value of the bit data bit being 1, and V refers to the value of the bit data bit being either 0 or 1, but in the prior art design, V was implemented with 1 to reduce the 0 to 1 transition on the line because the default value on AWORD lines was 1. BAx refers to the x-th digit of the BANK address, e.g., BA4 refers to the fourth digit of the BANK address.

In the prior art, the fault detection method for the command word lines corresponding to the row command word and the column command word mainly completes parity check by sending PAR (Parity Check) check information, specifically, a transmitted command carries a PAR check bit, exclusive-or operation is performed on values of other bit data bits except the PAR check bit in the command to obtain an exclusive-or operation result, when the exclusive-or operation result is the same as the value of the PAR check bit, it is determined that each command word line used for transmitting the command has no fault, and when the exclusive-or operation result is different from the value of the PAR check bit, it is determined that at least one command word line in each command word line used for transmitting the command has fault, but the parity check method cannot determine which command word line has fault. The conventional parity check method is described by taking a row instruction as a refresh instruction as an example, and as shown in the following table 2, the values corresponding to each instruction word of one refresh instruction are transmitted:

TABLE 2

	R0	R1	R2	R3	R4	R5	R6
								Rising edge	0	0	1	1	1	1	1
Falling edge	1	1	PAR＝0	BA4＝0	1	1	1

As can be seen from table 2, the refresh command includes a check bit par=0, and the exclusive-or operation shown in the following formula is performed on the values of the data bits of each bit except for the PAR check bit in the refresh command, so that the exclusive-or operation result is 0, and the exclusive-or operation result is the same as the PAR value, so that it can be determined that each command word line of the refresh command has no fault, where "≡" indicates exclusive-or.

0^0^1^1^1^1^1^1^1^0^1^1^1＝0

The following table 3 shows values corresponding to each instruction word of the refresh instruction, where the rising edge instruction word of R1 has a transmission error from 0 to 1, the rising edge instruction word of R3 has a transmission error from 1 to 0, and the rising edge instruction word of R6 has a transmission error from 1 to 0:

TABLE 3 Table 3

R0

R1

R2

R3

R4

R5

R6

Rising edge

0

0->1

1

1->0

1

1->0

Falling edge

1

PAR＝0

BA4＝0

1

The exclusive-or operation shown in the following formula is performed on the values of the other bits of data bits except the PAR check bit in the refresh instruction shown in table 3, so that the exclusive-or operation result is 1, and the exclusive-or operation result is different from the PAR value, so that it can be determined that at least one instruction word line has a fault in each instruction word line of the refresh instruction, but it cannot be determined which instruction word line has a fault in each instruction word line, wherein "≡" indicates exclusive-or.

0^1^1^0^1^0^1^1^1^0^1^1^1＝1

Table 4 below shows values corresponding to each instruction word of the refresh instruction, where the rising edge instruction word of R3 has a transmission error of 1 to 0, and the rising edge instruction word of R4 has a transmission error of 1 to 0:

TABLE 4 Table 4

	R0	R1	R2	R3	R4	R5	R6
								Rising edge	0	0	1	1->0	1->0	1	1
Falling edge	1	1	PAR＝0	BA4＝0	1	1	1

The exclusive-or operation shown in the following formula is performed on the values of the other bits of data except the PAR check bit in the refresh instruction shown in table 4, so that the exclusive-or operation result is 0, and the exclusive-or operation result is the same as the PAR value, so that it is determined that each instruction word line of the refresh instruction has no fault, where "≡" indicates exclusive-or.

0^0^1^0^0^1^1^1^1^0^1^1^1＝0

As can be seen from the above examples, when the number of faulty instruction word lines is an odd number, the parity check can detect that the instruction word lines are faulty, but cannot determine which instruction word lines are faulty among the instruction word lines; when the number of faulty instruction word lines is an even number, parity cannot be used to fault the detected instruction word lines.

The instruction word sequence refers to an instruction word set formed by arranging a plurality of instruction words according to a certain sequence, and specifically, the instruction word sequence comprises a row instruction word, a clock period instruction word and a column instruction word. In the embodiment of the application, the instruction word sequence comprises a plurality of instruction word combinations, and each instruction word combination comprises a rising edge instruction word and a falling edge instruction word aiming at any row (R) instruction word combination, column (C) instruction word combination or clock cycle CKE instruction word combination, and specifically, one row instruction word combination comprises a row rising edge instruction word and a row falling edge instruction word; a clock cycle instruction word combination comprises a rising edge clock cycle instruction word and a falling edge clock cycle instruction word; a column instruction word combination includes a column rising edge instruction word and a column falling edge instruction word.

Since each instruction word combination is transmitted via its corresponding instruction word line, the number of instruction word lines used for transmitting the instruction word sequence is the same as the number of instruction word combinations contained in the instruction word sequence.

It will be appreciated that each instruction word in the sequence of instruction words corresponds to a respective instruction word data bit, and that the sequence of instruction words may correspond to a plurality of instruction word data bits, and may include, in particular, a row instruction word data bit, a clock cycle instruction word data bit, and a column instruction word data bit.

As shown in fig. 5, in one embodiment, the HBM instruction word sequence is arranged in an order from left to right, where the instruction word sequence includes 34 instruction word data bits: falling edge instruction word data bits and rising edge instruction word data bits of R5-R0, falling edge instruction word data bits and rising edge instruction word data bits of R6, falling edge instruction word data bits and rising edge instruction word data bits of C7-C4, falling edge instruction word data bits and rising edge instruction word data bits of CKE, falling edge instruction word data bits and rising edge instruction word data bits of C3-C0, and falling edge instruction word data bits and rising edge instruction word data bits of C8. Where F represents a rising edge instruction word data bit and R represents a falling edge instruction word data bit. It will be appreciated that for any one data bit, the value may be either 0 or 1.

The instruction processing may include only shift processing, which may be referred to as shift, or may include both compression processing and shift processing, where the compression processing may be referred to as compression, where the compression processing is to compress a plurality of instruction word sequences into one instruction word sequence, and the shift processing is to shift the instruction word sequence to obtain a new instruction word sequence. It will be appreciated that the instruction word sequence sent by the computer device to the target memory may be one or more, and when one instruction word sequence is used, the instruction word sequence may be subjected to a shift process to obtain a first target instruction word sequence, and when a plurality of instruction word sequences are used, the instruction word sequences may be subjected to a compression process and a shift process to obtain a first target instruction word sequence.

Specifically, the computer equipment generates an instruction word sequence, and each instruction word combination in the instruction word sequence is sent to a target memory in a target mode through an instruction word line corresponding to each instruction word, and after the target memory in the target mode receives the instruction word sequence, the target memory processes the instruction word sequence based on an instruction processing circuit corresponding to the target mode to obtain a first target instruction word sequence.

The number of data bits of the first target instruction word sequence is the same as the number of data bits of the instruction word sequence, for example, the instruction word sequence includes 34 instruction word data bits, and the first target instruction word sequence also includes 34 instruction word data bits. The test mode refers to a working mode of the target memory when the target memory is tested, the test mode can be multiple, the target mode is one of multiple test modes, for example, the target mode can be a Multiple Input Shift Register (MISR) mode, or a normal Register mode, and the instruction processing circuit corresponding to the test mode is a Multiple Input Shift Register (MISR) circuit.

It should be noted that a Multiple Input Shift Register (MISR) circuit may include a plurality of flip-flops and a plurality of input selectors alternately coupled in series with each other, and the plurality of input selectors may correspond to the plurality of flip-flops, respectively. Referring to fig. 4, when the input control signals M0 and M1 are both 1, i.e., when the input control signals M0 and M1 are both input at a logic high level, the MISR circuit corresponds to a multiple input shift register mode (MISR mode), i.e., the MISR circuit can perform the function of a multiple input shift register; when the input control signal M0 bit is 0 and M1 bit is 1, that is, when the input control signal M0 is input at a logic low level and M1 is input at a logic high level, the MISR circuit corresponds to a simple Register mode (Register mode), that is, the MISR circuit can perform a simple Register (Register) function; when the input control signal M0 bit is 1 and M1 bit is 10, that is, when the input control signal M0 is input at a logic high level and M1 is input at a logic low level, the MISR circuit corresponds to a linear feedback shift register mode (LFSR mode), that is, the MISR circuit may perform a Linear Feedback Shift Register (LFSR) function.

It will be appreciated that when the instruction word data bits of the instruction word sequence are 34 bit data bits, the corresponding MISR circuit may comprise 34 flip-flops and 34 input selectors to store and output 34 bit data bits, and the 34 bit MISR circuit may be described mathematically by the following polynomial:

f(X)＝X³⁴+X²⁷+X²+1

It will be appreciated that after the instruction processing circuit performs instruction processing on the instruction word sequence to obtain a first target instruction word sequence, the target memory may store the processed first target instruction word sequence in a memory unit corresponding to the instruction processing circuit, for example, in the AWORD MISR register unit. In the embodiment of the present application, if the input instruction word sequence is 34 bits of data, the first target instruction word sequence obtained by performing instruction processing on the input instruction word sequence is also 34 bits of data.

S204, reading a first target instruction word sequence in a target memory through a target data interface.

The target data interface is a data reading interface based on a target protocol standard, which may be IEEE standard 1500, as shown in fig. 7, which is a schematic diagram of a data reading interface defined by the IEEE1500 standard, and fig. 8 shows functional description information of each interface in fig. 7.

It should be noted that, the data stored in the target memory in the target mode may be read through the target data interface.

Specifically, after obtaining the first target instruction word sequence, the target memory stores the first target instruction word sequence in an internal register unit of the target memory, for example, in a AWORD MISR register unit, and the terminal can read the first target instruction word sequence stored in the internal register unit through the target data interface.

S206, performing instruction processing on the instruction word sequence based on the target algorithm to obtain a second target instruction word sequence.

The target algorithm may be an algorithm matched with the instruction processing circuit, that is, an effect of performing instruction processing on the instruction word sequence by the target algorithm is the same as an effect of performing instruction processing on the instruction word sequence by the instruction processing circuit. The number of data bits of the second target instruction word sequence is the same as the number of data bits of the instruction word sequence, for example, the instruction word sequence includes 34 instruction word data bits, and the second target instruction word sequence also includes 34 instruction word data bits.

The instruction processing may specifically include only shift processing, or may include both compression processing, which is to compress a plurality of instruction word sequences into one instruction word sequence, and shift processing, which is to shift the instruction word sequence to obtain a new instruction word sequence. It will be appreciated that the instruction word sequence sent by the computer device to the target memory may be one or more, and when one instruction word sequence is used, the instruction word sequence may be subjected to a shift process to obtain a second target instruction word sequence, and when a plurality of instruction word sequences are used, the instruction word sequences may be subjected to a compression process and a shift process to obtain a second target instruction word sequence.

Specifically, after the computer equipment generates the instruction word sequence, on one hand, the generated instruction word sequence is sent to the target memory, and on the other hand, a preset target algorithm is obtained, and the target algorithm is adopted to perform instruction processing on the generated instruction word sequence to obtain a second target instruction word sequence.

S208, detecting line faults of the instruction word line in the process of transmitting the instruction words based on the first target instruction word sequence and the second target instruction word sequence.

Specifically, after the first target instruction word sequence and the second target instruction word sequence are obtained, the computer equipment sequentially compares corresponding instruction words in the first target instruction word sequence and the second target instruction word sequence to obtain comparison results of the corresponding instruction words, and determines line faults of the instruction word lines in the process of transmitting the instruction words according to the corresponding comparison results, namely whether the instruction word lines have faults or not.

In one embodiment, S208 specifically includes the steps of: sequentially comparing the instruction word of each data bit in the first target instruction word sequence with the instruction word of the corresponding data bit in the second target instruction word sequence to obtain a comparison result; when the comparison result shows that the instruction words are identical, determining that the line fault of the instruction word line does not occur in the process of transmitting the instruction words; and when the comparison result shows that the instruction words of the target data bits are different, determining that the line of the instruction word has line faults in the process of transmitting the instruction word.

The instruction words of the corresponding data bits are compared in sequence, specifically, the values of the instruction words are compared, and the comparison result indicates that the instruction words are identical, and the values of the corresponding instruction words are identical.

For example, the instruction word sequence has 34 data bits from 0 bit data bit to 33 bit data bit, from right to left, the instruction word of 0 bit data bit to 33 bit data bit is instruction word 1, the instruction word of 1 bit data bit is instruction word2, and so on, the instruction word of 32 bit data bit is instruction word 33, the instruction word of 33 bit data bit is instruction word 34, each instruction word of the instruction word sequence has corresponding value, the corresponding first target instruction word sequence also has 34 bit data bits from 0 bit data bit to 33 bit data bit, the second target instruction word sequence also has 34 bit data bits from 0 bit data bit to 33 bit data bit, then the 0 bit data bit of the first target instruction word sequence corresponds to the 0 bit data bit of the second target instruction word sequence, the 1 bit data bit of the first target instruction word sequence corresponds to the 1 bit data bit of the second target instruction word sequence, and so on, the corresponding first target instruction word sequence corresponds to the first bit data bit of the second target instruction word sequence, in other words, the first target instruction word sequence corresponds to the 1 bit data bit of the second target instruction word sequence, and the first target instruction word sequence corresponds to the first target instruction word of the first target instruction word sequence, and the second target instruction word sequence corresponds to the first target instruction word of 1 bit of the second target instruction word sequence, and the target instruction word sequence corresponds to the first target instruction word of the first target instruction word sequence is compared with the first target instruction word of the first target instruction word sequence, and the first target instruction word of the first target instruction word sequence is compared with the first target instruction word of the first target instruction word sequence, and the target instruction word of the first target instruction sequence is compared with the first target bit of the target instruction word sequence is the first target bit 1, comparing the value of the instruction word2 of the first target instruction word sequence with the value of the instruction word2 of the second target instruction word sequence, and so on, comparing the value of the instruction word 34 of the first target instruction word sequence with the value of the instruction word 34 of the second target instruction word sequence to obtain comparison results of the instruction words of the corresponding data bits, when the values of the corresponding instruction words in the comparison results are the same, determining that a line fault does not occur in the instruction word line in the process of transmitting the instruction words, and when the comparison results indicate that the instruction words of the target data bits are different, determining that the line fault occurs in the instruction word line in the process of transmitting the instruction words, if the value of the instruction word i of the ith bit data bit of the first target instruction word sequence is different from the value of the instruction word i of the ith bit data bit of the second target instruction word sequence, determining that the line fault occurs in the instruction word line in the process of transmitting the instruction words.

In the above embodiment, the computer device compares the instruction word of each data bit in the first target instruction word sequence with the instruction word of the corresponding data bit in the second target instruction word sequence in sequence to obtain a comparison result, so that the specific failed instruction word line is determined when the transmission line fails according to the comparison result, and the capability of detecting the failure of the transmission line is improved.

In one embodiment, the number of instruction word lines is the same as the number of instruction word combinations in the instruction word sequence; each instruction word combination includes a rising edge instruction word and a falling edge instruction word; the computer equipment executes the process of determining that the line of the instruction word has line fault in the process of transmitting the instruction word when the instruction words of the target data bits are different as shown by the comparison result, wherein the process comprises the following steps: when the comparison result shows that the instruction words with the target data bits are different, determining a target instruction word line corresponding to the target data bits in the instruction word lines with the number; and determining that a line fault occurs in the target instruction word line in the process of transmitting the instruction word.

For example, referring to FIG. 5, the sequence of instruction words has 34 bits from 0 th bit data bit to 33 rd bit data bit, from right to left in turn, the 0 th bit data bit to 33 rd bit data bit, the 0 th bit data bit of the instruction word is a C8 rising edge instruction word, the 1 st bit data bit of the instruction word is a C8 falling edge instruction word, and so on, the 32 nd bit data bit of the instruction word is an R5 rising edge instruction word, the 33 rd bit data bit of the instruction word is an R5 falling edge instruction word, each instruction word of the sequence of instruction words has a corresponding value, the corresponding first sequence of target instruction words also has 34 bits from 0 th bit to 33 th bit data bit, the second sequence of target instruction words also has 34 bits from 0 th bit data bit to 33 th bit data bit, then the 0 th bit data bit of the first sequence of target instruction words corresponds to the 0 th bit data bit of the second sequence of target instruction words, the 1 st bit data bit of the first target instruction word sequence corresponds to the 1 st bit data bit of the second target instruction word sequence, and so on, the 33 rd bit data bit of the first target instruction word sequence corresponds to the 33 rd bit data bit of the second target instruction word sequence, in other words, the C8 rising edge instruction word of the first target instruction word sequence corresponds to the C8 rising edge instruction word of the second target instruction word sequence, the C8 falling edge instruction word of the first target instruction word sequence corresponds to the C8 falling edge instruction word of the second target instruction word sequence, and so on, the R5 falling edge instruction word of the first target instruction word sequence corresponds to the R5 falling edge instruction word of the second target instruction word sequence, comparing the C8 rising edge instruction word of the first target instruction word sequence with the C8 rising edge instruction word of the second target instruction word sequence, comparing the C8 falling edge instruction word of the first target instruction word sequence with the C8 falling edge instruction word of the second target instruction word sequence, and so on, comparing the R5 falling edge instruction word of the first target instruction word sequence with the R5 falling edge instruction word of the second target instruction word sequence to obtain the comparison result of each corresponding data bit instruction word, determining that a line fault does not occur in the process of transmitting the instruction word of the instruction word when the values of the corresponding instruction words in the comparison result are the same, and determining that the line fault occurs in the process of transmitting the instruction word of the instruction word when the comparison result indicates that the instruction word of the target data bit is different, if the C8 rising edge instruction word of the 0 bit data bit of the first target instruction word sequence is different from the C8 rising edge instruction word of the 0 bit data bit of the second target instruction word sequence, determining that the line fault occurs in the process of transmitting the instruction word of the C8 rising edge instruction word of the corresponding to the C8.

In the above embodiment, when the comparison result indicates that the instruction words with the target data bits are different, the target instruction word line corresponding to the target data bits is determined in the number of instruction word lines, so that it is precisely determined that the line fault occurs in the target instruction word line in the process of transmitting the instruction word, and the capability of detecting the transmission line fault is improved.

In one embodiment, the sequence of instruction words includes a row instruction word, a clock cycle instruction word, and a column instruction word, the column instruction word includes a parity instruction word, and the computer device further determines whether the instruction word of the target data bit is a parity instruction word when determining that the instruction word of the target data bit is different, and determines that an instruction word line corresponding to the parity instruction word fails in the process of transmitting the instruction word when the instruction word of the target data bit is the parity instruction word.

For example, as shown in fig. 3 and 4, the R2 falling edge instruction word may also be referred to as a parity instruction word (PAR), and the C2 falling edge instruction word may also be referred to as a parity instruction word (PAR). Referring to fig. 5, the instruction word sequence has 34 data bits from the 0 th bit data bit to the 33 rd bit data bit, and referring to fig. 3 and 4, it can be seen that the instruction word of the 7 th bit data bit in fig. 5 is a parity instruction word, the instruction word of the 27 th bit data bit is a parity instruction word, and if the computer device determines that the target data bit is the i-th bit data bit, when i is equal to 7 or 27, it is determined that the instruction word of the target data bit is a parity instruction word, and further it is determined that a fault occurs in an instruction word line corresponding to the parity instruction word in the instruction word transmission process.

In the above embodiment, when the instruction word of the target data bit is a parity check instruction word, the computer device determines that the instruction word line corresponding to the parity check instruction word has a fault in the process of transmitting the instruction word, which solves the problem that if the PAR bit itself has a transmission fault of the instruction word line in the conventional PAR-based fault detection method, the PAR-based fault detection method fails to detect the fault of the instruction word line, and a false alarm fault or a false alarm fault may occur.

In one embodiment, when the instruction words of the target data bits are determined to be different according to the comparison result, the computer device may further determine the positions of the target data bits in the instruction word sequence and the number of instruction word lines corresponding to the target data bits.

For example, referring to the instruction word sequence shown in fig. 5, if the computer device determines that the target data bits are the 2 nd bit data bit, the 3 rd bit data bit, and the 28 th bit data bit, respectively, where the instruction word of the 2 nd bit data bit is a C0 rising edge instruction word, the instruction word of the 3 rd bit data bit is a C0 falling edge instruction word, the instruction word of the 28 th bit data bit is an R3 rising edge instruction word, that is, the 2 nd bit data bit and the 3 rd bit data bit both correspond to the C0 instruction word line, and the 28 th bit data bit corresponds to the R3 instruction word line, then the number of the instruction word lines corresponding to the target data bit is determined to be2, that is, the number of the instruction word lines having the line fault is determined to be 2.

In the above embodiment, when the comparison result indicates that the instruction words of the target data bits are different, the computer device may further determine the position of the target data bit in the instruction word sequence and the number of instruction word lines corresponding to the target data bit, that is, may detect all the instruction word line faults, and may locate the position of the bit where each instruction word line fault is located, thereby improving the capability of detecting the transmission line fault.

It can be understood that when the instruction word line for transmitting the instruction word sequence has no fault, the instruction word sequence sent by the terminal is identical to the instruction word sequence received by the target memory, and in the case that the target algorithm is an algorithm matched with the instruction processing circuit, the first target instruction word sequence obtained by performing instruction processing on the instruction word sequence based on the instruction processing circuit is identical to the second target instruction word sequence obtained by performing instruction processing on the instruction word sequence based on the target algorithm; when an instruction word line for transmitting an instruction word sequence has faults, the instruction word sequence sent by the terminal is different from the instruction word sequence received by the target memory, and under the condition that the target algorithm is an algorithm matched with the instruction processing circuit, a first target instruction word sequence obtained by performing instruction processing on the received instruction word sequence based on the instruction processing circuit is different from a second target instruction word sequence obtained by performing instruction processing on the instruction word sequence based on the target algorithm. It is thus possible to determine whether an instruction word line has failed during the transmission of an instruction word by determining whether the values of the instruction words of the corresponding bits in the first target instruction word sequence and the second target instruction word sequence are identical.

In the fault detection method of the instruction word line, an instruction word sequence is sent to the target memory through the instruction word line, so that the target memory carries out instruction processing on the instruction word sequence based on the instruction processing circuit to obtain a first target instruction word sequence; reading a first target instruction word sequence in a target memory through a target data interface; performing instruction processing on the instruction word sequence based on a target algorithm to obtain a second target instruction word sequence; based on the first target instruction word sequence and the second target instruction word sequence, line faults of the instruction word lines in the process of transmitting the instruction words are detected, so that the specific faulty instruction word line and the faulty target instruction word in the instruction word sequence can be determined when the transmission line breaks down, and the detection capability of the transmission line faults is improved.

In one embodiment, before the computer device sends the instruction word sequence to the target memory, the computer device needs to configure the test mode of the target memory, and the process of configuring the test mode of the target memory specifically includes the following steps: sending a mode configuration instruction to a target memory, so that the target memory configures a test mode into a first register mode and a second register mode based on the mode configuration instruction; when the target memory is in the first register mode, transmitting an instruction word sequence to the target memory through an instruction word line; when the target memory is in the second register mode, the first sequence of target instruction words is read from the target memory based on the target data interface.

Wherein the first Register mode is a multiple input shift Register mode (MISR mode) and the second Register mode is a simple Register mode (Register mode).

Specifically, after configuring the target memory into the multiple-input shift Register mode (MISR mode), the computer device sends a sequence of instruction words to the target memory through an instruction word line, and the target Register in the multiple-input shift Register mode (MISR mode) may perform instruction processing on the received sequence of instruction words to obtain a first sequence of target instruction words, and store the first sequence of target instruction words in the Register unit, after which the computer device configures the target memory into the simple Register mode (Register mode), and the computer device may read the first sequence of target instruction words stored in the Register unit through the target data interface.

In the above embodiment, the computer device sends the mode configuration instruction to the target memory, so that the target memory configures the test mode into the first register mode and the second register mode based on the mode configuration instruction, so that the target memory in the first register mode may process the instruction word sequence received to obtain the first target instruction word sequence, so that the target memory in the second register mode may output the first target instruction word sequence to the computer device through the target data interface, so that the computer device may detect, based on the first target instruction word sequence and the second target instruction word sequence, a line fault occurring in the instruction word line during the instruction word transmission process, so that a specific faulty instruction word line may be determined when the transmission line fails, and a target instruction word with an error occurring in the instruction word sequence may improve the capability of detecting the transmission line fault.

In one embodiment, the mode configuration instructions include a first mode configuration instruction and a second mode configuration instruction, and the process of the target memory configuring the test mode into the first register mode and the second register mode based on the mode configuration instructions includes the steps of: initializing an instruction processing circuit; based on the first mode configuration instruction, configuring a test mode of the instruction processing circuit to be a first register mode; based on the second mode configuration instruction, the test mode of the configuration instruction processing circuit is a second register mode.

Wherein the mode configuration instruction comprises 8 bits of data, different mode configuration instructions being generated by changing the values of different bits of data.

For example, the AWORD MISR register unit inside the HBM DRAM needs to complete the configuration of the AWORD _misr_config WRAPPER DATA REGISTER register after the initialization is completed, and then the AWORD MISR mode can be entered. As shown in fig. 9, the HBM DRAM has a functional description corresponding to each bit data bit of the mode configuration instruction, wherein the 7 th bit data bit is used to select the polynomial bit number supported by the MISR circuit, the 3 rd bit data bit is used to select whether AWORD MISR is enabled or not, and the 2 nd to 0th bit data bits are used to set the target mode.

Specifically, the computer device generates an initialization instruction and sends the initialization instruction to the target memory, the target memory initializes the instruction processing circuit based on the initialization instruction after receiving the initialization instruction, then the computer device sends a first mode configuration instruction to the target memory, the initialized target memory configures a test mode of the instruction processing circuit of the target memory to be a first register mode based on the first mode configuration instruction, the computer device sends a second mode configuration instruction to the target memory of the first register mode after sending an instruction word sequence to the target memory of the first register mode, and the target memory of the first register mode configures the test mode of the instruction processing circuit to be a second register mode based on the second mode configuration instruction.

In the above embodiment, the target memory is initialized by the instruction processing circuit; based on the first mode configuration instruction, configuring a test mode of the instruction processing circuit to be a first register mode; based on the second mode configuration instruction, the test mode of the configuration instruction processing circuit is a second register mode, so that the target memory in the first register mode can process instruction words of the received instruction word sequences to obtain a first target instruction word sequence, the target memory in the second register mode can output the first target instruction word sequence to the computer equipment through the target data interface, and the computer equipment can detect line faults of the instruction word lines in the process of transmitting the instruction words based on the first target instruction word sequence and the second target instruction word sequence, and therefore the specific faulty instruction word line and the faulty target instruction word in the instruction word sequence can be determined when the transmission line fails, and the detection capability of the transmission line faults is improved.

In one embodiment, the process of the computer device sending a sequence of instruction words to the target memory over the instruction word line to cause the target memory to process instructions on the sequence of instruction words based on the instruction processing circuitry to obtain a first sequence of target instruction words includes the steps of: transmitting an instruction word sequence to a target memory through an instruction word line so that the target memory shifts the instruction word sequence based on an instruction processing circuit to obtain a first target instruction word sequence; or transmitting at least two instruction word sequences to the target memory through the instruction word line so as to enable the target memory to compress the at least two instruction word sequences, and shifting the compressed instruction word sequences based on the instruction processing circuit to obtain a first target instruction word sequence.

Specifically, the number of instruction word sequences sent by the computer device to the target memory may be one or more, and it may be understood that when the number of instruction word sequences sent is one, the target memory performs shift processing on the instruction word sequence based on the instruction processing circuit to obtain a first target instruction word sequence; when the number of the instruction word sequences transmitted is at least two, the target memory can compress the at least two instruction word sequences into a new instruction word sequence, and shift the new instruction word sequence obtained by compression based on the instruction processing circuit to obtain a first target instruction word sequence.

The target memory can compress at least two instruction word sequences by adopting a compression algorithm, the compression algorithm can be an exclusive-or algorithm, and the exclusive-or algorithm is adopted to carry out exclusive-or operation on corresponding data bits of a plurality of instruction word sequences, so that a new instruction word sequence is obtained.

For example, there are an instruction word sequence 1 and an instruction word sequence 2, the instruction word sequence 1 has 34 data bits from the 0 th bit data bit to the 33 th bit data bit, the instruction word sequence 2 also has 34 data bits from the 0 th bit data bit to the 33 th bit data bit, then the 0 th bit data bit of the instruction word sequence 1 corresponds to the 0 th bit data bit of the instruction word sequence 2, the 1 st bit data bit of the instruction word sequence 1 corresponds to the 1 st bit data bit of the instruction word sequence 2, and so on, the 33 rd bit data bit of the instruction word sequence 1 corresponds to the 33 rd bit data bit of the instruction word sequence 2, the computer device performs exclusive-or operation on the values of the 0 th bit data bit in the instruction word sequence 1 and the 33 th bit data bit in the instruction word sequence 2 to obtain an operation result of the 0 th bit data bit, performs exclusive-or operation on the values of the 1 st bit data bit in the instruction word sequence 1 and the 1 st bit data bit in the instruction word sequence 2 to obtain an operation result of the 33 bit, and then performs exclusive-or operation on the 33 bit data bit in the instruction word sequence 2 according to the order of the result of the 33 bit data.

The instruction processing circuit used by the target memory may be a MISR circuit of the multiple input shift register mode (MISR mode) shown in fig. 6, by which the shifting of the compressed instruction word sequence to obtain the first target instruction word sequence may be implemented. The instruction processing circuit used in the target memory may be a MISR circuit in a linear feedback shift register mode (LFSR mode).

In the above embodiment, the computer device sends an instruction word sequence to the target memory through the instruction word line, so that the target memory shifts the instruction word sequence based on the instruction processing circuit to obtain a first target instruction word sequence; or at least two instruction word sequences are sent to the target memory through the instruction word line, so that the target memory compresses the at least two instruction word sequences, and the compressed instruction word sequences are shifted based on the instruction processing circuit to obtain a first target instruction word sequence, so that the computer equipment can detect line faults of the instruction word line in the process of transmitting the instruction word based on the first target instruction word sequence and the second target instruction word sequence, and therefore the specific faulty instruction word line and the faulty target instruction word in the instruction word sequence can be determined when the transmission line breaks down, and the detection capability of the transmission line fault is improved.

In one embodiment, the target algorithm includes at least one of a compression algorithm and a shift algorithm; the process of the computer equipment for carrying out instruction processing on the instruction word sequence based on the target algorithm to obtain a second target instruction word sequence comprises the following steps: when an instruction word sequence is sent, shifting the instruction word sequence based on a shifting algorithm to obtain a second target instruction word sequence; and when at least two instruction word sequences are transmitted, compressing the at least two instruction word sequences based on a compression algorithm, and shifting the compressed instruction word sequences based on a shifting algorithm to obtain a second target instruction word sequence.

The target algorithm may be an algorithm matched with the instruction processing circuit, that is, an effect of performing instruction processing on the instruction word sequence by the target algorithm is the same as an effect of performing instruction processing on the instruction word sequence by the instruction processing circuit. The target algorithm comprises a compression algorithm and a shift algorithm, wherein the compression algorithm is used for compressing a plurality of instruction word sequences to obtain an instruction word sequence, and the shift algorithm is used for carrying out shift processing on an input instruction word sequence to obtain a new instruction word sequence.

Specifically, the number of the instruction word sequences sent to the target memory by the computer device may be one or more, and it may be understood that when the number of the instruction word sequences sent is one, the computer device performs a shift process on the instruction word sequence by using a shift algorithm to obtain a second target instruction word sequence; when the number of the transmitted instruction word sequences is at least two, the computer equipment firstly compresses the at least two instruction word sequences into a new instruction word sequence based on a compression algorithm, and carries out shift processing on the new instruction word sequence obtained by compression based on a shift algorithm to obtain a second target instruction word sequence.

In one embodiment, the compression algorithm may be an exclusive-or algorithm, and the exclusive-or algorithm is used to perform an exclusive-or operation on corresponding data bits of the plurality of instruction word sequences, thereby obtaining a new instruction word sequence.

For example, there are an instruction word sequence 1 and an instruction word sequence 2, the instruction word sequence 1 has 34 bit data bits from the 0 th bit data bit to the 33 th bit data bit, the instruction word sequence 2 also has 34 bit data bits from the 0 th bit data bit to the 33 th bit data bit, then the 0 th bit data bit of the instruction word sequence 1 corresponds to the 0 th bit data bit of the instruction word sequence 2, the 1 st bit data bit of the instruction word sequence 1 corresponds to the 1 st bit data bit of the instruction word sequence 2, and so on, the 33 rd bit data bit of the instruction word sequence 1 corresponds to the 33 rd bit data bit of the instruction word sequence 2, the computer device performs exclusive-or operation on the values of the 0 th bit data bit in the instruction word sequence 1 and the 33 th bit data bit in the instruction word sequence 2 to obtain an exclusive-or operation result, performs exclusive-or operation on the values of the 1 st bit data bit in the instruction word sequence 1 and the 1 st bit data bit in the instruction word sequence 2 to obtain an exclusive-or operation result, and then performs exclusive-or operation on the 33 bit data bit in the order based on the 33 bit data bit sequence 3 to obtain an exclusive-or result.

In one embodiment, the shift algorithm may be a MISR algorithm, as shown in fig. 10, which is a code schematic diagram of the shift algorithm in one embodiment, and the computer device may generate a new sequence of instruction words by running the code.

For example, after compressing the instruction word sequence 1 and the instruction word sequence 2 to obtain the instruction word sequence 3, the computer device may use the instruction word sequence 3 as an input of the shift algorithm shown in fig. 10, and execute the code shown in fig. 10 to obtain the instruction word sequence 4.

In the above embodiment, when an instruction word sequence is sent, the computer device shifts the instruction word sequence based on a shift algorithm to obtain a second target instruction word sequence; when at least two instruction word sequences are sent, the computer equipment compresses the at least two instruction word sequences based on a compression algorithm, and shifts the instruction word sequences obtained by compression based on a shift algorithm to obtain a second target instruction word sequence, so that the computer equipment can detect line faults of the instruction word lines in the process of transmitting the instruction words based on the first target instruction word sequence and the second target instruction word sequence, and can determine the specific faulty instruction word lines and the target instruction words with errors in the instruction word sequences when the transmission lines are faulty, and the detection capability of the transmission line faults is improved.

The application also provides an application scene, which applies the fault detection method of the instruction word line. Specifically, the fault detection method of the instruction word line is applied to the application scene as follows:

step one, target memory initialization

Specifically, the HBM Host sends an initialization instruction to the target register to cause the target memory to complete initialization based on the initialization instruction.

Wherein, the initialization command comprises 8 bits, referring to the function description corresponding to each bit data bit shown in fig. 9, the specific configurable bit POLYNOMIAL _select bit is 1, and the 34bit mode is selected; note that HBM2 DRAM devices should select 30bit mode and HBM2E DRAM devices should select 34bit mode; simultaneously configuring a bit3 ENABLE bit to be 1, enabling the AWORD MISR mode; configuring three bits of bit2 to bit0 as 000, and setting the initial value of AWORD MISR as 0x2AAAAAAAh, thereby completing the initialization of the target memory.

MISR mode setting of target memory

Specifically, the HBM Host sends a MISR mode configuration instruction to the target register to cause the target memory to complete MISR mode setting of the target memory based on the MISR mode configuration instruction.

The MISR mode configuration instruction includes 8 bits, and specifically, configurable bits 2 to 03 are 011 and set as MISR mode, referring to the function description corresponding to each bit data bit shown in fig. 9.

Step three, transmitting a plurality of instruction word sequences to a target memory of MISR mode

Specifically, referring to the frame diagram shown in FIG. 11, HBM Host sends AWORD to target memory (HBM DRAM), where at least 1 set AWORD of data is to be sent.

As shown in FIG. 12, write AWORD patterns number 4 groups.

Fourth, register mode setting of target memory

Specifically, the HBM Host sends a Register mode configuration instruction to the target Register to cause the target memory to complete target memory Register mode settings based on the Register mode configuration instruction.

The Register mode configuration instruction comprises 8 bits, and referring to the function description corresponding to each bit data bit shown in fig. 9, bits 2 to 03 of the specific configurable bits are 010 and set as Register mode.

Step five, reading the first target instruction word sequence from the target memory

Referring to fig. 11, specifically, the HBM Host initiates a read AWORD request to the destination register, and reads out the first destination instruction word sequence (MISR PATTERN) through the IEEE1500 interface.

As shown in fig. 12, the number of patterns of Write AWORD is 4, and the target memory processes 4 sets Write AWORD to obtain a set MISR PATTERN, HBM Host, and reads the set MISR PATTERN as Read AWORD through the IEEE1500 interface.

Step five, instruction word line fault detection

Referring to fig. 11, specifically, the HBM Host performs instruction processing on AWORD sent to the target memory to obtain a second target instruction word sequence, and compares the second target instruction word sequence with the first target instruction word sequence, so as to determine the correctness of the AWORD line.

Specifically, the instruction processing performed on AWORD sent to the target memory may perform instruction processing on AWORD by using a MISR algorithm.

By the fault detection method of the command word line, the following technical effects can be achieved: 1. all instruction word line faults can be detected, and the position of the bit of each instruction word line fault can be positioned; 2. the number of faults of any number of instruction word lines can be detected, and the problem that parity check only can find faults of odd number and faults of even number can not be detected is completely solved; 3. the method solves the problems that in the traditional PAR-based fault detection method, if the PAR bit itself has the transmission fault of the instruction word line, the detection of the fault of the instruction word line by the PAR-based fault detection method is invalid, and false alarm fault or missing alarm fault can occur.

It should be understood that, although the steps in the flowcharts related to the embodiments described above are sequentially shown as indicated by arrows, these steps are not necessarily sequentially performed in the order indicated by the arrows. The steps are not strictly limited to the order of execution unless explicitly recited herein, and the steps may be executed in other orders. Moreover, at least some of the steps in the flowcharts described in the above embodiments may include a plurality of steps or a plurality of stages, which are not necessarily performed at the same time, but may be performed at different times, and the order of the steps or stages is not necessarily performed sequentially, but may be performed alternately or alternately with at least some of the other steps or stages.

Based on the same inventive concept, the embodiment of the application also provides a fault detection device of the instruction word line for realizing the fault detection method of the instruction word line. The implementation of the solution provided by the device is similar to the implementation described in the above method, so the specific limitation in the embodiments of the fault detection device for one or more instruction word lines provided below may be referred to the limitation of the fault detection method for an instruction word line hereinabove, and will not be repeated herein.

In one embodiment, as shown in fig. 13, there is provided a fault detection device of an instruction word line, including: an instruction sending module 1302, a data reading module 1304, an instruction processing module 1306, and a fault detection module 1308, wherein:

The instruction sending module 1302 is configured to send the instruction word sequence to the target memory through the instruction word line, so that the target memory performs instruction processing on the instruction word sequence based on the instruction processing circuit to obtain a first target instruction word sequence.

The data reading module 1304 is configured to read a first target instruction word sequence in the target memory through the target data interface.

The instruction processing module 1306 is configured to perform instruction processing on the instruction word sequence based on the target algorithm to obtain a second target instruction word sequence.

A fault detection module 1308 is configured to detect a line fault of the instruction word line during the instruction word transmission process based on the first target instruction word sequence and the second target instruction word sequence.

In the above embodiment, the instruction word line is used to send the instruction word sequence to the target memory, so that the target memory performs instruction processing on the instruction word sequence based on the instruction processing circuit to obtain the first target instruction word sequence; reading a first target instruction word sequence in a target memory through a target data interface; performing instruction processing on the instruction word sequence based on a target algorithm to obtain a second target instruction word sequence; based on the first target instruction word sequence and the second target instruction word sequence, line faults of the instruction word lines in the process of transmitting the instruction words are detected, so that the specific faulty instruction word line and the faulty target instruction word in the instruction word sequence can be determined when the transmission line breaks down, and the detection capability of the transmission line faults is improved.

In one embodiment, the fault detection module 1308 is further to: sequentially comparing the instruction word of each data bit in the first target instruction word sequence with the instruction word of the corresponding data bit in the second target instruction word sequence to obtain a comparison result; when the comparison result shows that the instruction words are identical, determining that the line fault of the instruction word line does not occur in the process of transmitting the instruction words; and when the comparison result shows that the instruction words of the target data bits are different, determining that the line of the instruction word has line faults in the process of transmitting the instruction word.

In one embodiment, the number of instruction word lines is the same as the number of instruction word combinations in the instruction word sequence; each instruction word combination includes a rising edge instruction word and a falling edge instruction word; the fault detection module 1308 is further configured to: when the comparison result shows that the instruction words with the target data bits are different, determining a target instruction word line corresponding to the target data bits in the number of instruction word lines; and determining that a line fault occurs in the target instruction word line in the process of transmitting the instruction word.

In one embodiment, the instruction word combinations include a row instruction word combination, a clock cycle instruction word combination, and a column instruction word combination, the column instruction word combination including a parity instruction word; the fault detection module 1308 is further configured to: when the instruction word of the target data bit is a parity check instruction word, determining that an instruction word line corresponding to the parity check instruction word fails in the process of transmitting the instruction word.

In one embodiment, the row instruction word combination includes a row rising edge instruction word and a row falling edge instruction word; the clock period instruction word combination comprises a rising edge clock period instruction word and a falling edge clock period instruction word; the column instruction word combination includes a column rising edge instruction word and a column falling edge instruction word.

In one embodiment, the fault detection module 1308 is further to: and when the comparison result shows that the instruction words of the target data bits are different, determining the positions of the target data bits in the instruction word sequences and the number of the instruction word lines corresponding to the target data bits.

In one embodiment, as shown in fig. 14, the apparatus further comprises: a mode configuration module 1310, configured to send a mode configuration instruction to the target memory, so that the target memory configures the test mode into a first register mode and a second register mode based on the mode configuration instruction; the sending module is further used for sending an instruction word sequence to the target memory through the instruction word line when the target memory is in the first register mode; the data reading module 1304 is further configured to: when the target memory is in the second register mode, the first sequence of target instruction words is read from the target memory based on the target data interface.

In one embodiment, the mode configuration instructions include a first mode configuration instruction and a second mode configuration instruction; the mode configuration module 1310 is further configured to: initializing an instruction processing circuit; based on the first mode configuration instruction, configuring a test mode of the instruction processing circuit to be a first register mode; based on the second mode configuration instruction, the test mode of the configuration instruction processing circuit is a second register mode.

In one embodiment, the instruction sending module 1302 is further configured to: transmitting an instruction word sequence to a target memory through an instruction word line so that the target memory shifts the instruction word sequence based on an instruction processing circuit to obtain a first target instruction word sequence; or transmitting at least two instruction word sequences to the target memory through the instruction word line so as to enable the target memory to compress the at least two instruction word sequences, and shifting the compressed instruction word sequences based on the instruction processing circuit to obtain a first target instruction word sequence.

In one embodiment, the target algorithm includes at least one of a compression algorithm and a shift algorithm; the instruction processing module 1306 is further configured to: when an instruction word sequence is sent, shifting the instruction word sequence based on a shifting algorithm to obtain a second target instruction word sequence; and when at least two instruction word sequences are transmitted, compressing the at least two instruction word sequences based on a compression algorithm, and shifting the compressed instruction word sequences based on a shifting algorithm to obtain a second target instruction word sequence.

In one embodiment, the target memory is a high bandwidth memory; the target data interface is a data read interface based on a target protocol standard.

The respective modules in the fault detection device of the above-described instruction word line may be implemented in whole or in part by software, hardware, and a combination thereof. The above modules may be embedded in hardware or may be independent of a processor in the computer device, or may be stored in software in a memory in the computer device, so that the processor may call and execute operations corresponding to the above modules.

In one embodiment, a computer device is provided, which may be a server, and the internal structure of which may be as shown in fig. 15. The computer device includes a processor, a memory, an Input/Output interface (I/O) and a communication interface. The processor, the memory and the input/output interface are connected through a system bus, and the communication interface is connected to the system bus through the input/output interface. Wherein the processor of the computer device is configured to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system, computer programs, and a database. The internal memory provides an environment for the operation of the operating system and computer programs in the non-volatile storage media. The database of the computer device is for storing instruction word data. The input/output interface of the computer device is used to exchange information between the processor and the external device. The communication interface of the computer device is used for communicating with an external terminal through a network connection. The computer program, when executed by a processor, implements a method of fault detection of an instruction word line.

In one embodiment, a computer device is provided, which may be a terminal, and the internal structure thereof may be as shown in fig. 16. The computer device includes a processor, a memory, an input/output interface, a communication interface, a display unit, and an input means. The processor, the memory and the input/output interface are connected through a system bus, and the communication interface, the display unit and the input device are connected to the system bus through the input/output interface. Wherein the processor of the computer device is configured to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system and a computer program. The internal memory provides an environment for the operation of the operating system and computer programs in the non-volatile storage media. The input/output interface of the computer device is used to exchange information between the processor and the external device. The communication interface of the computer device is used for carrying out wired or wireless communication with an external terminal, and the wireless mode can be realized through WIFI, a mobile cellular network, NFC (near field communication) or other technologies. The computer program, when executed by a processor, implements a method of fault detection of an instruction word line. The display unit of the computer equipment is used for forming a visual picture, and can be a display screen, a projection device or a virtual reality imaging device, wherein the display screen can be a liquid crystal display screen or an electronic ink display screen, the input device of the computer equipment can be a touch layer covered on the display screen, can also be a key, a track ball or a touch pad arranged on a shell of the computer equipment, and can also be an external keyboard, a touch pad or a mouse and the like.

It will be appreciated by those skilled in the art that the structures shown in fig. 15 or 16 are merely block diagrams of portions of structures associated with aspects of the application and are not intended to limit the computer device to which aspects of the application may be applied, and that a particular computer device may include more or fewer components than those shown, or may combine certain components, or may have a different arrangement of components.

In an embodiment, there is also provided a computer device comprising a memory and a processor, the memory having stored therein a computer program, the processor implementing the steps of the method embodiments described above when the computer program is executed.

In one embodiment, a computer-readable storage medium is provided, on which a computer program is stored which, when executed by a processor, carries out the steps of the method embodiments described above.

In an embodiment, a computer program product is provided, comprising a computer program which, when executed by a processor, implements the steps of the method embodiments described above.

It should be noted that, the user information (including but not limited to user equipment information, user personal information, etc.) and the data (including but not limited to data for analysis, stored data, presented data, etc.) related to the present application are information and data authorized by the user or sufficiently authorized by each party, and the collection, use and processing of the related data need to comply with the related laws and regulations and standards of the related country and region.

Those skilled in the art will appreciate that implementing all or part of the above described methods may be accomplished by way of a computer program stored on a non-transitory computer readable storage medium, which when executed, may comprise the steps of the embodiments of the methods described above. Any reference to memory, database, or other medium used in embodiments provided herein may include at least one of non-volatile and volatile memory. The nonvolatile Memory may include Read-Only Memory (ROM), magnetic tape, floppy disk, flash Memory, optical Memory, high density embedded nonvolatile Memory, resistive random access Memory (ReRAM), magneto-resistive random access Memory (Magnetoresistive Random Access Memory, MRAM), ferroelectric Memory (Ferroelectric Random Access Memory, FRAM), phase change Memory (PHASE CHANGE Memory, PCM), graphene Memory, and the like. Volatile memory can include random access memory (Random Access Memory, RAM) or external cache memory, and the like. By way of illustration, and not limitation, RAM can be in various forms such as static random access memory (Static Random Access Memory, SRAM) or dynamic random access memory (Dynamic Random Access Memory, DRAM), etc. The databases referred to in the embodiments provided herein may include at least one of a relational database and a non-relational database. The non-relational database may include, but is not limited to, a blockchain-based distributed database, and the like. The processor referred to in the embodiments provided in the present application may be a general-purpose processor, a central processing unit, a graphics processor, a digital signal processor, a programmable logic unit, a data processing logic unit based on quantum computing, or the like, but is not limited thereto.

The technical features of the above embodiments may be arbitrarily combined, and all possible combinations of the technical features in the above embodiments are not described for brevity of description, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.

The foregoing examples illustrate only a few embodiments of the application and are described in detail herein without thereby limiting the scope of the application. It should be noted that it will be apparent to those skilled in the art that several variations and modifications can be made without departing from the spirit of the application, which are all within the scope of the application. Accordingly, the scope of the application should be assessed as that of the appended claims.

Claims

1. A method of fault detection for an instruction word line, the method comprising:

Performing instruction processing on the instruction word sequence based on a target algorithm to obtain a second target instruction word sequence; the target algorithm is an algorithm matched with the instruction processing circuit;

2. The method of claim 1, wherein detecting a line fault in the instruction word line during instruction word transmission based on the first target instruction word sequence and the second target instruction word sequence comprises:

Sequentially comparing the instruction word of each data bit in the first target instruction word sequence with the instruction word of the corresponding data bit in the second target instruction word sequence to obtain a comparison result;

When the comparison result shows that the instruction words are the same, determining that the line of the instruction word has no road fault in the process of transmitting the instruction words;

and when the comparison result shows that the instruction words of the target data bits are different, determining that the line fault occurs in the instruction word line in the process of transmitting the instruction words.

3. The method of claim 2, wherein the number of instruction word lines is the same as the number of instruction word combinations in the instruction word sequence; each instruction word combination comprises a rising edge instruction word and a falling edge instruction word;

And when the comparison result indicates that the instruction words of the target data bits are different, determining that the line fault occurs in the instruction word line in the process of transmitting the instruction words, including:

When the comparison result shows that the instruction words with the target data bits are different, determining a target instruction word line corresponding to the target data bits in the instruction word lines with the number;

And determining that the target instruction word line has line faults in the process of transmitting the instruction word.

4. A method according to claim 3, wherein the combination of instruction words comprises a combination of row instruction words, a combination of clock cycle instruction words, and a combination of column instruction words, the combination of column instruction words comprising parity instruction words; the method further comprises the steps of:

And when the instruction word of the target data bit is the parity check instruction word, determining that an instruction word line corresponding to the parity check instruction word fails in the process of transmitting the instruction word.

5. The method of claim 4, wherein the row instruction word combination comprises a row rising edge instruction word and a row falling edge instruction word;

the clock period instruction word combination comprises a rising edge clock period instruction word and a falling edge clock period instruction word;

the column instruction word combination comprises a column rising edge instruction word and a column falling edge instruction word.

6. The method according to claim 2, wherein the method further comprises:

And when the comparison result shows that the instruction words of the target data bits are different, determining the positions of the target data bits in the instruction word sequences and the number of the instruction word lines corresponding to the target data bits.

7. The method according to claim 1, wherein the method further comprises:

sending a mode configuration instruction to a target memory, so that the target memory configures a test mode into a first register mode and a second register mode based on the mode configuration instruction;

the sending the instruction word sequence to the target memory through the instruction word line comprises the following steps:

When the target memory is in the first register mode, sending a sequence of instruction words to the target memory through an instruction word line;

The reading, by the target data interface, the first target instruction word sequence in the target memory includes:

the first sequence of target instruction words is read from the target memory based on a target data interface when the target memory is in the second register mode.

8. The method of claim 7, wherein the mode configuration instructions comprise a first mode configuration instruction and a second mode configuration instruction;

The configuring the test mode into the first register mode and the second register mode based on the mode configuration instruction includes:

initializing the instruction processing circuit;

configuring a test mode of the instruction processing circuit to be a first register mode based on the first mode configuration instruction;

and configuring a test mode of the instruction processing circuit to be a second register mode based on the second mode configuration instruction.

9. The method of claim 7, wherein the sending the sequence of instruction words to the target memory via the instruction word line to cause the target memory to perform instruction processing on the sequence of instruction words based on the instruction processing circuit to obtain the first sequence of target instruction words comprises:

transmitting an instruction word sequence to a target memory through an instruction word line so that the target memory shifts the instruction word sequence based on an instruction processing circuit to obtain a first target instruction word sequence; or alternatively

And transmitting at least two instruction word sequences to a target memory through an instruction word line so that the target memory compresses the at least two instruction word sequences, and shifting the compressed instruction word sequences based on an instruction processing circuit to obtain a first target instruction word sequence.

10. The method of claim 9, wherein the target algorithm comprises at least one of a compression algorithm and a shift algorithm; the target algorithm-based instruction processing is performed on the instruction word sequence to obtain a second target instruction word sequence, and the method comprises the following steps:

When an instruction word sequence is sent, shifting the instruction word sequence based on the shifting algorithm to obtain a second target instruction word sequence;

And when at least two instruction word sequences are transmitted, compressing the at least two instruction word sequences based on the compression algorithm, and shifting the compressed instruction word sequences based on the shifting algorithm to obtain a second target instruction word sequence.

11. The method of any one of claims 1 to 10, wherein the target memory is a high bandwidth memory; the target data interface is a data reading interface based on a target protocol standard.

12. A fault detection device for an instruction word line, the device comprising:

The instruction processing module is used for carrying out instruction processing on the instruction word sequence based on a target algorithm to obtain a second target instruction word sequence; the target algorithm is an algorithm matched with the instruction processing circuit;

13. The apparatus of claim 12, wherein the fault detection module is further configured to:

14. The apparatus of claim 13, wherein the number of instruction word lines is the same as the number of instruction word combinations in the sequence of instruction words; each instruction word combination comprises a rising edge instruction word and a falling edge instruction word;

the fault detection module is further configured to:

15. The apparatus of claim 14, wherein the combination of instruction words comprises a combination of row instruction words, a combination of clock cycle instruction words, and a combination of column instruction words, the combination of column instruction words comprising parity instruction words; the fault detection module is further configured to:

16. The apparatus of claim 15, wherein the row instruction word combination comprises a row rising edge instruction word and a row falling edge instruction word;

17. The apparatus of claim 13, wherein the fault detection module is further configured to:

18. The apparatus of claim 12, wherein the apparatus further comprises:

The mode configuration module is used for sending a mode configuration instruction to the target memory so that the target memory configures a test mode into a first register mode and a second register mode based on the mode configuration instruction;

the instruction sending module is further used for:

the data reading module is further configured to:

19. The apparatus of claim 18, wherein the mode configuration instructions comprise a first mode configuration instruction and a second mode configuration instruction;

The mode configuration module is further configured to:

initializing the instruction processing circuit;

20. The apparatus of claim 18, wherein the instruction sending module is further configured to:

21. The apparatus of claim 20, wherein the target algorithm comprises at least one of a compression algorithm and a shift algorithm; the instruction processing module is further configured to:

22. The apparatus according to any one of claims 12 to 21, wherein the target memory is a high bandwidth memory; the target data interface is a data reading interface based on a target protocol standard.

23. A computer device comprising a memory and a processor, the memory storing a computer program, characterized in that the processor implements the steps of the method of any one of claims 1 to 11 when the computer program is executed.

24. A computer readable storage medium, on which a computer program is stored, characterized in that the computer program, when being executed by a processor, implements the steps of the method of any of claims 1 to 11.

25. A computer program product comprising a computer program, characterized in that the computer program, when being executed by a processor, implements the steps of the method of any one of claims 1 to 11.