CN115102402A - Control method and circuit of double-clamping ZVS (zero voltage switching) buck-boost converter - Google Patents

Control method and circuit of double-clamping ZVS (zero voltage switching) buck-boost converter Download PDF

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Publication number
CN115102402A
CN115102402A CN202210555343.9A CN202210555343A CN115102402A CN 115102402 A CN115102402 A CN 115102402A CN 202210555343 A CN202210555343 A CN 202210555343A CN 115102402 A CN115102402 A CN 115102402A
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signal
circuit
voltage
switching tube
clamp
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Inventor
刘华吾
杨涛
王永生
王廷营
曹赟
赵瑞
丁星星
崔满超
胡家谕
朱轩锐
唐海瑞
胡东
宋亚龙
张吴涛
桂飞
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Shanghai Jieruizhao New Information Technology Co ltd
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Lianyungang Jierui Electronics Co Ltd
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Priority to CN202210555343.9A priority Critical patent/CN115102402A/en
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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/22—Conversion of dc power input into dc power output with intermediate conversion into ac
    • H02M3/24—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters
    • H02M3/28—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac
    • H02M3/325—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal
    • H02M3/335—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/33569—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only having several active switching elements
    • H02M3/33576—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only having several active switching elements having at least one active switching element at the secondary side of an isolation transformer
    • H02M3/33584—Bidirectional converters
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/0048—Circuits or arrangements for reducing losses
    • H02M1/0054—Transistor switching losses
    • H02M1/0058—Transistor switching losses by employing soft switching techniques, i.e. commutation of transistors when applied voltage is zero or when current flow is zero
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
    • H02M1/088—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters for the simultaneous control of series or parallel connected semiconductor devices
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/38—Means for preventing simultaneous conduction of switches
    • H02M1/385—Means for preventing simultaneous conduction of switches with means for correcting output voltage deviations introduced by the dead time
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/22—Conversion of dc power input into dc power output with intermediate conversion into ac
    • H02M3/24—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters
    • H02M3/28—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac
    • H02M3/325—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal
    • H02M3/335—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/33569—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only having several active switching elements
    • H02M3/33576—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only having several active switching elements having at least one active switching element at the secondary side of an isolation transformer
    • H02M3/33592—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only having several active switching elements having at least one active switching element at the secondary side of an isolation transformer having a synchronous rectifier circuit or a synchronous freewheeling circuit at the secondary side of an isolation transformer
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Dc-Dc Converters (AREA)

Abstract

The invention discloses a control method and a control circuit of a double-clamping ZVS buck-boost converter, which comprises a main power circuit of the double-clamping ZVS buck-boost converter and a converter control circuit, wherein the converter control circuit is connected into the converter control circuit based on the input voltage of the main power circuit, the voltage of a clamping capacitor and the drain-source voltage of a fourth switching tube, and outputs driving signals from a first switching tube to the fourth switching tube to control the switching of each switching tube in the converter so as to stabilize the output voltage of the converter. On one hand, the on-time of a clamping switch tube of the double-clamping converter is accurately controlled through the prefabricated data, so that the periodic initial current of the converter and the ZVS of the first switch tube are controlled, on the other hand, a clamping protection circuit is introduced, the reliability of the converter is improved, and the excessive on-time of the clamping switch tube under various extreme conditions is avoided; in addition, variable frequency control and maximum frequency limitation are automatically realized through a simple ZVS detection mode, and the conversion efficiency of the converter is improved.

Description

Control method and circuit of double-clamping ZVS (zero voltage switching) buck-boost converter
Technical Field
The invention belongs to the technical field of converters, and particularly relates to a control method and a control circuit of a double-clamping ZVS buck-boost converter.
Background
As shown in fig. 1, a double-clamped ZVS Buck-Boost converter (double-clamped ZVS Buck-Boost converter) is a high conversion efficiency, isolated converter, and was first proposed by VICOR corporation of america, and is disclosed in patent number US9083254B 1. The converter in fig. 1 mainly comprises first to fifth switching tubes, a transformer, a clamping capacitor, an output filter capacitor, an output load resistor and the like. The third switch tube can also be called a clamping switch tube. The first to fifth switching tubes additionally comprise parasitic diodes and parasitic capacitors of the switching tubes; the transformer additionally comprises its leakage inductance; the fifth switching tube, the filter capacitor, the output load resistor and other devices are connected to the secondary side of the transformer; the first to fourth switching tubes and the clamping capacitor are connected to the primary side of the transformer. The first switching tube, the second switching tube, the third switching tube and the fourth switching tube respectively form two half-bridge arms, and the primary side of the transformer is respectively connected to the middle points of the two half-bridge arms; and the input voltage source and the output capacitor are respectively connected with the two half-bridge arms in parallel.
Fig. 2A shows a typical waveform of a dual-clamp ZVS converter, in which the first and second switching tubes are complementarily turned on, and the third and fourth switching tubes are complementarily turned on; i is shown Lm Identifying an excitation current of the transformer; i is shown Lr Marking the total primary current of the transformer; as shown in fig. 2A, when the first and fourth switching tubes are turned on, the exciting inductance of the transformer stores energy, and the exciting current i Lm Linearly increasing, as shown by t in FIG. 2A 0 To t 1 A time period; when the second and third switching tubes are switched on, the fifth switching tube on the secondary side of the transformer is switched on, the energy of the transformer is transferred to the secondary side, the transformer is demagnetized, and the excitation current i Lm The linear decrease; at t 2 At the moment, the third switching tube is turned off, the fourth switching tube is turned on, the current of the transformer flows through the second switching tube and the third switching tube, and the current of the transformer basically keeps i r0 Unchanged, corresponding to t of said FIG. 2A 2 ～t 3 Stage, as such, said t 0 To t 3 Corresponding to a complete cycle of the dual-clamp ZVS buck-boost converter. In addition, the period start current i of the transformer shown in FIG. 2A r0 Is a small negative value, the cycle starts with a negative current i r0 The method has an important role, and is the key core of the control algorithm of the double-clamp ZVS converter. On the one hand, the appropriate negative current i r0 ZVS zero voltage switching-on of the first switching tube is facilitated, so that switching loss is reduced, and conversion efficiency of the converter is improved; on the other hand, if the current i r0 Too large a "negative" direction introduces additional conduction losses that affect the conversion efficiency of the converter. FIG. 2B shows the dual-clamp ZVS buck-boost converter under the same loadIn another possible operating waveform, the conduction time of the third switch tube is relatively long, thereby resulting in a period starting current i r0 The relatively large value further causes the conduction time of the first switching tube to be long, the switching frequency of the converter is low, and finally a series of negative problems that the conduction loss of the converter is large, the input ripple current is large and the like are caused. Further, the fig. 2A and 2B show that the cycle start current i r0 The switching frequency of the converter is further influenced by the switching-on time of the third switching tube, and under the light-load working condition of the converter, the switching frequency of the converter needs to be properly controlled, otherwise, the light-load switching frequency is extremely high, so that the converter is easy to fail; in addition, to achieve accurate control of the starting current, the dual-clamp ZVS buck-boost converter also requires effective control of the switching frequency of the converter. In summary, the key of the dual-clamp ZVS buck-boost converter is the control of the clamp switching tube and the converter switching frequency control. The US patent 9083254B1 proposes to indirectly control the clamp tube by means of driving of the fifth switch tube, and the scheme is relatively complex and is not beneficial to the realization of primary and secondary side voltage-resistant isolation.
Disclosure of Invention
In order to solve the technical problems, the invention provides a simple, reliable and effective solution, which not only can accurately control the magnitude of the negative current, but also can adaptively realize the proper control of the switching frequency of the converter, thereby realizing the efficient and reliable operation of the converter. The invention adopts the following technical scheme:
a control method of a double-clamping ZVS buck-boost converter is based on the fact that the converter comprises a first switching tube Q 1 To the fourth switching tube Q 4 A clamp capacitor C f The main power circuit 300 of the double-clamping ZVS buck-boost converter controls the first switch tube Q by executing the following steps 1 To the fourth switching tube Q 4 The output voltage of the dual-clamping ZVS buck-boost converter is further stabilized;
step 1, based on the input voltage v of the main power circuit 300 of the dual-clamp ZVS buck-boost converter in A clamp capacitor C f Voltage v of o And a fourth switching tube Q 4 Of the drain-source voltage v dsQ4 Respectively obtain the voltages v in Corresponding sampled signal v ins Voltage v o Corresponding sampled signal v os Voltage v dsQ4 Corresponding sampled signal v dss ；
Step 2, based on the sampling signal v ins Sampling signal v os Respectively obtain the first switch tube Q 1 On-time identification signal T 1 And a third switching tube Q 3 On-time identification signal T 2 ；
Step 3, based on the sampling signal v dss To obtain a fourth switching tube Q 4 Drain-source voltage zero-crossing signal v st ；
Step 4, based on the fourth switch tube Q 4 Drain-source voltage zero-crossing signal v st And a counting clock C lk To obtain a fourth switching tube Q 4 Pulse width ramp signal v of clamp ；
Step 5, based on the first switch tube Q 1 On-time identification signal T 1 And a third switching tube Q 3 On-time identification signal T 2 And a fourth switching tube Q 4 Pulse width ramp signal v of clamp Obtaining an on-time identification signal T 1 Corresponding high-low pulse width signal S 1 And on-time identification signal T 2 Corresponding high-low pulse width signal S 2 ；
Step 6, marking signal T based on opening time 1 Corresponding high-low pulse width signal S 1 And on-time identification signal T 2 Corresponding high-low pulse width signal S 2 And a fourth switching tube Q 4 Drain-source voltage zero-crossing signal v st To obtain the first switch tube Q 1 To the fourth switching tube Q 4 Is of the drive signal QS 1 ～QS 4 。
A circuit applied to a control method of a double-clamping ZVS buck-boost converter comprises a main power circuit 300 of the double-clamping ZVS buck-boost converter and a converter control circuit 311, wherein the main power circuit 300 of the double-clamping ZVS buck-boost converter comprises a primary side first switching tube Q 1 To the fourth switching tube Q 4 A clamp capacitor C f And a fifth secondary switch tube Q 5 And a synchronous rectification controller 301, a first switch tube Q 1 Source electrode of (1) and second switching tube Q 2 Is connected with the drain electrode of the first switch tube Q 1 Is connected to the input voltage v in Positive electrode of (1), second switching tube Q 2 Is connected to the input voltage v in Negative electrode of (2), third switching tube Q 3 Source electrode of (1) and fourth switching tube Q 4 Is connected to the drain of the third switching tube Q 3 Drain electrode of the capacitor is connected with a clamping capacitor C f Anode of (1), fourth switching tube Q 4 Source electrode of the capacitor C is connected with a clamping capacitor C f Based on the fifth switching tube Q, the synchronous rectification controller 301 5 The drain-source voltage of the fifth switching tube Q 5 Is of the drive signal QS 5 Controlling the fifth switch tube Q 5 The switch of (1); input voltage v of main power circuit 300 in A clamp capacitor C f Voltage v of o And a fourth switching tube Q 4 Of the drain-source voltage v dsQ4 The input signal is connected to the converter control circuit 311, and the converter control circuit 311 outputs a first switch tube Q 1 To the fourth switching tube Q 4 Is of the drive signal QS 1 ～QS 4 Controlling a first switch tube Q in a double-clamping ZVS buck-boost converter 1 To a fourth switching tube Q 4 And further stabilizing the output voltage of the dual-clamp ZVS buck-boost converter.
As a preferred technical solution of the present invention, the present invention further includes a capacitor C connected in parallel to two ends of the drain-source stage of the fourth switching tube Q4 zvs The method is used for controlling the period starting current of the double-clamping ZVS buck-boost converter.
As a preferred embodiment of the present invention, the converter control circuit 311 includes a first voltage sampling circuit 303, a feed-forward and output voltage closed loop circuit 304, a pulse width modulation circuit 305, a clamp protection circuit 306, a second voltage sampling circuit 307, a zero-crossing detection circuit 308, a pulse width ramp generation circuit 309, and an oscillator 310, and the input voltage v of the main power circuit 300 is in A clamp capacitor C f Voltage v of o Is connected to the first voltage sampling circuit 303Outputs a voltage v via the first voltage sampling circuit 303 in Corresponding sampled signal v ins And a voltage v o Corresponding sampled signal v os (ii) a Sampling signal v ins Sampling signal v os The feed-forward and output voltage closed-loop circuit 304 is connected, and the first switch tube Q is output through the feed-forward and output voltage closed-loop circuit 304 1 On-time identification signal T 1 And a third switching tube Q 3 On-time identification signal T 2 (ii) a The fourth switch tube Q 4 Of the drain-source voltage v dsQ4 Connected to a second voltage sampling circuit 307, and outputs a voltage v via the second voltage sampling circuit 307 dsQ4 Corresponding sampled signal v dss (ii) a Sampling signal v dss A zero-crossing detection circuit 308 is connected, and a zero-crossing signal v is output through the zero-crossing detection circuit 308 st (ii) a Zero crossing signal v st The pulse width ramp generating circuit 309 is connected, and the pulse width ramp generating circuit 309 outputs a pulse width ramp signal v under the action of the oscillator 310 clamp (ii) a Identification signal T 1 Identification signal T 2 And a pulse width ramp signal v clamp Connected to the pulse width modulation circuit 305, and the pulse width modulation circuit 305 outputs an on-time identification signal T 1 Corresponding high-low pulse width signal S 1 And an ON-time identification signal T 2 Corresponding high-low pulse width signal S 2 (ii) a Clamp protection circuit 306 is based on high-low pulse width signal S 1 High-low pulse width signal S 2 Zero crossing signal v st Output the first switch tube Q 1 To a fourth switching tube Q 4 Is driven by the driving signal QS 1 ～QS 4 。
In a preferred embodiment of the present invention, the feedforward and output voltage closed-loop circuit 304 includes a subtractor 501, a proportional-integral regulator 502, a feedforward parameter calculation module 504 and a table data module 503, and the sampling signal v is a signal os With a predetermined voltage reference v oref Outputs an error value E via a subtractor 501 er Error value E er Outputting a regulator output signal v via a proportional-integral regulator 502 er (ii) a Feedforward parameter calculation module 504 is based on regulator output signal v er Sampling signal v ins Sampling signal v os And the modified scaling factor k and the modified offset factor dT output by the table data module 503 output the first switch tube Q 1 On-time identification signal T 1 And a third switching tube Q 3 On-time identification signal T 2 (ii) a Table data module 503 outputs signal v based on regulator er And outputting the corresponding correction scaling coefficient k and the corresponding correction offset coefficient dT.
As a preferred technical solution of the present invention, the clamp protection circuit 306 includes a complementary circuit 701, a dead zone circuit 702, a complementary circuit 703, a dead zone circuit 704, an inverter device 705, an and gate device 706, and a and gate device 707, and the high-low pulse width signal S 1 The first and second switching tubes Q are output through the complementary circuit 701 and the dead zone circuit 702 in sequence 1 Is driven by the driving signal QS 1 And a second switching tube Q 1 Is of the drive signal QS 2 (ii) a The high-low pulse width signal S 2 Outputs a complementary signal S with a dead zone sequentially via a complementary circuit 703 and a dead zone circuit 704 3S And S 4S Complementary signal S 4S And said zero crossing signal v st A fourth switching tube Q for performing logical AND operation via a two-input AND gate device 707 4 Is driven by the driving signal QS 4 Said zero crossing signal v st The sum complementary signal S after inversion operation by the inverter device 705 3S The third switch tube Q is output by logical AND operation through the two-input AND gate device 706 3 Is driven by the driving signal QS 3 。
As a preferred technical solution of the present invention, the zero crossing detection circuit 308 includes a comparator Cp 1 And a resistor R 81 Resistance R 82 Presetting a reference voltage signal v F Via a resistance R 81 Connection comparator Cp 1 Of the sampling signal v dss Via a resistance R 82 Connection comparator Cp 1 Negative input of (2), comparator Cp 1 Output end of the fourth switch tube Q 4 Drain-source voltage zero-crossing signal v st 。
As a preferred technical solution of the present invention, the pulse width ramp generating circuit 309 includes an and gate device 900, a digital counter 901, and a maximum frequency limiting module 902, soThe zero crossing signal v st With the highest frequency limit signal T output by the highest frequency limit module 902 st Outputting a periodic set signal R via a two-input AND gate device 900 st The maximum frequency limit module 902 sets the signal R based on the period st And a counting clock C generated by the oscillator 310 lk Outputting the highest frequency limiting signal T st The digital counter 901 is based on a counting clock C generated by the oscillator 310 lk A periodic set signal R st Output pulse width ramp signal v c l amp 。
As a preferable technical solution of the present invention, the first switch tube Q 1 On-time identification signal T 1 And a third switching tube Q 3 On-time identification signal T 2 Calculated by the following formulas, respectively:
Figure BDA0003652187780000041
Figure BDA0003652187780000042
in the formula, k in Is an input voltage v in Inputting a resistance sampling voltage division coefficient corresponding to the output voltage in a first voltage sampling circuit; k is a radical of o Is a clamping capacitor C f Voltage v of o The first voltage sampling circuit inputs and outputs a resistance sampling voltage division coefficient corresponding to the voltage.
As a preferred embodiment of the present invention, the maximum frequency limiting module 902 includes a limiting threshold N Lm A module 1101, a digital comparator 1102, a value counter 1103, the value counter 1103 being based on said set signal R st And a counting clock C lk Outputting the count value v Trm A value, which is connected to the non-inverting input of the digital comparator 1102; limiting threshold N Lm Module 1101 minimum period output limit threshold N based on double-clamp ZVS buck-boost converter Lm And is connected to the inverting input terminal of the digital comparator 1102; output of digital comparator 1102Outputting a maximum frequency limiting signal T st 。
The invention has the beneficial effects that: the invention provides a control method and a control circuit of a double-clamping ZVS buck-boost converter, which comprises a main power circuit of the double-clamping ZVS buck-boost converter and a converter control circuit, wherein the converter control circuit is connected into the converter control circuit based on the input voltage of the main power circuit, the voltage of a clamping capacitor and the drain-source voltage of a fourth switching tube, and outputs driving signals from a first switching tube to the fourth switching tube to control the switching of each switching tube in the converter so as to stabilize the output voltage of the converter. On one hand, the on-time of a clamping switch tube of the double-clamping converter is accurately controlled through the prefabricated data, so that the periodic initial current of the converter and the ZVS of the first switch tube are controlled, on the other hand, a clamping protection circuit is introduced, the reliability of the converter is improved, and the excessive on-time of the clamping switch tube under various extreme conditions is avoided; in addition, variable frequency control and maximum frequency limitation are automatically realized through a simple ZVS detection mode, and the conversion efficiency of the converter is improved.
Drawings
FIG. 1 is a power circuit of a prior art dual clamp ZVS buck-boost converter;
FIG. 2A is a schematic diagram of a typical operating waveform of a prior art dual-clamp ZVS buck-boost converter;
FIG. 2B is a schematic diagram of another exemplary operating waveform of a prior art dual-clamp ZVS buck-boost converter;
fig. 3A is a main power circuit diagram of the dual-clamp ZVS buck-boost converter of the present embodiment;
fig. 3B is a structural diagram of a control device of the dual-clamp ZVS buck-boost converter of the present embodiment;
FIG. 4 is a diagram of the structure of the voltage sampling circuit of the present embodiment;
FIG. 5 is a diagram of the structure of the feedforward and output voltage closed-loop circuit of the present embodiment;
fig. 6 is a schematic diagram of an operating waveform of the dual-clamp ZVS buck-boost converter according to the present embodiment;
FIG. 7 is a diagram of the clamp protection circuit of the present embodiment;
fig. 8 is a structural diagram of a zero-cross detection circuit of the present embodiment;
fig. 9 is a structural diagram of a pulse width ramp generating circuit of the present embodiment;
fig. 10 is a schematic diagram of an operation waveform of the pulse width ramp generating circuit according to the present embodiment;
FIG. 11 is a block diagram of the maximum frequency limit module according to the present embodiment;
FIG. 12 is a schematic diagram of an operating waveform of the maximum frequency limiting module according to this embodiment;
fig. 13 is a steady state waveform diagram of the dual-clamp ZVS buck-boost converter of the present embodiment.
Detailed Description
The invention is further described below with reference to the accompanying drawings. The following examples are presented to enable one of ordinary skill in the art to more fully understand the present invention and are not intended to limit the invention in any way.
The application designs a control method and a circuit of a double-clamping ZVS buck-boost converter, which controls a first switching tube Q 1 To the fourth switching tube Q 4 And further stabilizing the output voltage of the dual-clamp ZVS buck-boost converter.
The control method of the double-clamping ZVS buck-boost converter is based on the fact that the double-clamping ZVS buck-boost converter comprises a first switching tube Q 1 To the fourth switching tube Q 4 A clamp capacitor C f The main power circuit 300 of the dual-clamp ZVS buck-boost converter, as shown in fig. 3A, the main power circuit 300 controls the first switch tube Q by performing the following steps 1 To the fourth switching tube Q 4 The output voltage of the dual-clamping ZVS buck-boost converter is further stabilized;
step 1, input voltage v of main power circuit 300 of buck-boost converter based on double-clamp ZVS in A clamp capacitor C f Voltage v of o And a fourth switching tube Q 4 Of the drain-source voltage v dsQ4 Respectively obtain voltages v through voltage sampling circuits in Corresponding sampled signal v ins Voltage v o Corresponding sampled signal v os Voltage v dsQ4 Corresponding sampled signal v dss ；
Step 2, based on the sampling signal v ins Sampling signal v os The first switch tube Q is obtained through the feedforward and output voltage closed loop circuit 304 respectively 1 On-time identification signal T 1 And a third switching tube Q 3 On-time identification signal T 2 ；
Step 3, based on the sampling signal v dss The fourth switching tube Q is obtained through the zero-crossing detection circuit 308 4 Drain-source voltage zero-crossing signal v st ；
Step 4, based on the fourth switch tube Q 4 Drain-source voltage zero-crossing signal v st And a count clock C lk The fourth switching tube Q is obtained through the pulse width ramp generating circuit 309 4 Pulse width ramp signal v of clamp ；
Step 5, based on the first switch tube Q 1 On-time identification signal T 1 And a third switching tube Q 3 On-time identification signal T 2 And a fourth switching tube Q 4 Pulse width ramp signal v of clamp The on-time flag signal T is obtained through the pulse width modulation circuit 305 1 Corresponding high-low pulse width signal S 1 And on-time identification signal T 2 Corresponding high-low pulse width signal S 2 ；
Step 6, marking signal T based on opening time 1 Corresponding high-low pulse width signal S 1 And on-time identification signal T 2 Corresponding high-low pulse width signal S 2 And a fourth switching tube Q 4 Drain-source voltage zero-crossing signal v st The first switch tube Q is obtained through the clamping protection circuit 306 1 To the fourth switching tube Q 4 Is of the drive signal QS 1 ～QS 4 。
The circuit based on the control method of the dual-clamp ZVS buck-boost converter comprises a dual-clamp ZVS buck-boost converter main power circuit 300 and a converter control circuit 311, as shown in fig. 3A and 3B, the clamp buck-boost converter main power circuit 300 comprises a primary side first switching tube Q 1 To the fourth switching tube Q 4 A clamp capacitor C f And a fifth secondary switch tube Q 5 And a synchronous rectification controller 301, a first switch tubeQ 1 Source electrode of (1) and second switching tube Q 2 Is connected with the drain electrode of the first switch tube Q 1 Is connected to the input voltage v in Positive electrode of (1), second switching tube Q 2 Is connected to the input voltage v in Negative electrode of (1), third switching tube Q 3 Source electrode of (1) and fourth switching tube Q 4 Is connected to the drain of the third switching tube Q 3 Drain electrode of the capacitor is connected with a clamping capacitor C f Anode of (1), fourth switching tube Q 4 Source electrode of (2) is connected with a clamping capacitor C f Based on the fifth switching tube Q, the synchronous rectification controller 301 5 The drain-source voltage of the fifth switching tube Q 5 Is of the drive signal QS 5 Controlling the fifth switch tube Q 5 The switch of (1); input voltage v of main power circuit 300 in A clamp capacitor C f Voltage v of o And a fourth switching tube Q 4 Of the drain-source voltage v dsQ4 The input signal is connected to the converter control circuit 311, and the converter control circuit 311 outputs a first switch tube Q 1 To the fourth switching tube Q 4 Is driven by the driving signal QS 1 ～QS 4 Controlling a first switch tube Q in a double-clamping ZVS buck-boost converter 1 To the fourth switching tube Q 4 The output voltage of the dual-clamping ZVS buck-boost converter is further stabilized; the capacitor Czvs is connected in parallel to the two ends of the drain-source stage of the fourth switching tube Q4 and used for controlling the period starting current of the double-clamping ZVS buck-boost converter.
The main power circuit 300 of the dual-clamp ZVS buck-boost converter of fig. 3A further includes a transformer T r Output capacitor C Ld And an output load R Ld Diode D shown in the figure 1 ～D 4 And a capacitor C 1 ～C 4 The first to fourth switching tubes Q 1 ～Q 4 Parasitic diodes and parasitic capacitances.
As shown in fig. 3B, the converter control circuit 311 includes a first voltage sampling circuit 303, a feed-forward and output voltage closed loop circuit 304, a pulse width modulation circuit 305, a clamp protection circuit 306, a second voltage sampling circuit 307, a zero-crossing detection circuit 308, a pulse width ramp generation circuit 309, and an oscillator 310, wherein the input power of the main power circuit 300 isPressure v in A clamp capacitor C f Voltage v of o Connected to the first voltage sampling circuit 303 and outputs a voltage v through the first voltage sampling circuit 303 in Corresponding sampled signal v ins And a voltage v o Corresponding sampled signal v os (ii) a Sampling signal v ins Sampling signal v os The feed-forward and output voltage closed-loop circuit 304 is connected, and the first switch tube Q is output through the feed-forward and output voltage closed-loop circuit 304 1 On-time identification signal T 1 And a third switching tube Q 3 On-time identification signal T 2 (ii) a The fourth switch tube Q 4 Of the drain-source voltage v dsQ4 Connected to a second voltage sampling circuit 307 and output a voltage v via the second voltage sampling circuit 307 dsQ4 Corresponding sampled signal v dss (ii) a Sampling signal v dss A zero-crossing detection circuit 308 is connected, and a zero-crossing signal v is output through the zero-crossing detection circuit 308 st (ii) a Zero crossing signal v st The pulse width ramp generating circuit 309 is connected, and the pulse width ramp generating circuit 309 outputs a pulse width ramp signal v under the action of the oscillator 310 clamp (ii) a Identification signal T 1 Identification signal T 2 And a pulse width ramp signal v clamp Connected to the pulse width modulation circuit 305, and the pulse width modulation circuit 305 outputs an on-time identification signal T 1 Corresponding high-low pulse width signal S 1 And an on-time identification signal T 2 Corresponding high-low pulse width signal S 2 (ii) a Clamp protection circuit 306 is based on high-low pulse width signal S 1 High-low pulse width signal S 2 Zero crossing signal v st Output the first switch tube Q 1 To the fourth switching tube Q 4 Is of the drive signal QS 1 ～QS 4 。
As shown in fig. 4, the first voltage sampling circuit 303 includes a resistor R 11 Resistance R 12 Capacitor C 11 And a resistor R 21 Resistance R 22 Capacitor C 21 Said input voltage v in Sequential path resistance R 11 And a resistor R 12 Ground, capacitor C 11 Parallel resistor R 12 Two ends, resistance R 11 Resistance R 12 As output terminal output samplingSample signal v ins Filter capacitor C 11 Parallel connection and sampling resistor R 12 Filtering is carried out, and the input voltage v in Via a resistor R 11 、R 12 Series voltage division generation sampling signal v ins (ii) a The clamp C f Voltage v of o Sequentially sampled resistors R 21 And a resistor R 22 Ground, capacitor C 21 Parallel resistor R 22 Two ends, resistance R 21 Resistance R 22 As an output terminal outputs a sampling signal v os Filter capacitor C 21 Parallel connection and voltage division R 22 Filtering to output voltage v o Via a sampling resistor R 21 、R 22 Series voltage division generation sampling signal v os ；
The second voltage sampling circuit 307 includes a resistor R 31 Resistance R 32 Depletion type MOS tube Q p Capacitor C 31 Said fourth switch tube Q 4 Of the drain-source voltage v dsQ4 Connecting resistor R 31 One terminal of (1), resistance R 31 The other end of the transistor is connected with a depletion type MOS transistor Q p Drain electrode of (1), depletion type MOS transistor Q p Via a resistor R 32 Connecting a predetermined voltage source v dg Depletion type MOS transistor Q p Via a capacitor C 31 And (4) grounding. The MOS transistor Q p The main purpose is to use the switching tube Q of the main power circuit 300 4 High voltage signal v of drain-source dsQ4 Converted into a low-voltage signal v dss To facilitate further processing by the control means 311. When the third capacitor C 31 Voltage v of dss Voltage lower than voltage source v dg Time-consuming depletion type MOS tube Q p Open, high voltage signal v dsQ4 Through MOS transistor Q p Capacitor C 31 Charging; when the capacitance C is 31 Voltage v of dss Higher than voltage source v dg While, MOS tube Q p When the voltage is cut off, the charging is finished, thereby realizing the high-voltage signal v dsQ4 Sampling is performed. Said voltage source v dg Typically 5V or 3.3V is chosen.
As shown in FIG. 5, the feedforward and output voltage closed-loop circuit 304 includes a subtractor 501, a proportional-integral regulator502. A feedforward parameter calculation module 504 and a table data module 503, the sampled signal v os With a predetermined voltage reference v oref Outputs an error value E via a subtractor 501 er Error value E er Outputting a regulator output signal v via a proportional-integral regulator 502 er (ii) a Feedforward parameter calculation module 504 is based on regulator output signal v er Sampling signal v ins Sampling signal v os And the corrected scaling factor k and the corrected bias factor dT output by the table data module 503 output the first switch tube Q 1 On-time identification signal T 1 And a third switching tube Q 3 On-time identification signal T 2 (ii) a Table data module 503 outputs signal v based on regulator er And outputting the corresponding correction scaling coefficient k and the corresponding correction offset coefficient dT. The coefficient is used for further adjusting the turn-on time of a third switching tube of the double-clamping ZVS buck-boost converter.
Based on the feedforward and output voltage closed-loop circuit 304, the T in this embodiment 1 And T 2 The formula of (c) is as follows:
Figure BDA0003652187780000081
Figure BDA0003652187780000082
in the formula k in And k o The resistance sampling division coefficients, k, corresponding to the input and output voltages of the first voltage sampling circuit are shown in Is an input voltage v in Inputting a resistance sampling voltage division coefficient corresponding to the output voltage in a first voltage sampling circuit; k is a radical of o Is a clamping capacitor C f Voltage v of o And a resistance sampling voltage division coefficient corresponding to the input and output voltage of the first voltage sampling circuit is input.
T shown in formula (1) as shown in FIG. 6 1 And T 2 Time period respectively indicates first switch tube Q of double-clamping ZVS buck-boost converter 1 On-time of and said conversionThird switch tube Q of device 3 Is the on-time of (i.e., t) shown in fig. 6 0 ～t 1 Time period and t 1 ～t 1_2 A time period. Further, t 0 ～t 1 In time period, a first switching tube Q of a double-clamping ZVS buck-boost converter 1 And a fourth switching tube Q 4 Simultaneously on, input voltage v in Applied to both ends of the transformer magnetizing inductance, the transformer magnetizing inductance current rises linearly as shown in the following formula (2),
Figure BDA0003652187780000091
at t 0 ～t 1 In a period of time, the clamping capacitor C f Voltage v of o Applied to two ends of the transformer, the exciting current of the transformer is linearly reduced,
Figure BDA0003652187780000092
wherein i in the formulae (2) and (3) Lm_t0 、i Lm_t1 And i Lm_t2 Respectively mean t 0 、t 1 And t 2 And exciting current of the corresponding transformer at the moment. Further, t is t to ensure that the transformer exciting current resets cycle by cycle 0 ～t 1 Within a time period and t 1 ～t 2 The variation of the exciting current of the time-interval transformer should be kept consistent, i.e. the variation
Figure BDA0003652187780000093
Thus, it is possible to prevent the occurrence of,
Figure BDA0003652187780000094
equation (5) shows a third switch tube Q of the dual-clamping ZVS buck-boost converter 3 The theoretical on-time of (c). It is to be noted that the formula (5) shows theoretical calculationAnd (3) the third switching tube is controlled by only formula (5) in the actual converter operation, and the system is easy to disperse and unstable, so that the theoretical value needs to be corrected and protected. The correction and protection scheme is realized in a table look-up mode shown in the figure 5 of the invention, namely, a formula (6)
Figure BDA0003652187780000095
Where k and dT are the correction scaling factor and the correction offset factor, respectively. It can be seen from the above formula (6) that the modification and protection scheme of the present invention is to avoid the third switch tube Q 3 Too long turn-on time; as shown in FIG. 6, the on-time of the third switch tube is t 1 To t 2 Nearby, however, the t 2 The time point is difficult to obtain accurately, so that the embodiment of the invention uses Q 3 The theoretical shutdown point of (1) 'moves forward' to t 1_2 Point in time, said t 1_2 The time point is obtained from said equation (6). It is to be noted that Q is defined as 3 To t 1_2 The normal operation of the double-clamping ZVS buck-boost converter is not influenced because the primary current of the transformer can continuously flow through the Q 3 The turned-on parasitic body diode freewheels. Further, the correction coefficients k and dT in the formula (6) need to be adjusted according to the working state of the dual-clamp ZVS buck-boost converter, that is, the working condition of the output load, so as to avoid that the Q is subjected to a heavy load 3 The efficiency of the converter is affected by too short on-time of the switching tube. Referring to fig. 5, the present application is in accordance with the output value v of the regulator 502 er The table look-up 503 adjusts the correction coefficients k and dT shown in equation (6) in real time. The data in the lookup table 503 can be obtained by an off-line measurement mode, and the value ranges of the modified proportionality coefficients k and dT are 0.8-0.9 and 0.0-0.1 respectively under a normal condition.
In summary, the first switch tube Q 1 On-time identification signal T 1 And a third switching tube Q 3 On-time identification signal T 2 Calculated by the following formulas, respectively:
Figure BDA0003652187780000101
Figure BDA0003652187780000102
in the formula, k in Is an input voltage v in Inputting a resistance sampling voltage division coefficient corresponding to the output voltage in a first voltage sampling circuit; k is a radical of o Is a clamping capacitor C f Voltage v of o And a resistance sampling voltage division coefficient corresponding to the input and output voltage of the first voltage sampling circuit is input.
Further, referring to fig. 3A, the fourth switch Q of the main power converter circuit 300 according to the exemplary embodiment of the present invention 4 Is connected in parallel with a ZVS capacitor Czvs across the drain-source stage of the converter for controlling the cycle start current of the converter, see i in fig. 6 r0 . The ZVS capacitor C zvs The capacitance value of the capacitor is determined according to the input and output operating conditions of the specific double-clamping ZVS buck-boost converter, and is generally between 1nF and 100 nF. Referring to FIG. 6, at t 1_2 Third switching tube Q of time-of-day double-clamping ZVS buck-boost converter 3 Turn off, primary side current i of transformer Lr Warp Q 3 Body diode freewheeling at t 1_3 At the moment, the primary side current i of the transformer Lr Zero crossing, excitation inductance and leakage inductance of the transformer and a third and fourth switching tube Q of a double-clamping ZVS buck-boost converter 3 、Q 4 Parasitic capacitance C of 3 、C 4 And the external ZVS capacitor Czvs starts to resonate, during which the primary current i of the transformer Lr The approximate expression is as shown in formula (7),
Figure BDA0003652187780000103
in the formula C oss_34 ＝C 3 +C 4 +C zvs . It can be seen from the equation (7) that the double-clamped cycle start voltage can be controlled by the external ZVS capacitor CzvsFlow to reliably realize the first switch tube Q of the converter 1 The ZVS of (1) is turned on, and the conversion efficiency is improved.
As shown in fig. 7, the clamp protection circuit protects the control of the clamp switching transistor Q3 in an extreme case, the clamp protection circuit 306 includes a complementary circuit 701, a dead zone circuit 702, a complementary circuit 703, a dead zone circuit 704, an inverter device 705, an and gate device 706, and a and gate device 707, and an input signal of the clamp protection circuit is the pulse width output signal S of the pulse width modulation circuit 305 shown in fig. 3B 1 、S 2 And the output zero-crossing signal v of the zero-crossing detection circuit 308 st (ii) a The output signals of the clamping protection circuit are the first to the fourth switching tubes Q of the double-clamping main power circuit shown in figure 3B 1 ～Q 4 Is of the drive signal QS 1 To QS 4 . The high-low pulse width signal S 1 The first and second switching tubes Q are output through the complementary circuit 701 and the dead zone circuit 702 in sequence 1 Is of the drive signal QS 1 And a second switching tube Q 1 Is of the drive signal QS 2 (ii) a The high-low pulse width signal S 2 Outputs a complementary signal S with a dead zone sequentially via a complementary circuit 703 and a dead zone circuit 704 3S And S 4S Complementary signal S 4S And said zero crossing signal v st A fourth switching tube Q for performing logical AND operation via a two-input AND gate device 707 4 Is of the drive signal QS 4 Said zero crossing signal v st The sum complementary signal S after inversion operation by the inverter device 705 3S The third switch tube Q is output by logical AND operation through the two-input AND gate device 706 3 Is of the drive signal QS 3 . The purpose of the clamping protection circuit is to ensure that the third switching tube, namely the clamping switching tube Q of the double-clamping ZVS buck-boost converter 3 Is of the drive signal QS 3 Must be only at zero crossing signal v st After turning to low level, thereby ensuring that the clamping switch tube Q 3 Under any problem or transient working condition, the normal work of the converter cannot be influenced by 'excessive' switching-on.
As shown in FIG. 8, the zero crossing detection circuit 308 includes a comparator Cp 1 And a resistor R 81 And a resistor R 82 Presetting a reference voltageSignal v F Via a resistance R 81 Connection comparator Cp 1 Of the sampling signal v dss Via a resistance R 82 Connection comparator Cp 1 Of the negative input terminal, comparator Cp 1 Output end of the fourth switch tube Q 4 Drain-source voltage zero-crossing signal v st . The voltage sampling signal v dss The drain-source stage voltage of the fourth switch tube from the dual-clamp ZVS buck-boost converter generated by the 307 module in FIG. 3B is converted into a voltage signal by a high-voltage signal through a sampling circuit. The reference voltage signal v F Voltage source v generally as shown in figure 4 dg Correlation, usually v F ＝(0.1～0.4)v dg . When v is st When the voltage is high, the fourth switch tube Q is marked 4 Voltage v of the drain-source stage dsQ4 The voltage crosses zero. The zero-crossing identification signal v st The clamp protection circuit for the block 306 of fig. 3B on the one hand and the block 309 of fig. 3B on the other hand are used to determine the switching frequency of the dual-clamp ZVS buck-boost converter.
Further, as shown in fig. 9, the pulse width ramp generating circuit according to the embodiment of the present invention is based on the zero-crossing flag signal v st An automatic frequency conversion mechanism is introduced, the pulse width ramp generating circuit 309 comprises an and gate device 900, a digital counter 901 and a maximum frequency limiting module 902, and the embodiment of the invention applies the invention according to a zero-crossing identification signal v st Introducing an automatic frequency conversion mechanism, the zero-crossing signal v st With the highest frequency limit signal T output by the highest frequency limit module 902 st Outputting a periodic set signal R via a two-input AND gate device 900 st The maximum frequency limiting module 902 sets the signal R based on the period st And a counting clock C generated by the oscillator 310 lk Outputting the highest frequency limiting signal T st The digital counter 901 is based on a counting clock C generated by the oscillator 310 lk And a periodic set signal R st Output pulse width ramp signal v clamp . Each time the count clock arrives, the counter performs an add 1 operation. Periodic set signal R st When the counting value is temporarily cleared, a new counting period is started. The clock signal C lk From the oscillator 31 shown0 is generated. The set signal R st Zero crossing identification signal v st And said 902 block highest frequency limit signal T st Obtained after logical and operation via two-input and gate 900. FIG. 10 shows a schematic waveform of the pulse width ramp generating circuit block, the maximum frequency limiting signal T st At the time of passing through T Lm After the time, the voltage is turned to high level; when zero crossing the identification signal v st After the signal is inverted to high level, the signal R is periodically set st Inverting high level followed by pulse width ramp signal v clamp And immediately clearing to start the next period. The T is Lm Time, i.e. the minimum cycle time, T, of the corresponding converter Lm The value can be determined according to the specific working condition of the converter, and is usually about 1 mu s. As can be seen from fig. 10, in the embodiment of the present invention, the drain-source voltage v of the fourth switching tube of the dual-clamp ZVS buck-boost converter is sampled in real time dsQ4 Modulating the operating frequency of the converter in real time; at the same time, the maximum frequency limit module 902 of FIG. 9 limits the maximum operating frequency of the converter to ensure reliable operation.
Further, fig. 11 is a block diagram of an implementation of the maximum frequency limiting module shown in fig. 9, where the maximum frequency limiting module 902 includes a limiting threshold N Lm A module 1101, a digital comparator 1102, a value counter 1103, the value counter 1103 being based on said set signal R st And a counting clock C lk Outputting the count value v Trm A value, which is connected to the non-inverting input of the digital comparator 1102; limiting threshold N Lm Module 1101 minimum period output limit threshold N based on double-clamp ZVS buck-boost converter Lm And is connected to the inverting input terminal of the digital comparator 1102; the output terminal of the digital comparator 1102 outputs the highest frequency limit signal T st . Said N is Lm I.e. T as shown in FIG. 10 Lm Clock in time C lk A numerical value. The input signal of the module shown in FIG. 11 is a counting clock C lk A periodic set signal R st The output signal being a maximum frequency limiting signal T st . Clock C for each counting lk At the arrival, the numerical counter 1103 performs an add-1 operation, each time resetting the signal R st At high level, the count value of the second digital counter is cleared and resetThe counting is started anew. When the second counter outputs a signal v Trm Count value of to the limit threshold value T Lm While, the digital comparator 1102 is flipped, the frequency limiting signal T st Turning to a high level; when the count value is reset by the signal R st Set to zero, the frequency limiting signal T st And likewise toggles low. Referring to fig. 12, the signal T is limited due to the frequency st Even if the zero-crossing identification signal v shown in fig. 9 exists st First with the highest frequency limiting signal T shown st When the signal arrives, the AND gate module 900 of FIG. 9 guarantees the periodic set signal R st Limiting the signal T at zero-crossing and frequency as shown st Are all high and then are inverted, thereby finally limiting the ramp signal v shown in fig. 9 clamp I.e. the maximum operating frequency of the entire converter is limited to ensure reliable operation.
The invention designs a control method and a circuit of a double-clamping ZVS buck-boost converter, which can accurately control the switching-on time of a clamping switch tube of the double-clamping ZVS buck-boost converter on one hand, thereby controlling the periodic initial current of the converter and the ZVS of a first switch tube, and on the other hand, additionally introduce a clamping protection circuit, improve the reliability of the converter, and avoid the excessive switching-on of the clamping switch tube under various extreme conditions; in addition, the frequency conversion control is automatically realized through a simple ZVS detection mode, and the conversion efficiency of the converter is improved.
Further, according to the embodiment of the invention, a double-clamping ZVS buck-boost converter prototype is built, and a steady-state waveform is measured, as shown in FIG. 13, it can be seen that the embodiment of the invention can effectively realize reliable control of the converter.
Although the present invention has been described with reference to the preferred embodiments, it is not intended to be limited thereto. Those skilled in the art can make various changes and modifications without departing from the spirit and scope of the invention.
Although the present invention has been described in detail with reference to the foregoing embodiments, it will be apparent to those skilled in the art that modifications may be made to the embodiments described in the foregoing detailed description, or equivalent changes may be made in some of the features of the embodiments described above. The equivalent structures made by using the contents of the specification and the attached drawings of the invention are directly or indirectly applied to other related technical fields, and are all within the protection scope of the patent of the invention.

Claims (10)

1. A control method of a double-clamping ZVS buck-boost converter is characterized by comprising the following steps: based on the fact that the first switch tube Q is included 1 To the fourth switching tube Q 4 A clamp capacitor C f The main power circuit 300 of the double-clamping ZVS buck-boost converter controls the first switch tube Q by executing the following steps 1 To a fourth switching tube Q 4 The output voltage of the dual-clamping ZVS buck-boost converter is further stabilized;
step 1, input voltage v of main power circuit 300 of buck-boost converter based on double-clamp ZVS in A clamp capacitor C f Voltage v of o And a fourth switching tube Q 4 Of the drain-source voltage v dsQ4 Respectively obtain the voltages v in Corresponding sampled signal v ins Voltage v o Corresponding sampled signal v os Voltage v dsQ4 Corresponding sampled signal v dss ；
Step 2, based on the sampling signal v ins Sampling signal v os Respectively obtain the first switch tube Q 1 On-time identification signal T 1 And a third switching tube Q 3 On-time identification signal T 2 ；
Step 3, based on the sampling signal v dss To obtain a fourth switching tube Q 4 Drain-source voltage zero crossing signal v st ；
Step 4, based on the fourth switch tube Q 4 Drain-source voltage zero-crossing signal v st And a counting clock C lk To obtain a fourth switching tube Q 4 Pulse width ramp signal v of clamp ；
Step 5, based on the first switch tube Q 1 On-time identification signal T 1 And a third switching tube Q 3 On-time identification signal ofT 2 And a fourth switching tube Q 4 Pulse width ramp signal v of clamp Obtaining an on-time identification signal T 1 Corresponding high-low pulse width signal S 1 And on-time identification signal T 2 Corresponding high-low pulse width signal S 2 ；
Step 6, marking signal T based on opening time 1 Corresponding high-low pulse width signal S 1 And on-time identification signal T 2 Corresponding high-low pulse width signal S 2 And a fourth switching tube Q 4 Drain-source voltage zero-crossing signal v st Obtaining a first switch tube Q 1 To the fourth switching tube Q 4 Is of the drive signal QS 1 ～QS 4 。
2. A circuit applied to the control method of the dual-clamp ZVS buck-boost converter of claim 1, wherein: the dual-clamp ZVS buck-boost converter comprises a dual-clamp ZVS buck converter main power circuit 300 and a converter control circuit 311, wherein the dual-clamp ZVS buck converter main power circuit 300 comprises a primary side first switching tube Q 1 To the fourth switching tube Q 4 A clamp capacitor C f And a fifth switching tube Q on the secondary side 5 And a synchronous rectification controller 301, a first switch tube Q 1 Source electrode of (1) and second switching tube Q 2 Is connected to the drain of the first switching tube Q 1 Is connected to the input voltage v in Positive electrode of (1), the second switching tube Q 2 Is connected to the input voltage v in Negative electrode of (1), third switching tube Q 3 Source electrode of (1) and fourth switching tube Q 4 Is connected to the drain of the third switching tube Q 3 Drain electrode of the capacitor is connected with a clamping capacitor C f Anode of (1), fourth switching tube Q 4 Source electrode of the capacitor C is connected with a clamping capacitor C f Based on the fifth switching tube Q, the synchronous rectification controller 301 5 The drain-source voltage of the fifth switch tube Q 5 Is of the drive signal QS 5 To control the fifth switch tube Q 5 The switch of (2); input voltage v of main power circuit 300 in A clamp capacitor C f Voltage v of o And a fourth switching tube Q 4 Of the drain-source voltage v dsQ4 Switching in converter control as input signalThe control circuit 311, the inverter control circuit 311 outputs a first switch tube Q 1 To the fourth switching tube Q 4 Is of the drive signal QS 1 ～QS 4 Controlling a first switch tube Q in a double-clamping ZVS buck-boost converter 1 To the fourth switching tube Q 4 And further stabilizing the output voltage of the dual-clamp ZVS buck-boost converter.
3. The control circuit of a dual-clamp ZVS buck-boost converter as claimed in claim 2, wherein: also comprises a fourth switch tube Q connected in parallel 4 Capacitor C across the drain-source stage zvs The method is used for controlling the period starting current of the double-clamping ZVS buck-boost converter.
4. The control circuit of a dual-clamp ZVS buck-boost converter as claimed in claim 2, wherein: the converter control circuit 311 comprises a first voltage sampling circuit 303, a feed-forward and output voltage closed loop circuit 304, a pulse width modulation circuit 305, a clamp protection circuit 306, a second voltage sampling circuit 307, a zero-crossing detection circuit 308, a pulse width ramp generation circuit 309 and an oscillator 310, wherein the input voltage v of the main power circuit 300 in A clamp capacitor C f Voltage v of o Connected to the first voltage sampling circuit 303, and outputs a voltage v via the first voltage sampling circuit 303 in Corresponding sampled signal v ins And a voltage v o Corresponding sampled signal v os (ii) a Sampling signal v ins Sampling signal v os The feed-forward and output voltage closed-loop circuit 304 is connected, and the first switch tube Q is output through the feed-forward and output voltage closed-loop circuit 304 1 On-time identification signal T 1 And a third switching tube Q 3 On-time identification signal T 2 (ii) a The fourth switch tube Q 4 Of the drain-source voltage v dsQ4 Connected to a second voltage sampling circuit 307, and outputs a voltage v via the second voltage sampling circuit 307 dsQ4 Corresponding sampled signal v dss (ii) a Sampling signal v dss A zero-crossing detection circuit 308 is connected, and a zero-crossing signal v is output through the zero-crossing detection circuit 308 st (ii) a Zero crossing signal v st Access pulse width rampA ramp generating circuit 309, the pulse width ramp generating circuit 309 outputs a pulse width ramp signal v under the action of the oscillator 310 clamp (ii) a Identification signal T 1 Identification signal T 2 And a pulse width ramp signal v clamp Connected to the pulse width modulation circuit 305, and the pulse width modulation circuit 305 outputs an on-time identification signal T 1 Corresponding high-low pulse width signal S 1 And an on-time identification signal T 2 Corresponding high-low pulse width signal S 2 (ii) a Clamp protection circuit 306 is based on high-low pulse width signal S 1 High-low pulse width signal S 2 Zero crossing signal v st Output the first switch tube Q 1 To a fourth switching tube Q 4 Is of the drive signal QS 1 ～QS 4 。
5. The control circuit of the dual-clamp ZVS buck-boost converter of claim 3, wherein: the feedforward and output voltage closed-loop circuit 304 comprises a subtractor 501, a proportional-integral regulator 502, a feedforward parameter calculation module 504 and a table data module 503, wherein the sampling signal v os With a predetermined voltage reference v oref Outputs an error value E via a subtractor 501 er Error value E er Outputting a regulator output signal v via a proportional-integral regulator 502 er (ii) a Feedforward parameter calculation module 504 is based on regulator output signal v er Sampling signal v ins Sampling signal v os And the modified scaling factor k and the modified offset factor dT output by the table data module 503 output the first switch tube Q 1 On-time identification signal T 1 And a third switching tube Q 3 On-time identification signal T 2 (ii) a Table data module 503 outputs signal v based on regulator er And outputting the corresponding correction scaling coefficient k and the corresponding correction offset coefficient dT.
6. The control circuit of a dual-clamp ZVS buck-boost converter as claimed in claim 3, wherein: the clamp protection circuit 306 comprises a complementary circuit 701, a dead zone circuit 702, a complementary circuit 703, a dead zone circuit 704, an inverter device 705, an AND gate device 706, and an AND gate device 707High and low pulse width signal S 1 The first and second switching tubes Q are output through the complementary circuit 701 and the dead zone circuit 702 in sequence 1 Is of the drive signal QS 1 And a second switching tube Q 1 Is of the drive signal QS 2 (ii) a The high-low pulse width signal S 2 Outputs a complementary signal S with a dead zone sequentially via a complementary circuit 703 and a dead zone circuit 704 3S And S 4S Complementary signal S 4S And said zero crossing signal v st A fourth switching tube Q for performing logical AND operation via a two-input AND gate device 707 4 Is driven by the driving signal QS 4 Said zero crossing signal v st The sum complementary signal S after inversion operation by the inverter device 705 3S The third switch tube Q is output by logical AND operation through the two-input AND gate device 706 3 Is of the drive signal QS 3 。
7. The control circuit of a dual-clamp ZVS buck-boost converter as claimed in claim 3, wherein: the zero crossing detection circuit 308 includes a comparator Cp 1 Resistance R 81 Resistance R 82 Presetting a reference voltage signal v F Via a resistance R 81 Connection comparator Cp 1 Of the sampling signal v dss Via a resistance R 82 Connection comparator Cp 1 Of the negative input terminal, comparator Cp 1 Output end of the fourth switch tube Q 4 Drain-source voltage zero-crossing signal v st 。
8. The control circuit of a dual-clamp ZVS buck-boost converter as claimed in claim 3, wherein: the pulse width ramp generating circuit 309 comprises an and gate device 900, a digital counter 901, a maximum frequency limiting module 902, and the zero-crossing signal v st With the highest frequency limit signal T output by the highest frequency limit module 902 st Outputting a periodic set signal R through a two-input AND gate device 900 st The maximum frequency limit module 902 sets the signal R based on the period st And a counting clock C generated by the oscillator 310 lk Outputting the highest frequency limiting signal T st Digital counter 901 is based on the signal generated by oscillator 310Counting clock C lk A periodic set signal R st Output pulse width ramp signal v clamp 。
9. The control circuit of a dual-clamp ZVS buck-boost converter as claimed in claim 5, wherein: the first switch tube Q 1 On-time identification signal T 1 And a third switching tube Q 3 On-time identification signal T 2 Calculated by the following formulas, respectively:
Figure FDA0003652187770000031
Figure FDA0003652187770000032
in the formula, k in Is an input voltage v in Inputting a resistance sampling voltage division coefficient corresponding to the output voltage in a first voltage sampling circuit; k is a radical of o Is a clamping capacitor C f Voltage v of o And a resistance sampling voltage division coefficient corresponding to the input and output voltage of the first voltage sampling circuit is input.
10. The control circuit of a dual-clamp ZVS buck-boost converter as claimed in claim 8, wherein: the maximum frequency limit module 902 includes a limit threshold N Lm A module 1101, a digital comparator 1102, a value counter 1103, the value counter 1103 being based on said set signal R st And a counting clock C lk Outputting the count value v Trm The value, which is switched into the non-inverting input of the digital comparator 1102; limiting threshold value N Lm Module 1101 minimum period output limit threshold N based on double-clamp ZVS buck-boost converter Lm And is connected to the inverting input terminal of the digital comparator 1102; the output terminal of the digital comparator 1102 outputs the highest frequency limit signal T st 。
CN202210555343.9A 2022-05-19 2022-05-19 Control method and circuit of double-clamping ZVS (zero voltage switching) buck-boost converter Pending CN115102402A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116365837A (en) * 2022-12-16 2023-06-30 南京航空航天大学 Control method and control circuit of isolated four-tube Buck-Boost converter

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116365837A (en) * 2022-12-16 2023-06-30 南京航空航天大学 Control method and control circuit of isolated four-tube Buck-Boost converter
CN116365837B (en) * 2022-12-16 2023-11-17 南京航空航天大学 Control method and control circuit of isolated four-tube Buck-Boost converter

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