CN115101637A - Light emitting diode epitaxial wafer and preparation method thereof - Google Patents

Light emitting diode epitaxial wafer and preparation method thereof Download PDF

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CN115101637A
CN115101637A CN202211023097.9A CN202211023097A CN115101637A CN 115101637 A CN115101637 A CN 115101637A CN 202211023097 A CN202211023097 A CN 202211023097A CN 115101637 A CN115101637 A CN 115101637A
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layer
growth
structural
emitting diode
gan
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CN115101637B (en
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张彩霞
印从飞
程金连
胡加辉
金从龙
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Jiangxi Zhao Chi Semiconductor Co Ltd
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Jiangxi Zhao Chi Semiconductor Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/025—Physical imperfections, e.g. particular concentration or distribution of impurities
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/22—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of inorganic material, other than metallic material
    • C23C16/30—Deposition of compounds, mixtures or solid solutions, e.g. borides, carbides, nitrides
    • C23C16/301—AIII BV compounds, where A is Al, Ga, In or Tl and B is N, P, As, Sb or Bi
    • C23C16/303—Nitrides
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/44—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
    • C23C16/52—Controlling or regulating the coating process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02538—Group 13/15 materials
    • H01L21/0254—Nitrides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0062—Processes for devices with an active region comprising only III-V compounds
    • H01L33/0066—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound
    • H01L33/007—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound comprising nitride compounds

Abstract

The invention provides a light-emitting diode epitaxial wafer and a preparation method thereof, belonging to the technical field of diode semiconductors. The light emitting diode epitaxial wafer comprises a three-dimensional structure layer, wherein the three-dimensional structure layer comprises a first structure layer, a second structure layer and a third structure layer which are sequentially stacked; the first structural layer comprises In alternately stacked periodically a N 1‑a Layer and Al b Ga 1‑b N layers; the second structural layer is Al c N 1‑c A layer; the third structural layer comprises GaN layers and Al which are periodically and alternately stacked m Ga 1‑m N layer of Al m Ga 1‑m The V/III and growth speed of the N layer are higher than those of the GaN layer; al (aluminum) b Ga 1‑b The growth pressure of the N layer is the same as that of the second structural layer, and the growth pressure of the third structural layer is between In a N 1‑a Layer and Al b Ga 1‑b The growth pressure of the N layer. The light emitting diode can improve the light emitting efficiency and the antistatic capacity of the light emitting diode.

Description

Light emitting diode epitaxial wafer and preparation method thereof
Technical Field
The invention belongs to the technical field of diode semiconductors, and particularly relates to a light emitting diode epitaxial wafer and a preparation method thereof.
Background
At present, GaN-based light emitting diodes have been widely applied to the solid-state lighting field and the display field, and have attracted more and more attention due to their excellent characteristics of large forbidden bandwidth, high electron saturation drift velocity, high temperature resistance, high power capacity, and the like. GaN-based leds have been produced industrially and are widely used in backlights, illuminations, landscape lamps, etc.
Because the substrate and the GaN material have serious lattice mismatch, in order to reduce the degree of lattice mismatch, an MOCVD method is generally adopted to grow an intrinsic GaN layer at a growth temperature of 1000 ℃ to 1050 ℃. However, when the intrinsic GaN-containing layers grown in the prior art are merged in the three-dimensional islands, dislocation defects with high density are generated at the interface, the original crystal sequence of GaN is seriously damaged due to the dislocation defects, and some dislocation defects extend from the bottom layer of the LED epitaxial structure to the light emitting region of the quantum well, so that non-radiative recombination of hole and electron pairs is caused, and the light emitting efficiency of the light emitting diode is reduced. In addition, dislocation defects can cause the increase of leakage channels of the LED device, and the antistatic capability of the LED device is weakened.
Disclosure of Invention
In order to solve the technical problems, the invention provides a light emitting diode epitaxial wafer and a preparation method thereof, through the structure of a three-dimensional structure layer structure, dislocation defects generated by merging of three-dimensional islands when the three-dimensional structure layer grows can be reduced, the generated dislocations are twisted and annihilated, and the dislocation defects are reduced to extend to a quantum well, so that the light emitting efficiency and the antistatic capability of the light emitting diode are improved.
In one aspect, the invention provides a light emitting diode epitaxial wafer, which comprises a three-dimensional structure layer, wherein the three-dimensional structure layer comprises a first structure layer, a second structure layer and a third structure layer which are sequentially stacked; the first structural layer comprises In alternately stacked periodically a N 1-a Layer and Al b Ga 1-b N layers; the second structural layer is Al c N 1-c A layer; the third structural layer comprises GaN layers and Al which are periodically and alternately stacked m Ga 1-m N layer of said Al m Ga 1-m The V/III and growth speed of the N layer are greater than those of the GaN layer; the Al is b Ga 1-b The growth pressure of the N layer is the same as that of the second structural layer, and the growth pressure of the third structural layer is between that of the In layer a N 1-a Layer and the Al b Ga 1-b The growth pressure of the N layer.
Compared with the prior art, the invention has the beneficial effects that: first, In is grown under high pressure a N 1-a The layer is more beneficial to axial three-dimensional island growth than a GaN material, In atoms are larger and can generate tensile stress, and the stress is opposite to that generated by warping of the bottom layer, so that warping can be relieved, and the three-dimensional islands are more uniformly distributed; growing Al at low pressure b Ga 1-b The N layer is beneficial to two-dimensional transverse growth, and the Al atoms are smaller and more beneficial to two-dimensional transverse growth. Next, Al is grown on the first structural layer c N 1-c Layer, Al is added in the state that three-dimensional islands are just merged c N 1-c The layer reduces defects, causing dislocations that are generated when the three-dimensional islands merge with the islands to be distorted and annihilated. Thirdly, Al m Ga 1-m V/III of the N layer is greater than V/III of the GaN layer, so that Al m Ga 1-m The N layer is easy to grow longitudinally, and the GaN layer is easy to grow transversely; and Al m Ga 1-m The growth speed of the N layer is greater than that of the GaN layer, and the larger ratio of the transverse growth rate to the longitudinal growth rate can enable the contact interface to generate an inclination angle to cause the extension dislocation to bend so as to further inhibit the dislocation from extending upwards; and GaN layer is Ga-polar, Al m Ga 1-m The N layer has N polarity, so that the N layer and the N layer are attached more tightly to inhibit the generation of dislocation defects.
Preferably, the In a N 1-a The growth atmosphere of the layer is nitrogen, and the Al b Ga 1-b The growth atmosphere of the N layer is hydrogen, and the growth atmosphere of the second structural layer and the growth atmosphere of the third structural layer are mixed gas of nitrogen and hydrogen.
Preferably, the growth temperature of the first structural layer is increased in a stepwise manner with a period, and the growth temperature of the second structural layer is between the growth temperatures of the first structural layer and the third structural layer.
Preferably, a single In the first structural layer a N 1-a The thickness of the layer is 5 nm-10 nm, single Al b Ga 1-b The thickness of the N layer is 10 nm-20 nm, and the stacking period number is 30-40; in the second structure layer, the thickness of the AlN layer is 1 nm-3 nm; the thickness of a single GaN layer in the third structural layer is 3-5nm, and the thickness of a single Al layer m Ga 1-m The thickness of the N layer is 20 nm-30 nm, and the periodicity is 10-20;
preferably, the In a N 1-a Layer of the Al b Ga 1-b N layer of the Al c N 1-c Layer and the Al m Ga 1-m A, b, c and m in the N layers respectively satisfy: a is more than or equal to 0.2 and less than or equal to 0.5, b is more than or equal to 0.1 and less than or equal to 0.3, c is more than or equal to 0.1 and less than or equal to 0.2, and m is more than or equal to 0.1 and less than or equal to 0.2.
Preferably, the light emitting diode epitaxial wafer further comprises a substrate, a buffer layer, an intrinsic GaN layer, an n-type semiconductor layer, a multi-quantum well layer, an electronic barrier layer and a p-type semiconductor layer, wherein the buffer layer, the three-dimensional structure layer, the intrinsic GaN layer, the n-type semiconductor layer, the multi-quantum well layer, the electronic barrier layer and the p-type semiconductor layer are sequentially laminated on the substrate.
Preferably, the multiple quantum well layer comprises InGaN quantum well layers and GaN quantum barrier layers which are alternately stacked periodically, and the number of stacking periods is 3-15.
In another aspect, the present invention provides a method for preparing the light emitting diode epitaxial wafer, where the method includes:
providing a substrate;
sequentially growing a buffer layer and a three-dimensional structure layer on the substrateForming a first semiconductor layer by the intrinsic GaN layer and the n-type semiconductor layer; the three-dimensional structure layer is of a composite structure and comprises a first structure layer, a second structure layer and a third structure layer which are sequentially stacked; the first structural layer comprises In alternately stacked periodically a N 1-a Layer and Al b Ga 1-b N layers; the second structural layer is Al c N 1-c A layer; the third structural layer comprises GaN layers and Al which are periodically and alternately stacked m Ga 1-m N layer of said Al m Ga 1-m The V/III and growth speed of the N layer are greater than those of the GaN layer; the Al is b Ga 1-b The growth pressure of the N layer is the same as that of the second structural layer, and the growth pressure of the third structural layer is between that of the In layer a N 1-a Layer and the Al b Ga 1-b The growth pressure of the N layer;
growing a multi-quantum well layer on the third structural layer;
and sequentially growing an electronic barrier layer and a p-type semiconductor layer on the multi-quantum well layer to form a second semiconductor layer, thereby finishing the preparation of the light-emitting diode epitaxial wafer.
Compared with the prior art, the invention has the beneficial effects that: first, In is grown by high pressure growth a N 1-a The layer is more beneficial to axial three-dimensional island growth than a GaN material, In atoms are larger and can generate tensile stress, and the stress is opposite to that generated by warping of the bottom layer, so that warping can be relieved, and the three-dimensional islands are more uniformly distributed; and by growing Al at low pressure b Ga 1-b The N layer is beneficial to two-dimensional transverse growth, and the Al atoms are smaller and more beneficial to two-dimensional transverse growth. Next, Al is grown on the first structural layer c N 1-c Layer of Al added in the state of just merged three-dimensional islands c N 1-c The layer reduces defects, causing dislocations that are generated when the three-dimensional islands merge with the islands to be distorted and annihilated. Thirdly, growing Al m Ga 1-m V/III of the N layer is greater than V/III of the GaN layer, so that Al m Ga 1-m The N layer is easy to grow longitudinally, and the GaN layer is easy to grow transversely; and Al m Ga 1-m The growth rate of the N layer is greater than that of the GaN layer, and the growth rate is largerThe ratio of the long rate to the longitudinal growth rate is such that the contact interface exhibits a tilt angle that causes bending of the extended dislocations to further inhibit dislocation propagation upward; and GaN layer is Ga-polar, Al m Ga 1-m The N layer has N polarity, so that the N layer and the N layer are attached more tightly to inhibit dislocation defects.
Preferably, the In a N 1-a The growth atmosphere of the layer is nitrogen, and the Al b Ga 1-b The growth atmosphere of the N layer is hydrogen, and the growth atmosphere of the second structural layer and the growth atmosphere of the third structural layer are mixed gas of nitrogen and hydrogen.
Preferably, the growth temperature of the first structural layer is increased in a stepwise manner with a period, and the growth temperature of the second structural layer is between the growth temperatures of the first structural layer and the third structural layer.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings required to be used in the embodiments or the prior art description will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings may be obtained according to these drawings without inventive labor.
FIG. 1 is a schematic view of a prior art light emitting diode epitaxial slice plane;
fig. 2 is a schematic view of an epitaxial fragment plane of a light emitting diode provided in embodiment 1 of the present invention;
fig. 3 is a schematic flow chart of a method for manufacturing an epitaxial wafer of a light emitting diode according to embodiment 1 of the present invention.
Description of reference numerals:
10-a substrate;
21-buffer layer, 22-three-dimensional structure layer, 221-first structure layer, 2211-In a N 1-a Layer, 2212-Al b Ga 1-b N layer, 222-second structure layer, 223-third structure layer, 2231-GaN layer, 2232-Al layer m Ga 1-m An N layer, a 23-intrinsic GaN layer, a 24-N type semiconductor layer;
30-multiple quantum well layer, 31-InGaN quantum well layer and 32-GaN quantum barrier layer;
41-electron blocking layer, 42-p type semiconductor layer.
Detailed Description
Reference will now be made in detail to embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the drawings are exemplary and intended to be illustrative of the embodiments of the present invention, and should not be construed as limiting the invention.
Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or to implicitly indicate the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the embodiments of the present invention, "a plurality" means two or more unless specifically limited otherwise.
Comparative example
As shown in fig. 1, the present comparative example employs a related art light emitting diode epitaxial wafer including a substrate 10, and a buffer layer 21, an intrinsic GaN layer 23, an n-type semiconductor layer 24, a multi-quantum well layer 30, an electron blocking layer 41, and a p-type semiconductor layer 42 sequentially deposited on the substrate 10. The light emitting diode epitaxial wafer of the comparative example was subjected to XRD testing, and the light emitting diode epitaxial wafer was fabricated into a 10mil by 24mil LED chip by a chip fabrication process, and the antistatic ESD pass yield and luminance were tested by a related testing instrument, and the specific test results are shown in table 1.
Example 1
As shown in fig. 2, the present embodiment provides a light emitting diode epitaxial wafer, which includes a substrate 10, and a buffer layer 21, a three-dimensional structure layer 22, an intrinsic GaN layer 23, an n-type semiconductor layer 24, a multi-quantum well layer 30, an electron blocking layer 41, and a p-type semiconductor layer 42 sequentially deposited on the substrate 10.
In this embodiment, the substrate 10 is made of sapphire; the sapphire substrate has the advantages of mature preparation process, low price, easy cleaning and treatment and good stability at high temperature. Of course, other embodiments may employ one of a silicon dioxide sapphire composite, a silicon liner material, a silicon carbide material, a gallium nitride material, or a zinc oxide material.
The buffer layer 21 in this embodiment is made of AlGaN and has a thickness of 30 nm. The buffer layer is mainly used for providing seed crystals, relieving lattice mismatch of the substrate and the epitaxial layer and improving the lattice quality of the light-emitting diode.
The three-dimensional structure layer 22 in this embodiment is a composite structure, and includes a first structure layer 221, a second structure layer 222, and a third structure layer 223 stacked in sequence. Specifically, the first structure layer 221 includes In alternately stacked periodically a N 1-a Layer 2211 and Al b Ga 1-b N layer 2212, preferably, a is more than or equal to 0.2 and less than or equal to 0.5, and b is more than or equal to 0.1 and less than or equal to 0.3; in a N 1-a The growth atmosphere of the layer is nitrogen, Al b Ga 1-b The growth atmosphere of the N layer is hydrogen; single In a N 1-a Layer thickness 8nm, single Al b Ga 1-b The thickness of the N layer was 15nm and the number of stacking cycles was 35. The second structure layer 222 is Al c N 1-c Layer, preferably, 0.1. ltoreq. c.ltoreq.0.2, Al c N 1-c The atmosphere of layer growth is mixed gas of nitrogen and hydrogen; the AlN layer had a thickness of 3 nm. The third structure layer 223 includes GaN layers 2231 and Al alternately stacked periodically m Ga 1-m The N layer 2232, the growth atmosphere of which is a mixed gas of nitrogen and hydrogen; the thickness of the single GaN layer in the third structural layer is 4nm, and the single Al layer m Ga 1-m The thickness of the N layer is 25nm, preferably, 0.1 m 0.2, and the number of stacking periods is 15. Further, Al m Ga 1-m V/III of N layer and growth rate are higher than those of GaN layer, so that Al m Ga 1-m The N layer is easy to grow longitudinally, and the GaN layer is easy to grow transversely; and Al m Ga 1-m The growth speed of the N layer is greater than that of the GaN layer, and the larger ratio of the transverse growth rate to the longitudinal growth rate can enable the contact interface to generate an inclination angle to cause the extension dislocation to bend so as to further inhibit the dislocation from extending upwards; and GaN layer is Ga-polar, Al m Ga 1-m The N layers are N-polar to make the two bondedThe compaction serves to suppress the generation of dislocation defects. And, the GaN layer is Ga-polar, Al m Ga 1-m The N layer has N polarity, so that the N layer and the N layer are attached more tightly to inhibit the generation of dislocation defects.
Note that, Al in the three-dimensional structure layer in this embodiment is referred to b Ga 1-b Growth pressure of N layer and Al c N 1-c The growth pressure of the layer is the same, and is specifically in the range of 100 Torr-200 Torr; and the growth pressure of the third structural layer is between In a N 1-a Layer and Al b Ga 1-b Growth pressure of N layer, In particular a N 1-a The layer is at 300Torr to 500Torr, and the third structural layer is at 200Torr to 300 Torr. By growing Al under high pressure and nitrogen atmosphere c N 1-c The layer is more favorable to axial three-dimensional island growth than the GaN material, and In atom is great can produce tensile stress, and the stress that produces with the bottom warpage is opposite, can alleviate the warpage and make three-dimensional island distribution more even, especially epitaxial wafer edge portion. Then growing Al under the conditions of low pressure and hydrogen atmosphere b Ga 1-b The N layer is beneficial to two-dimensional transverse growth, and the Al atoms are smaller and more beneficial to two-dimensional transverse growth. Al (Al) c N 1-c Layer and Al b Ga 1-b The N layers are repeatedly grown in a laminated mode, the three-dimensional islands grow longitudinally and then transversely, the three-dimensional islands are combined together repeatedly, the growth temperature rises along with the period along with the continuous growth of the three-dimensional islands, the mobility of Ga atoms is increased when the three-dimensional islands are combined finally, the generated defects are few, and the dislocation and the accumulated stress are relatively few due to the three-dimensional island combination method.
The thickness of the intrinsic GaN layer 23 in this embodiment is 400 nm.
The n-type semiconductor layer 24 in the present embodiment has a thickness of 2 μm, and is doped with Si element for supplying electrons.
Among them, the multiple quantum well layer 30 in the present embodiment includes InGaN quantum well layers 31 and GaN quantum barrier layers 32 alternately stacked periodically. Specifically, the thickness of a single InGaN quantum well layer is 3nm, the thickness of a single GaN quantum barrier layer is 10nm, and the number of stacking cycles is 10.
The electron blocking layer 41 in this embodiment is a periodic structure formed by alternately stacking AlGaN and InGaN materials, the thickness of a single AlGaN material layer is 6nm, the thickness of a single InGaN material layer is 6nm, and the stacking period number is 8. The electron blocking layer is mainly used for blocking electrons and preventing the electrons from overflowing.
The p-type semiconductor layer 42 in this embodiment has a thickness of 4nm, is doped with Mg, and has a doping concentration range of 1 × 10 17 cm -3 ～1×10 19 cm -3 For providing a cavity.
The three-dimensional structure layer with the design reduces the generation of bottom layer stress, defects generated by merging of three-dimensional islands when the three-dimensional structure layer grows, and twists and annihilates generated dislocations to obtain the light-emitting diode epitaxial wafer with low dislocation density and good lattice quality, so that the defects are reduced to extend to a quantum well to influence the light-emitting efficiency, and the antistatic capacity of the light-emitting diode is enhanced.
Further, as shown in fig. 3, a method for preparing the light emitting diode epitaxial wafer of the present embodiment is provided, where the method includes the following steps:
s01, providing a sapphire substrate.
Specifically, the growth temperature of the reaction chamber is controlled to be 1000-1200 ℃, the growth pressure is controlled to be 200-600 Torr, and the rotation speed of the graphite base is controlled to be 500-1200 r/min. The sapphire substrate is annealed at a high temperature for 5-8 min in a hydrogen atmosphere, and particles and oxides on the surface of the sapphire substrate are cleaned.
And S02, growing a buffer layer on the sapphire substrate.
In this embodiment, the thickness of the buffer layer is 30nm, and the buffer layer is made of AlGaN. Specifically, the growth temperature of the reaction chamber is controlled to be 500-700 ℃, the growth pressure is controlled to be 200-400 Torr, the rotation speed of the graphite base is controlled to be 500-1200 r/min, ammonia gas is introduced to serve as an N source, TMGa is introduced to serve as a Ga source, and TMAl is introduced to serve as an Al source in the atmosphere of mixed gas of nitrogen and hydrogen.
And S03, sequentially arranging a first structural layer, a second structural layer and a third structural layer on the buffer layer to form a three-dimensional structural layer.
Wherein the first structural layer comprises In alternately stacked periodically a N 1-a Layer and Al b Ga 1-b And N layers. Specifically, the growth pressure of the reaction chamber is controlled to be 300 Torr-500 Torr, the rotation speed of the graphite base is set to be 500 r/min-1200 r/min, the growth temperature is set to be 800 ℃ -850 ℃, nitrogen is introduced as carrier gas, hydrogen is not introduced, ammonia is introduced as N source, TMIn is introduced as In source to grow In with the thickness of 8nm a N 1-a A layer; then setting the growth pressure of the reaction chamber to be 100 Torr-200 Torr, closing the nitrogen and introducing hydrogen, closing the In source, introducing TMGa as Ga source, introducing TMAL as Al source, and growing to be 15nmAl b Ga 1- b And N layers. Then repeating the laminated growth for 35 periods, wherein the process conditions except the growth temperature are consistent with those of the first period, the growth temperature is increased in a step-by-step manner along with the growth period, and the growth temperature of the last growth period is 1000-1050 ℃.
Wherein the second structural layer is Al c N 1-c And (3) a layer. Specifically, the growth pressure of the reaction chamber is controlled to be 100 Torr-200 Torr, the rotation speed of the graphite base is set to be 500 r/min-1200 r/min, the growth temperature is 1050 ℃ -1070 ℃, the mixed gas of nitrogen and hydrogen is introduced as carrier gas, ammonia is introduced as N source, TMAL is introduced as Al source, and Al with the growth thickness of 3nm is grown c N 1-c And (3) a layer.
Wherein the third structural layer comprises GaN layers and Al which are periodically and alternately stacked m Ga 1-m And N layers. Specifically, the growth pressure of the reaction chamber is controlled to be 200 Torr-300 Torr, the rotation speed of the graphite base is set to be 500 r/min-1200 r/min, the growth temperature is 1070 ℃ to 1100 ℃, the mixed gas of nitrogen and hydrogen is introduced as carrier gas, ammonia is introduced as N source, TMGa is introduced as Ga source, V/III is controlled to be 200-400, the length speed is 0.3 nm/sec-0.5 nm/sec, and a GaN layer with the thickness of 4nm is grown. Then introducing Al source, continuing to introduce Ga source, controlling the V/III to be 800-1000, the growth speed to be 1-2 nm/sec, and growing Al with the thickness of 25nm m Ga 1-m And N layers. Then in the same wayUnder the growth process, the stacking growth is repeated for 15 periods.
And S04, growing an intrinsic GaN layer on the third structural layer.
Specifically, the growth temperature of the reaction chamber is controlled to be 1100-1150 ℃, the growth pressure is controlled to be 100-500 Torr, the rotation speed of the graphite base is controlled to be 500-1200 r/min, ammonia gas is introduced to serve as an N source, mixed gas of nitrogen and hydrogen is introduced to serve as carrier gas, TMGa is introduced to serve as a Ga source, and the intrinsic GaN layer with the thickness of 400nm is grown.
And S05, growing an n-type semiconductor layer on the intrinsic GaN layer.
Specifically, the growth temperature of the reaction chamber is controlled to be 1100-1150 ℃, the growth pressure is controlled to be 100-500 Torr, the rotation speed of the graphite base is set to be 500-1200 r/min, ammonia gas is introduced to be used as an N source, mixed gas of nitrogen and hydrogen is introduced to be used as carrier gas, TMGa is introduced to be used as a Ga source, SiH is introduced to be used as a Ga source 4 As N-type doping, an N-type semiconductor layer was grown to a thickness of 2 μm.
And S06, growing a multi-quantum well layer on the n-type semiconductor layer.
Wherein the multiple quantum well layer comprises InGaN quantum well layers and GaN quantum barrier layers which are periodically and alternately stacked. Specifically, in the process of growing the multi-quantum well layer, the growth pressure of the reaction chamber is controlled to be 100 Torr-500 Torr, and the rotating speed of the graphite base is set to be 600 r/min-1000 r/min. Further, firstly, controlling the growth temperature of the reaction chamber to be 700-800 ℃, introducing ammonia gas as an N source, introducing nitrogen gas as a carrier gas, introducing TEGa as a Ga source, introducing TMIn as an In source, and growing an InGaN quantum well layer with the thickness of 3 nm; secondly, controlling the growth temperature of the reaction chamber to be 800-900 ℃, closing the In source, introducing mixed gas of nitrogen and hydrogen as carrier gas, introducing TEGa as Ga source, and growing a GaN quantum barrier layer with the thickness of 10 nm; the stack growth was then repeated for 10 cycles under the same growth process.
And S07, growing an electron barrier layer on the multi-quantum well layer.
The electron blocking layer is a periodic structure formed by alternately laminating and growing AlGaN and InGaN materials. Specifically, firstly, controlling the growth temperature of a reaction chamber to be 900-1000 ℃ and the growth pressure to be 100-500 Torr, setting the rotation speed of a graphite base to be 600-1000 r/min, introducing ammonia gas as an N source, introducing TEGa as a Ga source, introducing TMAl as an Al source, growing an AlGaN material layer with the thickness of 6nm, secondly, closing the Al source, continuously introducing the Ga source, opening the In source, and growing an InGaN material layer with the thickness of 6 nm; the stack growth was then repeated for 8 cycles under the same growth process.
And S08, growing a p-type semiconductor layer on the electron blocking layer.
Concretely, firstly, the growth temperature of the reaction chamber is controlled to be 800-1000 ℃, the growth pressure is controlled to be 100-300 Torr, the rotation speed of the graphite plate is set to be 800-1200 r/min, ammonia gas is introduced to be used as an N source, TEGa is introduced to be used as a Ga source, and CP is introduced to be used as a Ga source 2 Mg acts as a p-type dopant, so that a Mg-doped p-type semiconductor layer with a thickness of 4nm is grown.
The LED epitaxial wafer of this embodiment was used to test XRD, and the LED epitaxial wafer was fabricated into a 10mil by 24mil LED chip by a chip fabrication process, and the antistatic ESD pass yield and luminance were tested by a related testing apparatus, and the specific test results are shown in table 1.
Example 2
The present embodiment is different from embodiment 1 in that: single In of the first structural layer a N 1-a Layer thickness of 5nm, single Al b Ga 1-b The thickness of the N layer is 10nm, and the stacking period number is 30; al of the second structural layer c N 1-c The thickness of the layer is 1 nm; the thickness of the single GaN layer of the third structural layer is 3nm, and the single Al layer m Ga 1-m The thickness of the N layer was 20nm and the number of stacking cycles was 10. The number of stacking periods of the multiple quantum well layer was 3. The number of stacking cycles of the electron blocking layer was 3.
The LED epitaxial wafer of this embodiment was used to test XRD, and the LED epitaxial wafer was fabricated into a 10mil by 24mil LED chip by a chip fabrication process, and the antistatic ESD pass yield and luminance were tested by a related testing apparatus, and the specific test results are shown in table 1.
Example 3
The difference between the present embodiment and embodiment 1 is thatIn the following steps: single In of the first structural layer a N 1-a Layer thickness 10nm, single Al b Ga 1-b The thickness of the N layer is 20nm, and the stacking period number is 40; al of the second structural layer c N 1-c The thickness of the layer is 2 nm; the thickness of the single GaN layer of the third structural layer is 5nm, and the single Al layer m Ga 1-m The thickness of the N layer was 30nm and the number of stacking cycles was 20. The number of stacking periods of the multiple quantum well layer was 15. The number of stacking cycles of the electron blocking layer was 15.
The LED epitaxial wafer of this embodiment was used to test XRD, and the LED epitaxial wafer was fabricated into a 10mil by 24mil LED chip by a chip fabrication process, and the antistatic ESD pass yield and luminance were tested by a related testing apparatus, and the specific test results are shown in table 1.
Table 1: comparative table of test results of each example and comparative example
Figure 674755DEST_PATH_IMAGE001
As can be seen from table 1, the present invention adds a three-dimensional structure layer, which includes a first structure layer, a second structure layer, and a third structure layer stacked in sequence; the first structural layer comprises In alternately stacked periodically a N 1-a Layer and Al b Ga 1-b N layers; the second structural layer is Al c N 1-c A layer; the third structural layer comprises GaN layers and Al which are periodically and alternately stacked m Ga 1-m N layer of Al m Ga 1-m The V/III and growth speed of the N layer are higher than those of the GaN layer; al (Al) b Ga 1-b The growth pressure of the N layer is the same as that of the second structure layer, and the growth pressure of the third structure layer is between In a N 1-a Layer and Al b Ga 1-b The growth pressure of the N layer. Further, In a N 1-a The growth atmosphere of the layer is nitrogen, Al b Ga 1-b The growth atmosphere of the N layer is hydrogen, and the growth atmosphere of the second structural layer and the growth atmosphere of the third structural layer are mixed gas of nitrogen and hydrogen. The growth temperature of the first structural layer is increased in a step-like manner with the period, and the growth temperature of the second structural layer is increasedBetween the growth temperature of the first structural layer and the third structural layer. Single In the first structural layer a N 1-a The thickness of the layer is 5 nm-10 nm, single Al b Ga 1-b The thickness of the N layer is 10 nm-20 nm, and the stacking period number is 30-40; in the second structure layer, the thickness of the AlN layer is 1 nm-3 nm; the thickness of the single GaN layer in the third structural layer is 3-5nm, and the single Al layer m Ga 1-m The thickness of the N layer is 20 nm-30 nm, and the periodicity is 10-20. Through the above arrangement, the following effects are achieved:
1. growing In under high pressure and nitrogen atmosphere a N 1-a The layer is more beneficial to axial three-dimensional island growth than a GaN material, In atoms are larger and can generate tensile stress, and the stress is opposite to that generated by warping of the bottom layer, so that warping can be relieved, and the three-dimensional islands are more uniformly distributed; growth of Al at low pressure and in a hydrogen atmosphere b Ga 1-b The N layer is beneficial to two-dimensional transverse growth, and the Al atoms are smaller and more beneficial to two-dimensional transverse growth.
2. Growing Al on the first structural layer c N 1-c Layer, Al is added in the state that three-dimensional islands are just merged c N 1-c The layer reduces defects, causing dislocations that are generated when the three-dimensional islands merge with the islands to be distorted and annihilated.
3、Al m Ga 1-m V/III of the N layer is greater than V/III of the GaN layer, so that Al m Ga 1-m The N layer is easy to grow longitudinally, and the GaN layer is easy to grow transversely; and Al m Ga 1-m The growth speed of the N layer is greater than that of the GaN layer, and the larger ratio of the transverse growth rate to the longitudinal growth rate can enable the contact interface to generate an inclination angle to cause the extension dislocation to bend so as to further inhibit the dislocation from extending upwards;
4. GaN layer of Ga-polar, Al m Ga 1-m The N layer has N polarity, so that the N layer and the N layer are attached more tightly to inhibit the generation of dislocation defects.
In conclusion, the three-dimensional structure layer designed by the invention can enable the test results of XRD (002) and XRD (102) to be smaller so as to have better lattice quality, obviously reduce dislocation, and further improve antistatic ability and luminous brightness.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents and improvements made within the spirit and principle of the present invention are intended to be included within the scope of the present invention.

Claims (10)

1. The light-emitting diode epitaxial wafer is characterized by comprising a three-dimensional structure layer, wherein the three-dimensional structure layer comprises a first structure layer, a second structure layer and a third structure layer which are sequentially stacked; the first structural layer comprises In alternately stacked periodically a N 1-a Layer and Al b Ga 1-b N layers; the second structural layer is Al c N 1-c A layer; the third structural layer comprises GaN layers and Al which are periodically and alternately stacked m Ga 1-m N layer of said Al m Ga 1-m The V/III and growth speed of the N layer are greater than those of the GaN layer; the Al is b Ga 1- b The growth pressure of the N layer is the same as that of the second structural layer, and the growth pressure of the third structural layer is between that of the In layer a N 1-a Layer and the Al b Ga 1-b The growth pressure of the N layer.
2. The light emitting diode epitaxial wafer as claimed In claim 1, wherein the In is a N 1-a The growth atmosphere of the layer is nitrogen, the Al b Ga 1-b The growth atmosphere of the N layer is hydrogen, and the growth atmosphere of the second structural layer and the growth atmosphere of the third structural layer are mixed gas of nitrogen and hydrogen.
3. The light emitting diode epitaxial wafer of claim 1, wherein the growth temperature of the first structural layer is increased in a stepwise manner with a period, and the growth temperature of the second structural layer is between the growth temperatures of the first structural layer and the third structural layer.
4. The light emitting diode epitaxial wafer of claim 1, wherein the first structural layerIn (b) is a single In a N 1-a The thickness of the layer is 5 nm-10 nm, single Al b Ga 1-b The thickness of the N layer is 10 nm-20 nm, and the stacking period number is 30-40; in the second structure layer, the thickness of the AlN layer is 1 nm-3 nm; the thickness of a single GaN layer in the third structural layer is 3-5nm, and the thickness of a single Al layer m Ga 1-m The thickness of the N layer is 20 nm-30 nm, and the periodicity is 10-20.
5. The light-emitting diode epitaxial wafer according to claim 1, wherein the In is a N 1-a Layer of the Al b Ga 1-b N layer of the Al c N 1-c Layer and the Al m Ga 1-m A, b, c and m in the N layers respectively satisfy: a is more than or equal to 0.2 and less than or equal to 0.5, b is more than or equal to 0.1 and less than or equal to 0.3, c is more than or equal to 0.1 and less than or equal to 0.2, and m is more than or equal to 0.1 and less than or equal to 0.2.
6. The light-emitting diode epitaxial wafer according to any one of claims 1 to 5, further comprising a substrate, a buffer layer, an intrinsic GaN layer, an n-type semiconductor layer, a multi-quantum well layer, an electron blocking layer and a p-type semiconductor layer, wherein the buffer layer, the three-dimensional structure layer, the intrinsic GaN layer, the n-type semiconductor layer, the multi-quantum well layer, the electron blocking layer and the p-type semiconductor layer are sequentially laminated on the substrate.
7. The light emitting diode epitaxial wafer of claim 6, wherein the multiple quantum well layer comprises InGaN quantum well layers and GaN quantum barrier layers which are alternately stacked periodically, and the number of stacking periods is 3-15.
8. A preparation method of the light-emitting diode epitaxial wafer as claimed in any one of claims 1 to 7, wherein the preparation method comprises the following steps:
providing a substrate;
growing a buffer layer, a three-dimensional structure layer, an intrinsic GaN layer and an n-type semiconductor layer on the substrate in sequence to form a first semiconductor layer; wherein, the three-dimensional structure layer is a composite structure and comprises first structures which are sequentially stackedA structural layer, a second structural layer and a third structural layer; the first structural layer comprises In alternately stacked periodically a N 1-a Layer and Al b Ga 1-b N layers; the second structural layer is Al c N 1-c A layer; the third structural layer comprises GaN layers and Al which are periodically and alternately stacked m Ga 1-m N layer of said Al m Ga 1-m The V/III and growth speed of the N layer are greater than those of the GaN layer; the Al is b Ga 1-b The growth pressure of the N layer is the same as that of the second structural layer, and the growth pressure of the third structural layer is between that of the In layer a N 1-a Layer and the Al b Ga 1-b The growth pressure of the N layer;
growing a multi-quantum well layer on the third structural layer;
and sequentially growing an electronic barrier layer and a p-type semiconductor layer on the multi-quantum well layer to form a second semiconductor layer, thereby finishing the preparation of the light-emitting diode epitaxial wafer.
9. The production method according to claim 8, wherein the In a N 1-a The growth atmosphere of the layer is nitrogen, and the Al b Ga 1-b The growth atmosphere of the N layer is hydrogen, and the growth atmosphere of the second structural layer and the growth atmosphere of the third structural layer are mixed gas of nitrogen and hydrogen.
10. The method of claim 8, wherein the growth temperature of the first structural layer is increased in a periodic stepwise manner, and the growth temperature of the second structural layer is between the growth temperatures of the first structural layer and the third structural layer.
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