CN115101434A - Packaging structure manufacturing method and chip anti-warping device - Google Patents

Abstract

The invention discloses a manufacturing method of a packaging structure and a chip warping prevention device, wherein the manufacturing method comprises the following steps: providing a test substrate and a test stacking chip set to form a test packaging structure; carrying out reflow soldering process on the test packaging structure; testing the welding performance of the packaging structure after the reflow soldering process is tested; and when the welding performance fails, providing a chip anti-warping device and a product packaging structure which is the same as the test packaging structure, fixedly loading the product packaging structure in the chip anti-warping device, and then carrying out reflow soldering process. The method can effectively prevent the lower chip from warping to a greater extent in the reflow soldering process, reduce the risk of soldering failure between the upper chip and the lower chip, and improve the 3D packaging soldering quality.

Description

Packaging structure manufacturing method and chip anti-warping device

technical field

The invention relates to the technical field of semiconductor packaging, in particular to a method for manufacturing a packaging structure and a device for preventing warping of a chip.

Background technique

TSV (Through Silicon Via, through-silicon via technology) technology is a high-density packaging technology, which is gradually replacing the current wire bonding technology with a relatively mature process, and is considered to be the fourth-generation packaging technology. TSV technology is to make vertical conduction between chips and wafers, and through the filling of conductive materials such as copper, tungsten, and polysilicon to realize vertical electrical interconnection of through-silicon vias, which can be reduced by vertical interconnection. Small interconnect length, reduced signal delay, reduced capacitance/inductance, low power consumption between chips, high-speed communication, increased bandwidth and miniaturization of device integration.

With the development of electronic products towards miniaturization, no matter how the stacking form and wiring method change, the thickness of each layer of chips used in the stacking inevitably needs to be reduced under the trend that the overall thickness of the package remains unchanged or even decreases. Thin. In the 3D stacking project, the thickness of TSV chips is between 100 and 200 μm. Compared with conventional chips, there will be warpage problems at room temperature or high temperature environment. The warpage degree increases with the increase of chip size. Under the current conventional process, after the TSV chip is flip-chip reflowed and underfilled, the warpage can reach more than 200μm, and in the case of large warpage of the TSV chip, mounting the chip on the TSV chip will It is difficult to implement, especially when the size of the top chip is small, it is difficult to complete the packaging of the whole chip.

SUMMARY OF THE INVENTION

The purpose of the present invention is to provide a method for manufacturing a package structure and a device for preventing warping of a chip.

In order to achieve one of the above purposes of the invention, an embodiment of the present invention provides a manufacturing method of a package structure, the manufacturing method comprising the steps of:

A test substrate and a test stack chip set are provided, the test stack chip set includes at least an upper test chip and a lower test chip, and the lower test chip is formed between the test substrate and the upper test chip to form a test package structure;

performing a reflow soldering process on the test package structure;

testing the welding performance between the upper test chip and the lower test chip after the reflow soldering process;

When the soldering performance fails, a chip anti-warping device and a product packaging structure identical to the test package structure are provided. The product packaging structure is fixedly placed above the base, the support members are respectively placed on both sides of the product packaging structure, the cover plate is covered on the upper surface of the product packaging structure, and is mounted on the product packaging structure. on the support;

A reflow soldering process is performed on the product packaging structure that is fixedly loaded in the chip warpage preventing device.

As a further improvement of an embodiment of the present invention, forming the lower test chip between the test substrate and the upper test chip to form a test package structure specifically includes:

Flip-chip welding the functional surface of the lower test chip to the upper surface of the test substrate through solder balls;

The functional surface of the upper test chip is flip-chip bonded to the upper surface of the lower test chip through solder balls.

As a further improvement of an embodiment of the present invention, the testing of the soldering performance between the upper test chip and the lower test chip in the package structure after the reflow soldering process specifically includes:

testing the electrical conductivity between the upper test chip and the lower test chip;

The soldering quality of the solder balls is inspected by X-Ray technology.

As a further improvement of an embodiment of the present invention, providing the product packaging structure that is exactly the same as the test packaging structure specifically includes:

providing the same substrate as the test substrate and the same stacked chip set as the test stacked chip set, the stacked chip set including at least the same upper chip as the upper test chip and the same lower part as the lower test chip chip;

The lower chip is formed between the substrate and the upper chip to form a product package structure.

As a further improvement of an embodiment of the present invention, the fixing and placing of the product packaging structure above the base specifically includes:

The device further includes a base plate fixing member, and the base plate fixing member is placed above the base;

The substrate is fixed and clamped in the substrate fixing member.

As a further improvement of an embodiment of the present invention, the support members are respectively placed on both sides of the product packaging structure, the cover plate is covered on the upper surface of the product packaging structure, and is mounted on the product packaging structure. on the support, specifically including:

The support members placed on one side of the base plate include a set of first support members and two sets of second support members, the first support members are placed on opposite sides of the cover plate along the length direction, and the two sets of support members are placed. The second support members are placed on opposite sides of the cover plate along the width direction, and the first support member and the second support member placed on the same side of the base plate form a triangular structure on a plane;

The cover plate is covered on the upper surface of the upper chip, and is mounted on the first support member and the second support member at the same time.

As a further improvement of an embodiment of the present invention, the manufacturing method further includes:

A step is formed on the top of the first support member and the second support member, which is recessed inward toward the cover plate side, and the height of the upper surface of the step is consistent with the height of the upper surface of the upper chip. Both ends of the board in its length direction are simultaneously mounted on the upper surfaces of the steps of the first support and the second support, and the cover plate is fixedly clamped to the first support and the second support. Inside the steps of the two supports.

As a further improvement of an embodiment of the present invention, the manufacturing method further includes:

An elastic piece is installed at the partial area of the support piece, and the elastic piece enables the support piece to perform telescopic movement in the height direction thereof.

The present invention also provides a chip anti-warping device, the chip anti-warping device includes a base and at least two support members disposed on the base, the base is used for placing a substrate and a support member disposed on the substrate. a stacked chip set, the stacked chip set at least includes an upper chip and a lower chip, the lower chip is arranged between the substrate and the upper chip, and the support members are respectively arranged on both sides of the substrate;

The device further includes a cover plate, the cover plate covers the upper surface of the upper chip, and is mounted on the support member.

As a further improvement of an embodiment of the present invention, the support members disposed on both sides of the base plate include a first support member and a second support member, and the first support members are disposed on opposite sides of the cover plate along the length direction. , the second support members are arranged on opposite sides of the cover plate along the width direction.

As a further improvement of an embodiment of the present invention, the support member disposed on one side of the substrate includes a set of first support members and two sets of second support members, and the two sets of second support members are respectively disposed on the cover plate On opposite sides along the width direction, the first support member and the second support member located on the same side of the substrate form a triangular structure on a plane.

As a further improvement of an embodiment of the present invention, the tops of the first support member and the second support member are recessed inward toward the substrate side to form a step, and the height of the upper surface of the step is the same as the height of the upper surface of the upper chip. The surface heights are kept the same, the two ends of the cover plate in the longitudinal direction are mounted on the upper surfaces of the steps of the first support member and the second support member at the same time, and the cover plate is fixedly clamped to the in the steps of the first support and the second support.

As a further improvement of an embodiment of the present invention, the functional surface of the lower chip is flip-chip bonded to the upper surface of the substrate through solder balls, and the functional surface of the upper chip is flip-chip bonded to the lower chip through solder balls. upper surface.

As a further improvement of an embodiment of the present invention, the device further includes a base plate fixing member, the base plate fixing member is disposed above the base, and the base plate is fixedly clamped in the base plate fixing member.

As a further improvement of an embodiment of the present invention, the height of the top of the substrate fixing member is lower than the height of the upper surface of the step.

As a further improvement of an embodiment of the present invention, an elastic member is provided in a partial area of the support member, and the elastic member enables the support member to perform telescopic movement in the height direction thereof.

The beneficial effect of the present invention is that the formed test packaging structure is subjected to a reflow soldering process at one time, and if the soldering performance of the test packaging structure is normal after the reflow soldering process, the same chips in the subsequent product manufacturing process as those in the test packaging structure can be used. The manufacturing process of first soldering and then reflowing; however, when the soldering performance of the test package structure fails after the reflow soldering process, in the subsequent product manufacturing process, the product package structure identical to the test package structure is fixedly installed in the package provided by the present invention. In the anti-warping device of the chip, the reflow soldering process is carried out. Even if the upper chip is small in size and light in weight, the weight of the cover plate is used to press the upper chip, which can well suppress the chip packaging structure. During the reflow soldering process, the lower chip is warped to a large extent, preventing welding problems between the upper chip and the lower chip, and improving the welding quality of the 3D package.

Description of drawings

FIG. 1 is a schematic flowchart of a manufacturing method of a package structure in an embodiment of the present invention.

FIGS. 2( a ) to ( h ) are diagrams of manufacturing steps of a package structure in an embodiment of the present invention.

FIG. 3 is a structural side view of a chip warpage preventing device in an embodiment of the present invention.

FIG. 4 is a top view of the structure of a device for preventing warping of a chip according to an embodiment of the present invention.

FIG. 5 is a structural side view of a device for preventing warping of a chip according to another embodiment of the present invention.

Detailed ways

In order to make the objectives, technical solutions and advantages of the present invention clearer, the technical solutions of the present invention will be clearly and completely described below with reference to the specific embodiments of the present invention and the corresponding drawings. Obviously, the described embodiments are only some, but not all, embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

Embodiments of the present invention are described in detail below, examples of which are illustrated in the accompanying drawings, wherein the same or similar reference numerals refer to the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary, only used to explain the present invention, and should not be construed as a limitation of the present invention.

For the convenience of description, the term used to describe the relative position in space, such as "upper", "lower", "rear", "front", etc., is used to describe one unit or feature shown in the drawings relative to another A unit or feature relationship. The term spatially relative position may include different orientations of the device in use or operation other than the orientation shown in the figures. For example, if the device in the figures is turned over, elements described as "below" or "above" other elements or features would then be oriented "below" or "above" the other elements or features. Thus, the exemplary term "below" can encompass both a spatial orientation of below and above.

An embodiment of the present invention also provides a manufacturing method of a package structure, as shown in FIG. 1 , including the steps:

S1: Provide a test substrate and a test stack chip set, the test stack chip set includes at least an upper test chip and a lower test chip, and the lower test chip is formed between the test substrate and the upper test chip to form a test package structure.

S2: The test package structure is subjected to a reflow soldering process.

S3: Test the soldering performance between the upper test chip and the lower test chip after the reflow soldering process.

S4: When the soldering performance fails, provide a chip anti-warping device and a product packaging structure with the same structure as the test package. The chip anti-warping device includes a base, at least two supports and a cover plate, and the product packaging structure is fixedly placed Above the base, the support members are respectively placed on both sides of the product packaging structure, the cover plate is covered on the upper surface of the product packaging structure, and mounted on the support members.

S5: perform a reflow soldering process on the product packaging structure that is fixedly loaded in the chip anti-warping device.

In step S1, a test substrate 1' and a test stack chip set 2' are provided. The test stack chip set 2' includes at least an upper test chip 21' and a lower test chip 22', and the lower test chip 22' is formed on the test substrate 1 ' and the upper test chip 21', a test package structure A' is formed, which specifically includes:

As shown in FIGS. 2( a ) to ( c ), a test substrate 1 ′ is provided. The upper surface of the test substrate 1 ′ is provided with a plurality of electrical pads, and the functional surface of the lower test chip 22 ′ is bonded by a flip-chip ball bonding process. The solder balls 6 are welded to the upper surface of the test substrate 1 ′, and the lower test chip 22 ′ is electrically connected to the test substrate 1 ′. On the upper surface of the chip 22', the upper test chip 21' and the lower test chip 22' are electrically connected. In this embodiment, the lower test chip 22 ′ is preferably a TSV chip, and its thickness can be selected to be 100-200 μm, the upper test chip 21 ′ is other functional chips, and the chip thickness can be selected according to actual design requirements, and the solder balls 6 are tin The ball, which can be melted and welded at high temperature, is solid at normal temperature, and plays a certain supporting role for the lower test chip 22' and the upper test chip 21'.

Of course, this step also includes applying flux to the functional surface of the lower test chip 22' and the functional surface of the upper test chip 21', which is the prior art, and the present invention will not be described here, but it should be emphasized that, In the specific embodiment of the present invention, a flux with high viscosity and good temperature resistance, such as a resin active series flux, is used to prevent the upper test chip 21 ′, the lower test chip 22 ′ and the package structure during the reflow soldering process. There is a risk of displacement between the test substrates 1'.

In an embodiment of the present invention, the upper test chip 21' is two chips that are soldered side by side on the lower test chip 22', as shown in Fig. 2(c). In other embodiments of the present invention, the upper test chip 21 ′ can also be multiple chips welded side by side on the lower test chip 22 ′, or a multi-layer chip stacked and welded in the vertical direction, which can be set according to actual design requirements , the present invention is not limited here.

In step S3, test the welding performance between the upper test chip 21' and the lower test chip 22' after the reflow process, specifically including:

Conduct a conductivity test on the test package structure A' after step S2, specifically, test the conductivity between the upper test chip 21' and the lower test chip 22', if the upper test chip 21' and the lower test chip 22' If there is an electrical connection between them, the test result is normal. For each chip that is the same as the upper test chip 21' and the lower test chip 22', it can be fabricated according to steps S1-S2, and the chips are first soldered, assembled, and reflowed again. If the test result of the electrical conductivity between the upper test chip 21' and the lower test chip 22' is an open circuit or a short circuit, step S4 is performed.

In another embodiment of the present invention, for the test package structure A' after step S2, X-Ray technology can also be used to detect the soldering quality of the solder balls 6. Specifically, the upper test chip 21' and the lower test chip 21' are inspected. The soldering quality of each solder ball 6 between the chips 22 ′ is observed, and whether the solder ball 6 after the reflow soldering process has voids, solder bridges, excessive solder joints, insufficient solder joints, etc. is observed. Similarly, if the detection result is normal, each chip identical to the upper test chip 21' and the lower test chip 22' can be fabricated according to steps S1-S2, and the fabrication process of chip welding, assembly, and reflow is performed again; If it is detected that the solder balls 6 are abnormal, step S4 is performed.

Of course, in other embodiments of the present invention, it is also possible to not only detect the conductive performance of the package structure A', but also use the X-Ray technology to detect the soldering quality of the solder balls 6, so as to ensure the accuracy of whether the package structure's solderability performance is effective. Specifically, the detection can be performed based on the actual manufacturing process, and the present invention does not limit the specific technical means for detecting the welding performance.

In step S4, the same product packaging structure A as the test packaging structure A' is provided, which specifically includes:

As shown in FIG. 2(d), the same substrate 1 as the test substrate 1' and the same stacked chip set 2 as the test stacked chip set 2' are provided, the stacked chip set 2 including at least the same upper chip as the upper test chip 21' 21 and the same lower chip 22 as the lower test chip 22'.

The lower chip 22 is formed between the substrate 1 and the upper chip 21 to form the product packaging structure A. Specifically, a plurality of electrical pads are arranged on the upper surface of the substrate 1, and the functional surface of the lower chip 22 is bonded by a flip-chip ball bonding process. By soldering the solder balls 6 to the upper surface of the substrate 1, the lower chip 22 is electrically connected to the substrate 1, and the functional surface of the upper chip 21 is flip-chip welded to the upper surface of the lower chip 22 through the solder balls 6. The upper chip 21 It is electrically connected with the lower chip 22 . Here, the selection of the chip types of the upper chip 21 and the lower chip 22 and the specific arrangement of the upper chip 21 are the same as those in the test package structure A', which will not be repeated here. The following description will be given by taking as an example the package structure in which the upper chip 21 is two chips soldered on the lower chip 22 side by side in FIG. 2( d ).

In step S4, a chip anti-warping device is provided, and the product packaging structure A is fixedly placed above the base 3, which specifically includes:

As shown in FIG. 2(e), the chip anti-warping device in the specific embodiment of the present invention also provides a substrate fixing member 7, and the product packaging structure A and the substrate fixing member 7 are placed above the base 3, and the substrate fixing member 7 is at least It is placed at a pair of corners of the substrate 1, and two substrate fixing members 7 are respectively placed on both sides of the corner ends of the opposite corners of the substrate 1, and the substrate 1 is fixed by the two substrate fixing members 7 placed on both sides of the diagonal corner ends. live. Specifically, two substrate fixing members 7 are respectively placed on both sides of each corner end of the two opposite corners of the substrate 1, and the substrate 1 is fixedly clamped in the substrate fixing member 7, which is used to secure the substrate 1 in the subsequent packaging process. Fixed.

In the specific embodiment of the present invention, the height of the provided substrate fixing member 7 may be slightly higher than the height of the upper surface of the substrate 1 to ensure that it can better fix the substrate 1 . However, the specific height of the substrate fixing member 7 is not limited in the present invention, as long as the height of the top end of the substrate fixing member 7 is lower than the height of the upper surface of the upper chip 21, the substrate 1 can be fixed without moving. It only needs to interfere with the lower surface of the cover plate 5 placed above the upper chip 21 in the subsequent process.

Preferably, the substrate fixing member 7 is a Pin. Of course, in some other embodiments of the present invention, the substrate fixing member 7 can also be a fixing member made of other high temperature resistant materials, which can still lift the substrate 1 under high temperature. to the fixed effect.

In other embodiments of the present invention, the substrate 1 can also be fixedly placed on the base 3 first, and then a chip bonding process is performed on the upper surface of the substrate 1 to form the product package structure A. For the two process sequences, the present invention is in This is not limited.

In step S4, the support members 4 are respectively placed on both sides of the product packaging structure A, the cover plate 5 is covered on the upper surface of the product packaging structure A, and is mounted on the support member 4, which specifically includes:

As shown in FIG. 2( f ), the cover plate 5 is a rectangular silicon wafer, and the cover plate 5 is placed on the upper surface of the upper chip 21 , that is, the lower surface of the cover plate 5 is in contact with the upper surface of the upper chip 21 , and is used to apply a certain amount to the upper chip 21 . The pressure, the greater its weight, the greater the pressure exerted on the upper chip 21 . The size of the cover plate 5 can be designed according to the specific arrangement of the upper chips 21 . Preferably, the cover plate 5 fully covers the upper surface of each upper chip 21 to ensure that the positions of each upper chip 21 are uniformly stressed. The thickness of the cover plate 5 can be determined according to the actual design requirements. In the subsequent reflow soldering process, the pressure exerted by the cover plate 5 on the upper chip 21 can not only prevent the lower chip 22 from warping, but will not affect the relationship between the upper chip 21 and the lower chip 22. At the same time, it can also ensure that the pressure exerted on the upper chip 21 will not collapse the solder balls 6 . Of course, in some other embodiments, the material of the cover plate 5 can also be some other high temperature resistant materials, such as glass sheets and the like.

As shown in FIG. 2( g ), the support member 4 placed on one side of the substrate 1 provided in the specific embodiment of the present invention includes a set of first support members 41 and two sets of second support members 42 . Placed on opposite sides of the cover plate 5 along the length direction, two sets of second supports 42 are placed on the opposite sides of the cover plate 5 along the width direction, placed on the first support 41 and the second support on the same side of the substrate 1 The pieces 42 form a triangular structure in plan.

Specifically, the tops of the provided first support member 41 and the second support member 42 are recessed inward toward the cover plate 5 to form a step 43 , and the height of the upper surface of the formed step 43 is consistent with the height of the upper surface of the upper chip 21 . . Both ends of the cover plate 5 in the longitudinal direction are placed on the upper surfaces of the steps 43 of the first support member 41 and the second support member 42 at the same time, and the cover plate 5 can be fixedly clamped to the first support member 41 and the second support member 42. Inside the steps of the two support members 42 . In this way, the stepped surfaces of the first support members 41 placed on opposite sides of the cover plate 5 in the length direction fix the cover plate 5 in its length direction, and the second support members located on the opposite sides in the width direction of the cover plate 5 The stepped surface of 42 fixes the cover plate 5 in its width direction.

Preferably, the first support member 41 and the second support member 42 are Pin pins. Of course, the present invention does not limit the materials for making the first support member 41 and the second support member 42. Have some support.

In some possible embodiments of the present invention, the first support member 41 , the second support member 42 and the substrate fixing member 7 in the provided chip anti-warping device can be moved and fixed at any position on the base 3 , and the first support member 41 and The specific position where the second support member 42 is fixed on the base 3 can be determined according to the specific length of the cover plate 5 and the specific position where it is placed on the upper surface of the upper chip 21 . The first support members 41 placed on both sides of the cover plate 5 It is only necessary that the step of the second support member 42 can restrict the movement of the cover plate 5 in the longitudinal direction and the width direction thereof. The specific number and arrangement of the support members 4 for supporting and fixing the cover plate 5 are specifically adjusted according to factors such as the size of the cover plate 5 . The specific position where the substrate fixing member 7 is fixed on the base 3 is specifically adjusted according to the specific size of the substrate 1 , and the substrate fixing members 7 placed on both sides of each corner end of the two diagonal corners of the substrate 1 can restrict the substrate 1 in its length direction. and movement in the width direction.

Finally, step S5 is performed to perform a reflow soldering process on the product packaging structure fixedly loaded in the provided chip warpage preventing device. Since the cover plate 5 exerts a certain pressure on the upper chip 21, it can relatively avoid the upper chip 21 and the lower part under high temperature. The movement of the chip 22 in the horizontal direction prevents the soldering failure between the upper chip 21 and the lower chip 22 due to the large warpage of the lower chip 22 caused by the temperature change during the reflow soldering process.

However, since the solder balls 6 are in a melted state at high temperature, the size, thickness and weight design of the cover plate 5 are very important for the pressure exerted on the upper chip 21 and the lower chip 22. Excessive pressure can easily cause the upper chip 21 and the lower chip 22. There is a bridging phenomenon between the lower chip 22 and the substrate 1, so the selection of the size, thickness and weight of the cover plate 5 needs to be very precise, and the process is difficult.

Therefore, in step S4 of the manufacturing method of the package structure of the present invention, another structure of the chip anti-warping device is provided. As shown in FIG. Before being mounted on the base 3 , an elastic member 8 is installed at a partial area of the support member 4 . Specifically, an elastic member 8 is installed at the bottom ends of the first support member 41 and the second support member 42, and the elastic member 8 enables the first support member 41 and the second support member 42 to perform telescopic movement in the height direction thereof.

When the solder balls 6 are in a melted state at a high temperature, their supporting force on the upper chip 21 and the lower chip 22 is reduced, and the pressure of the cover plate 5 on the upper chip 21 and the lower chip 22 is greater than that of the solder balls 6 on the upper chip under high temperature. 21 and the supporting force of the lower chip 22, the elastic member 8 gradually shrinks at this time, that is, the elastic member 8 moves downward in its height direction, and the supporting force of the elastic member 8 for the cover plate 5 rises to avoid the upper chip 21 and the lower chip. A bridge phenomenon occurs between 22 and between the lower chip 22 and the substrate 1 . Of course, in this embodiment, the weight of the cover plate 5 and the elastic strength of the elastic member 8 are designed according to different products, which are not limited in the present invention. In the chip warpage prevention device with the elastic member 8 installed, the selection of the size, thickness and weight of the cover plate does not need to be precisely controlled, which greatly reduces the difficulty of the process.

Of course, in the chip anti-warping device with the elastic member 8 installed, the elastic member 8 is not limited to being installed at the bottom end of the support member 4, and it can also be fixedly installed on the upper surface of the step 43 of each support member. Both ends in the longitudinal direction are placed above the elastic member 8 and fixedly clamped in the steps 43 of each support member. It should be noted that when the elastic member 8 is installed on the upper surface of the steps 43 of each support member, the height of the upper surface of the step 43 at this time must be lower than the height of the upper surface of the upper chip 21, and the elastic member 8 installed on the step 43 The height of the upper surface of the upper chip 21 must be consistent with the height of the upper surface of the upper chip 21 .

Alternatively, in other possible embodiments of the present invention, the supporting member 4 is integrally supported to form an elastic member, the lower surface of the cover plate 5 is formed with a circular hole corresponding to the size of the supporting member 4, and the top end of the supporting member 4 can be fixedly clamped in the circular hole , the cover plate 5 can be supported and fixed.

The specific structural relationship between the support member 4, the elastic member 8 and the cover plate 5 in the chip warpage prevention device provided by the present invention is not limited to this, as long as the cover plate 5 can be supported and fixed, and the cover plate can be supported and fixed. 5 can be moved in its height direction.

Step S5 is performed on the package structure as shown in FIG. 2(h) that is fixedly loaded in the chip warpage prevention device with the elastic member 8 installed, and the elastic member 8 installed at the bottom end of the support member 4 can prevent the reflow soldering process , since the solder balls are in a melted state at high temperature, their supporting force on the upper chip 21 and the lower chip 22 is reduced. At this time, the elastic member 8 can play a certain supporting force on the cover plate 5 to avoid the upper chip 21 and the lower chip 22. A bridge phenomenon occurs between the chips 22 and between the lower chip 22 and the substrate 1 .

As shown in FIGS. 3 and 4 , the present invention further provides a device for preventing warping of a chip, which is applied to a method for manufacturing a package structure. In the 3D stacking project, the lower chip is thinner, and the lower chip is prone to warpage at room temperature or high temperature. When the fabricated test package structure cannot guarantee the soldering performance between chips after reflow soldering The chip warpage prevention device provided by the present invention needs to be used, especially when the size of the upper chip is small, the pressure on the lower chip cannot restrain the warpage of the lower chip, which may easily lead to the problem of welding failure between the upper chip and the lower chip. Therefore, the device for preventing warping of the chip provided by the present invention is applied to the case where the upper chip is small in size and light in weight.

The chip warpage prevention device proposed in an embodiment of the present invention includes a base 3 and at least two support members 4 disposed on the base 3 . The base 3 is used to place the substrate 1 and the stacked chip set 2 disposed on the substrate 1 .

The stacked chip set 2 includes at least an upper chip 21 and a lower chip 22 , and the lower chip 22 is disposed between the substrate 1 and the upper chip 21 . The lower chip 22 is preferably a TSV chip, and its thickness can be selected to be 100-200 μm, and the upper chip 21 is another functional chip, and the thickness of the chip can be selected according to actual design requirements. In an embodiment of the present invention, the upper chip 21 is two chips that are soldered on the lower chip 22 side by side, as shown in the figure. Of course, in other embodiments of the present invention, the upper chip 21 may also be a plurality of chips welded on the lower chip 22 side by side, or a plurality of chips stacked and welded in the vertical direction, which can be set according to actual design requirements. The invention is not limited here, and the following description will be given as an example of a package structure in which the upper chip 21 is two chips soldered on the lower chip 22 side by side.

Specifically, the lower chip 22 has a functional surface provided with pads and a non-functional surface opposite to the functional surface. The functional surface of the lower chip 22 is disposed facing the substrate 1, and is flip-chip welded to the upper surface of the substrate 1 through the solder balls 6. The substrate 1 realizes electrical connection. Similarly, the upper chip 21 has a functional surface provided with pads and a non-functional surface opposite to the functional surface. The functional surface of the upper chip 21 is disposed toward the lower chip 22 and is flip-chip bonded to the upper surface of the lower chip 22 through solder balls 6 , which is electrically connected with the lower chip 22 . In this embodiment, the solder balls 6 are specifically solder balls, which can be melted for soldering at high temperature, and are solid at normal temperature, and play a certain supporting role for the lower chip 22 and the upper chip 21 .

The support members 4 are respectively disposed on both sides of the substrate 1 , and the chip anti-warping device further includes a cover plate 5 . The cover plate 5 covers the upper surface of the upper chip 21 and is mounted on the support member 4 . Specifically, the cover plate 5 is a rectangular silicon wafer, the lower surface of which is in contact with the upper surface of the upper chip 21 for exerting a certain pressure on the upper chip 21 . The size of the cover plate 5 can be designed according to the specific arrangement of the upper chips 21 . Preferably, the cover plate 5 fully covers the upper surface of each upper chip 21 to ensure that the positions of each upper chip 21 are uniformly stressed. The thickness of the cover plate 5 can be determined according to the actual design requirements. In the subsequent reflow soldering process, the pressure exerted by the cover plate 5 on the upper chip 21 can not only prevent the lower chip 22 from warping, but will not affect the relationship between the upper chip 21 and the lower chip 22. At the same time, it can also ensure that the pressure exerted on the upper chip 21 will not collapse the solder balls 6 . Of course, in some other embodiments, the material of the cover plate 5 can also be some other high temperature resistant materials, such as glass sheets and the like.

Specifically, the support members 4 disposed on both sides of the base plate 1 include a first support member 41 and a second support member 42 , the first support member 41 is disposed on opposite sides of the cover plate 5 along the length direction, and the second support member 42 is disposed on opposite sides of the cover plate 5 along the width direction.

The support member 4 disposed on one side of the base plate 1 includes a set of first support members 41 and two sets of second support members 42. The two sets of second support members 42 are respectively disposed on opposite sides of the cover plate 5 along the width direction, located on the base plate. The first support 41 and the second support 42 on the same side form a triangular structure on a plane.

More specifically, the tops of the first support member 41 and the second support member 42 are recessed inward toward the cover plate 5 to form a step 43 . The height of the upper surface of the step 43 is consistent with the height of the upper surface of the upper chip 21 . Both ends in the longitudinal direction are mounted on the upper surfaces of the steps 43 of the first support 41 and the second support 42 at the same time, and the cover plate 5 is fixedly clamped to the steps of the first support 41 and the second support 42 Inside. That is, the stepped surfaces of the first support members 41 located on opposite sides of the cover plate 5 in the length direction fix the cover plate 5 in its length direction, and the second support members 42 located on the opposite sides in the width direction of the cover plate 5 are The stepped surface immobilizes the cover plate 5 in its width direction.

In the specific embodiment of the present invention, the first support member 41 and the second support member 42 are Pin needles. Of course, the present invention does not limit the materials for making the first support member 41 and the second support member 42, and the materials that can withstand high temperature are selected. The material is sufficient and has a certain supporting force at high temperature.

Further, the chip anti-warping device further includes a substrate fixing member 7 , the substrate fixing member 7 is arranged above the base 3 , and the substrate fixing member 7 is arranged at least at a pair of corners of the substrate 1 and on both sides of the corner ends of the pair of corners of the substrate 1 . Two substrate fixing members 7 are respectively provided, and the substrate 1 is fixedly clamped in the substrate fixing members 7 . In this embodiment, two substrate fixing members 7 are respectively disposed on both sides of each corner end of two opposite corners of the substrate 1 , so as to fix the substrate 1 in a subsequent packaging process.

Specifically, the height of the top of the substrate fixing member 7 may be slightly higher than the height of the upper surface of the substrate 1 to ensure that it can better fix the substrate 1 . However, the specific height of the substrate fixing member 7 is not limited in the present invention. As long as the height of the top end of the substrate fixing member 7 is lower than the height of the upper surface of the step 43, the substrate 1 can be fixed without any What is necessary is just to interfere with the lower surface of the cover plate 5 .

The substrate fixing member 7 is also a pin. Of course, in other embodiments of the present invention, the substrate fixing member 7 can also be a fixing member made of other high-temperature resistant materials, which can still fix the substrate 1 at high temperatures. can work.

In some possible embodiments of the present invention, the first support member 41 , the second support member 42 and the base plate fixing member 7 can be movably fixed to any position on the base, and the first support member 41 and the second support member 42 are fixed to the base 3 The specific position of the upper chip 21 can be determined according to the specific length of the cover plate 5 and its specific position on the upper surface of the upper chip 21. The steps of the first support member 41 and the second support member 42 on both sides of the cover plate 5 can limit the The cover plate 5 may be moved in the longitudinal direction and the width direction. The specific number and arrangement of the support members 4 provided to support and fix the cover plate 5 are specifically adjusted according to factors such as the size of the cover plate 5 . The specific position where the substrate fixing member 7 is fixed on the base 3 can be determined according to the specific size of the substrate 1 . Move in the width direction.

At normal temperature, since the solder balls 6 are solid, they can support the pressure of the cover plate 5 on the upper chip 21 and the lower chip 22 , while at high temperature, the solder balls 6 will be in a melted state as the temperature increases, and the cover plate 5 The size, thickness, and weight design are very important for the pressure applied to the upper chip 21 and the lower chip 22. Excessive pressure can easily lead to bridges between the upper chip 21 and the lower chip 22, and between the lower chip 22 and the substrate 1. Therefore, the selection of the size, thickness and weight of the cover plate 5 in the chip warpage prevention device in the above embodiment needs to be very precise, and the process is difficult.

As shown in FIG. 5 , the device for preventing warping of chips in another embodiment of the present invention is different from the structure in FIG. 3 in that in order to prevent the solder balls 6 on the lower surfaces of the upper chip 21 and the lower chip 22 from melting at high temperature, As a result, a bridge phenomenon occurs between the upper chip 21 and the lower chip 22 and between the lower chip 22 and the substrate 1. An elastic member 8 is provided in a partial area of the support member 4, and the elastic member 8 can make the support member 4 move in its height direction. For telescopic movement, specifically, the elastic member 8 is provided at the bottom end of the support member 4 , that is, the bottom ends of the first support member 41 and the second support member 42 are both provided with the elastic member 8 . Since the solder balls 6 are in a melted state at a high temperature, the supporting force for the upper chip 21 and the lower chip 22 is reduced, and the pressure of the cover plate 5 on the upper chip 21 and the lower chip 22 is greater than that under the high temperature. When the supporting force of the lower chip 22 is used, the elastic member 8 is gradually contracted at this time, that is, the elastic member 8 moves downward in its height direction, and the supporting force of the elastic member 8 for the cover plate 5 increases to avoid the upper chip 21 and the lower chip 22. A bridging phenomenon occurs between, and between the lower chip 22 and the substrate 1 . In this embodiment, the weight of the cover plate 5 and the elastic strength of the elastic member 8 are designed according to different products, and the present invention is not limited herein.

Of course, in the present invention, the elastic member 8 is not limited to be disposed at the bottom end of the support member 4, and it can also be fixedly disposed on the upper surface of the step 43 of each support member. The two ends of the cover plate 5 in the length direction are placed on the elastic member. 8, and fixedly clamped in the steps 43 of each support. It should be noted that when the elastic member 8 is disposed on the upper surface of the steps 43 of each support member, the height of the upper surface of the step 43 at this time must be lower than the height of the upper surface of the upper chip 21, and the elastic member 8 placed on the step 43 The height of the upper surface of the upper chip 21 must be consistent with the height of the upper surface of the upper chip 21 .

Alternatively, in other possible implementations of the present invention, the supporting member 4 is an elastic member as a whole, the lower surface of the cover plate 5 is provided with a circular hole corresponding to the size of the supporting member 4, and the top end of the supporting member 4 can be fixedly clamped to the circular hole Inside, the cover plate 5 can be supported and fixed.

The specific structural relationship between the support member 4, the elastic member 8 and the cover plate 5 in the present invention is not limited to this, as long as the cover plate 5 can be supported and fixed, and the cover plate 5 can be moved in its height direction, that is, Can.

To sum up, the test package structure formed in the present invention is subjected to a reflow soldering process at one time. If the soldering performance of the test package structure is normal after the reflow soldering process, the same chips in the subsequent product manufacturing process as those in the test package structure can be used. The manufacturing process of first soldering and then reflowing is adopted; however, when the soldering performance of the test package structure fails after the reflow process, in the subsequent product manufacturing process, the product package structure identical to the test package structure is fixedly installed in the present invention In the provided chip anti-warping device, the reflow soldering process is performed again. Even if the upper chip is small in size and light in weight, the weight of the cover plate is used to press the upper chip, which can well suppress the chip packaging. In the structure, the lower chip is warped to a large extent during the reflow soldering process, which prevents welding problems between the upper chip and the lower chip, and improves the welding quality of the 3D package.

It should be understood that although this specification is described in terms of embodiments, not every embodiment only includes an independent technical solution, and this description in the specification is only for the sake of clarity, and those skilled in the art should take the specification as a whole, and each The technical solutions in the embodiments can also be appropriately combined to form other embodiments that can be understood by those skilled in the art.

The series of detailed descriptions listed above are only specific descriptions for the feasible embodiments of the present invention, and they are not used to limit the protection scope of the present invention. Changes should all be included within the protection scope of the present invention.

Claims (16)

1. a preparation method of packaging structure, is characterized in that, described preparation method comprises the steps: A test substrate and a test stack chip set are provided, the test stack chip set includes at least an upper test chip and a lower test chip, and the lower test chip is formed between the test substrate and the upper test chip to form a test package structure; performing a reflow soldering process on the test package structure; testing the welding performance between the upper test chip and the lower test chip after the reflow soldering process; When the soldering performance fails, a chip anti-warping device and a product packaging structure identical to the test package structure are provided. The product packaging structure is fixedly placed above the base, the support members are respectively placed on both sides of the product packaging structure, the cover plate is covered on the upper surface of the product packaging structure, and is mounted on the product packaging structure. on the support; A reflow soldering process is performed on the product packaging structure that is fixedly loaded in the chip warpage preventing device. 2 . The method for manufacturing a package structure according to claim 1 , wherein the forming the lower test chip between the test substrate and the upper test chip to form a test package structure specifically includes: 3 . Flip-chip bonding the functional surface of the lower test chip to the upper surface of the test substrate through solder balls; The functional surface of the upper test chip is flip-chip bonded to the upper surface of the lower test chip through solder balls. 3 . The manufacturing method of the package structure according to claim 2 , wherein, the welding performance between the upper test chip and the lower test chip in the package structure after the reflow soldering process is tested, specifically include: testing the electrical conductivity between the upper test chip and the lower test chip; The soldering quality of the solder balls is inspected by X-Ray technology. 4. The method for manufacturing a packaging structure according to claim 3, wherein the providing a product packaging structure identical to the test packaging structure specifically includes: providing the same substrate as the test substrate and the same stacked chip set as the test stacked chip set, the stacked chip set including at least the same upper chip as the upper test chip and the same lower part as the lower test chip chip; The lower chip is formed between the substrate and the upper chip to form a product package structure. 5 . The manufacturing method of the packaging structure according to claim 4 , wherein the fixing and placing the product packaging structure above the base comprises: 5 . The device further includes a base plate fixing member, and the base plate fixing member is placed above the base; The substrate is fixed and clamped in the substrate fixing member. 6 . The manufacturing method of the package structure according to claim 5 , wherein the support members are respectively placed on both sides of the product package structure, and the cover plate is covered on the product package structure. 7 . The upper surface of the , and is mounted on the support, including: The support members placed on one side of the base plate include a set of first support members and two sets of second support members, the first support members are placed on opposite sides of the cover plate along the length direction, and the two sets of support members are placed. The second support members are placed on opposite sides of the cover plate along the width direction, and the first support member and the second support member placed on the same side of the base plate form a triangular structure on a plane; The cover plate is covered on the upper surface of the upper chip, and is mounted on the first support member and the second support member at the same time. 7. The manufacturing method of the packaging structure according to claim 6, wherein the manufacturing method further comprises: A step is formed on the top of the first support member and the second support member, which is recessed inward toward the cover plate side, and the height of the upper surface of the step is consistent with the height of the upper surface of the upper chip. Both ends of the board in its length direction are simultaneously mounted on the upper surfaces of the steps of the first support and the second support, and the cover plate is fixedly clamped to the first support and the second support. Inside the steps of the two supports. 8. The manufacturing method of the packaging structure according to any one of claims 1-7, wherein the manufacturing method further comprises: An elastic piece is installed at the partial area of the support piece, and the elastic piece enables the support piece to perform telescopic movement in the height direction thereof. 9. A chip anti-warping device, characterized in that, The chip anti-warping device includes a base and at least two support members arranged on the base, the base is used to place a substrate and a stacked chip set arranged on the base, and the stacked chip set at least includes an upper part a chip and a lower chip, the lower chip is arranged between the substrate and the upper chip, and the support members are respectively arranged on both sides of the substrate; The device further includes a cover plate, the cover plate covers the upper surface of the upper chip, and is mounted on the support member. 10 . The chip anti-warping device according to claim 9 , wherein the support members disposed on both sides of the substrate comprise a first support member and a second support member, and the first support member is disposed on the On opposite sides of the cover plate along the length direction, the second support members are disposed on opposite sides of the cover plate along the width direction. 11 . The chip anti-warping device according to claim 10 , wherein the support members disposed on one side of the substrate comprise a set of first support members and two sets of second support members, and two sets of the second support members. 12 . The support members are respectively disposed on opposite sides of the cover plate along the width direction, and the first support member and the second support member located on the same side of the base plate form a triangular structure on a plane. 12 . The device for preventing warpage of a chip according to claim 11 , wherein the tops of the first support member and the second support member are recessed inward toward the substrate to form a step, and the step is 12 . The height of the upper surface is consistent with the height of the upper surface of the upper chip, and both ends of the cover plate in its length direction are simultaneously mounted on the upper surfaces of the steps of the first support and the second support, so The cover plate is fixedly clamped in the steps of the first support member and the second support member. 13 . The device for preventing warpage of a chip according to claim 12 , wherein the functional surface of the lower chip is flip-chip welded to the upper surface of the substrate by solder balls, and the functional surface of the upper chip is soldered to the upper surface of the substrate. 14 . Flip-chip bonding to the upper surface of the lower chip. 14 . The chip anti-warping device according to claim 13 , wherein the device further comprises a substrate fixing member, the substrate fixing member is disposed above the base, and the substrate is fixedly clamped to the substrate. 15 . inside the fixture. 15 . The device for preventing warping of chips according to claim 14 , wherein the height of the top of the substrate fixing member is lower than the height of the upper surface of the step. 16 . 16. The device for preventing warping of chips according to any one of claims 9 to 15, wherein an elastic member is provided in a partial area of the support member, and the elastic member can make the support member in the height direction of the support member. Perform a telescoping exercise.

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