CN115101434A - Packaging structure manufacturing method and chip anti-warping device - Google Patents

Packaging structure manufacturing method and chip anti-warping device Download PDF

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Publication number
CN115101434A
CN115101434A CN202210863313.4A CN202210863313A CN115101434A CN 115101434 A CN115101434 A CN 115101434A CN 202210863313 A CN202210863313 A CN 202210863313A CN 115101434 A CN115101434 A CN 115101434A
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China
Prior art keywords
chip
test
substrate
cover plate
supporting
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CN202210863313.4A
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Chinese (zh)
Inventor
徐晨
杨丹凤
何晨烨
林耀剑
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JCET Group Co Ltd
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Jiangsu Changjiang Electronics Technology Co Ltd
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Priority to CN202210863313.4A priority Critical patent/CN115101434A/en
Publication of CN115101434A publication Critical patent/CN115101434A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/10—Measuring as part of the manufacturing process
    • H01L22/12—Measuring as part of the manufacturing process for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
    • H01L22/32—Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Wire Bonding (AREA)

Abstract

The invention discloses a manufacturing method of a packaging structure and a chip warping prevention device, wherein the manufacturing method comprises the following steps: providing a test substrate and a test stacking chip set to form a test packaging structure; carrying out reflow soldering process on the test packaging structure; testing the welding performance of the packaging structure after the reflow soldering process is tested; and when the welding performance fails, providing a chip anti-warping device and a product packaging structure which is the same as the test packaging structure, fixedly loading the product packaging structure in the chip anti-warping device, and then carrying out reflow soldering process. The method can effectively prevent the lower chip from warping to a greater extent in the reflow soldering process, reduce the risk of soldering failure between the upper chip and the lower chip, and improve the 3D packaging soldering quality.

Description

Packaging structure manufacturing method and chip anti-warping device
Technical Field
The invention relates to the technical field of semiconductor packaging, in particular to a packaging structure manufacturing method and a chip anti-warping device.
Background
The TSV (Through Silicon Via) technology is a high-density packaging technology, and is gradually replacing the wire bonding technology that is mature in the current technology, and is considered as a fourth generation packaging technology. The TSV technology is characterized in that vertical conduction is made between chips and between wafers, the wafers and the wafers, vertical electrical interconnection of silicon through holes is achieved through filling of conductive substances such as copper, tungsten and polycrystalline silicon, interconnection length can be reduced through the vertical interconnection, signal delay is reduced, capacitance/inductance is reduced, low power consumption and high-speed communication between the chips are achieved, a broadband is increased, and miniaturization of device integration is achieved.
With the development of electronic products toward miniaturization, no matter how the stacking form and the connection manner are changed, the thickness of each layer of chips used in the stack inevitably needs to be reduced under the trend that the overall thickness of the package is not changed or even reduced. In the 3D stacking project, the thickness of the TSV chip is 100-200 μm, and compared with a conventional chip, the TSV chip has the problem of warping at normal temperature or high temperature, and the warping degree increases along with the increase of the size of the chip. Under the conventional process, after the reverse flow and the bottom filling of the TSV chip are completed, the warpage of the TSV chip can reach more than 200 microns, and under the condition that the TSV chip is greatly warped, the chip is difficult to mount on the TSV chip, and especially when the size of the top chip is small, the whole chip is difficult to package.
Disclosure of Invention
The invention aims to provide a manufacturing method of a packaging structure and a chip anti-warping device.
In order to achieve one of the above objects, an embodiment of the present invention provides a method for manufacturing a package structure, the method comprising:
providing a test substrate and a test stacked chip set, wherein the test stacked chip set at least comprises an upper test chip and a lower test chip, and the lower test chip is formed between the test substrate and the upper test chip to form a test packaging structure;
carrying out a reflow soldering process on the test packaging structure;
testing the welding performance between the upper test chip and the lower test chip after the reflow soldering process;
when the welding performance fails, providing a chip anti-warping device and a product packaging structure which is the same as the test packaging structure, wherein the chip anti-warping device comprises a base, at least two supporting pieces and a cover plate, the product packaging structure is fixedly placed above the base, the supporting pieces are respectively placed on two sides of the product packaging structure, and the cover plate is covered on the upper surface of the product packaging structure and is placed on the supporting pieces in a carrying manner;
and carrying out reflow soldering process on the product packaging structure fixedly loaded in the chip warpage preventing device.
As a further improvement of an embodiment of the present invention, the forming the lower test chip between the test substrate and the upper test chip to form a test package structure specifically includes:
flip-chip bonding the functional surface of the lower test chip to the upper surface of the test substrate through solder balls;
and flip-chip bonding the functional surface of the upper test chip to the upper surface of the lower test chip through solder balls.
As a further improvement of an embodiment of the present invention, the testing of the soldering performance between the upper test chip and the lower test chip in the package structure after the reflow soldering process specifically includes:
testing the conductivity between the upper test chip and the lower test chip;
and detecting the welding quality of the solder balls by using an X-Ray technology.
As a further improvement of an embodiment of the present invention, providing a product package structure that is completely the same as the test package structure specifically includes:
providing a substrate identical to the test substrate and a stacked chip set identical to the test stacked chip set, the stacked chip set including at least an upper chip identical to the upper test chip and a lower chip identical to the lower test chip;
and forming the lower chip between the substrate and the upper chip to form a product packaging structure.
As a further improvement of an embodiment of the present invention, the fixing and placing the product packaging structure above the base specifically includes:
the device also comprises a substrate fixing piece, wherein the substrate fixing piece is placed above the base;
and fixedly clamping the substrate in the substrate fixing piece.
As a further improvement of an embodiment of the present invention, the placing the supporting members on two sides of the product packaging structure, respectively, covering the cover plate on the upper surface of the product packaging structure, and placing the cover plate on the supporting members in a carrying manner specifically includes:
the supporting pieces arranged on one side of the base plate comprise a group of first supporting pieces and two groups of second supporting pieces, the first supporting pieces are arranged on two opposite sides of the cover plate along the length direction, the two groups of second supporting pieces are arranged on two opposite sides of the cover plate along the width direction, and the first supporting pieces and the second supporting pieces arranged on the same side of the base plate form a triangular structure on a plane;
and covering the cover plate on the upper surface of the upper chip, and carrying and placing the cover plate on the first supporting piece and the second supporting piece simultaneously.
As a further improvement of an embodiment of the present invention, the manufacturing method further includes:
and the tops of the first supporting piece and the second supporting piece are inwards sunken towards one side of the cover plate to form a step, the height of the upper surface of the step is consistent with that of the upper surface of the upper chip, two ends of the cover plate in the length direction are simultaneously placed on the upper surfaces of the steps of the first supporting piece and the second supporting piece in a carrying manner, and the cover plate is fixedly clamped in the steps of the first supporting piece and the second supporting piece.
As a further improvement of an embodiment of the present invention, the manufacturing method further includes:
and an elastic piece is arranged at the partial area of the supporting piece, and the elastic piece can enable the supporting piece to perform telescopic movement in the height direction.
The invention also provides a chip warpage prevention device, which comprises a base and at least two supporting pieces arranged on the base, wherein the base is used for placing a substrate and a stacked chip group arranged on the substrate, the stacked chip group at least comprises an upper chip and a lower chip, the lower chip is arranged between the substrate and the upper chip, and the supporting pieces are respectively arranged on two sides of the substrate;
the device also comprises a cover plate, wherein the cover plate is covered on the upper surface of the upper chip and is arranged on the supporting piece in a carrying way.
As a further improvement of an embodiment of the present invention, the supporting members disposed at both sides of the base plate include a first supporting member and a second supporting member, the first supporting member is disposed at opposite sides of the cover plate along a length direction, and the second supporting member is disposed at opposite sides of the cover plate along a width direction.
As a further improvement of an embodiment of the present invention, the supporting members disposed on one side of the base plate include a set of first supporting members and two sets of second supporting members, the two sets of second supporting members are respectively disposed on two opposite sides of the cover plate along the width direction, and the first supporting members and the second supporting members on the same side of the base plate form a triangular structure on a plane.
As a further improvement of the embodiment of the present invention, the top portions of the first supporting member and the second supporting member are recessed inward toward the substrate side to form a step, the height of the upper surface of the step is consistent with the height of the upper surface of the upper chip, the two ends of the cover plate in the length direction are simultaneously mounted on the upper surfaces of the steps of the first supporting member and the second supporting member, and the cover plate is fixedly clamped in the steps of the first supporting member and the second supporting member.
In a further improvement of an embodiment of the present invention, the functional surface of the lower chip is flip-chip bonded to the upper surface of the substrate through solder balls, and the functional surface of the upper chip is flip-chip bonded to the upper surface of the lower chip through solder balls.
As a further improvement of an embodiment of the present invention, the apparatus further includes a substrate fixing member, the substrate fixing member is disposed above the base, and the substrate is fixedly clamped in the substrate fixing member.
As a further improvement of an embodiment of the present invention, a height of a top end of the substrate fixing member is lower than a height of an upper surface of the step.
As a further improvement of an embodiment of the invention, the support part region is provided with an elastic member which can make the support part perform telescopic movement in the height direction thereof.
The invention has the beneficial effects that: performing a reflow soldering process on the formed test packaging structure at one time, and if the soldering performance of the test packaging structure is normal after the reflow soldering process, adopting a manufacturing process of soldering first and then reflowing for chips which are the same as those in the test packaging structure in a subsequent product manufacturing process; however, when the welding performance of the test packaging structure fails after the reflow soldering process, the product packaging structure which is the same as the test packaging structure is fixedly installed in the chip warpage preventing device provided by the invention in the subsequent product manufacturing process, and then the reflow soldering process is performed, so that even if the upper chip is small in size and light in weight, the upper chip is pressed by using the weight of the cover plate, the lower chip of the chip packaging structure can be well restrained from warping to a large extent in the reflow soldering process, the situation that the welding problem occurs between the upper chip and the lower chip is prevented, and the 3D packaging and welding quality is improved.
Drawings
Fig. 1 is a flow chart illustrating a manufacturing method of a package structure according to an embodiment of the invention.
Fig. 2(a) - (h) are process diagrams of manufacturing a package structure according to an embodiment of the invention.
Fig. 3 is a structural side view of a chip warpage preventing apparatus according to an embodiment of the present invention.
Fig. 4 is a top view of a chip warpage preventing apparatus according to an embodiment of the present invention.
Fig. 5 is a structural side view of a chip warpage preventing apparatus in another embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the technical solutions of the present invention will be described in detail and completely with reference to the following detailed description of the invention and the accompanying drawings. It is to be understood that the described embodiments are merely exemplary of the invention, and not restrictive of the full scope of the invention. All other embodiments, which can be obtained by a person skilled in the art without any inventive step based on the embodiments of the present invention, are within the scope of the present invention.
Reference will now be made in detail to embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to the same or similar elements or elements having the same or similar function throughout. The embodiments described below with reference to the accompanying drawings are illustrative only for the purpose of explaining the present invention, and are not to be construed as limiting the present invention.
For convenience in explanation, the description herein uses terms indicating relative spatial positions, such as "upper," "lower," "rear," "front," and the like, to describe one element or feature's relationship to another element or feature as illustrated in the figures. The term spatially relative position may encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as "below" or "above" other elements or features would then be oriented "below" or "above" the other elements or features. Thus, the exemplary term "below" can encompass both a spatial orientation of below and above.
An embodiment of the present invention further provides a method for manufacturing a package structure, as shown in fig. 1, including the steps of:
s1: providing a test substrate and a test stack chip set, wherein the test stack chip set at least comprises an upper test chip and a lower test chip, and forming the lower test chip between the test substrate and the upper test chip to form a test packaging structure.
S2: and carrying out a reflow soldering process on the test packaging structure.
S3: and testing the welding performance between the upper test chip and the lower test chip after the reflow soldering process.
S4: when the welding performance fails, a chip anti-warping device and a product packaging structure identical to the test packaging structure are provided, the chip anti-warping device comprises a base, at least two supporting pieces and a cover plate, the product packaging structure is fixedly placed above the base, the supporting pieces are respectively placed on two sides of the product packaging structure, the cover plate is covered on the upper surface of the product packaging structure, and the cover plate is carried and placed on the supporting pieces.
S5: and carrying out reflow soldering process on the product packaging structure fixedly loaded in the chip warpage preventing device.
In step S1, a test substrate 1 ' and a test stack chipset 2 ' are provided, where the test stack chipset 2 ' at least includes an upper test chip 21 ' and a lower test chip 22 ', and the lower test chip 22 ' is formed between the test substrate 1 ' and the upper test chip 21 ' to form a test package structure a ', which specifically includes:
as shown in fig. 2(a) - (c), a test substrate 1 'is provided, the upper surface of the test substrate 1' is provided with a plurality of electrical pads, the functional surface of the lower test chip 22 'is soldered to the upper surface of the test substrate 1' through the solder balls 6 by using a flip-chip ball bonding process, the lower test chip 22 'is electrically connected to the test substrate 1', the functional surface of the upper test chip 21 'is flip-chip bonded to the upper surface of the lower test chip 22' through the solder balls 6, and the upper test chip 21 'is electrically connected to the lower test chip 22'. In the embodiment, the lower test chip 22 'is preferably a TSV chip, the thickness of which may be selected to be 100 to 200 μm, the upper test chip 21' is another functional chip, the thickness of the chip may be selected according to actual design requirements, the solder ball 6 is a solder ball that can be melted at high temperature for soldering, and the solder ball is solid at normal temperature, so as to support the lower test chip 22 'and the upper test chip 21' to some extent.
Of course, this step also includes applying flux to the functional surfaces of the lower test chip 22 ' and the functional surfaces of the upper test chip 21 ', which is the prior art, and the present invention is not described herein in more detail, but it should be emphasized that in the embodiment of the present invention, a flux with high viscosity and good temperature resistance, such as resin-reactive flux, is used to prevent the risk of displacement between the upper test chip 21 ', the lower test chip 22 ' and the test substrate 1 ' during the reflow process.
In one embodiment of the present invention, the upper test chip 21 'is two chips soldered side by side to the lower test chip 22', as shown in fig. 2 (c). In other embodiments of the present invention, the upper test chip 21 'may also be a plurality of chips soldered side by side on the lower test chip 22', or a plurality of chips soldered in a stacked manner in a vertical direction, which may be set according to actual design requirements, and the present invention is not limited thereto.
In step S3, the testing of the soldering performance between the upper test chip 21 'and the lower test chip 22' after the reflow soldering process specifically includes:
testing the conductivity of the test package structure a ' after the step S2, specifically, testing the conductivity between the upper test chip 21 ' and the lower test chip 22 ', if there is electrical connection between the upper test chip 21 ' and the lower test chip 22 ', the test result is normal, and for each chip that is the same as the upper test chip 21 ' and the lower test chip 22 ', the process can be performed according to the steps S1-S2, the manufacturing process of chip soldering, assembling and reflowing again is performed first; if the result of the test of the electrical conduction performance between the upper test chip 21 'and the lower test chip 22' is an open circuit or a short circuit, step S4 is performed.
In another embodiment of the present invention, for the test package structure a ' after performing step S2, the soldering quality of the solder balls 6 may also be detected by using an X-Ray technique, specifically, the soldering quality of each solder ball 6 between the upper test chip 21 ' and the lower test chip 22 ' is checked, and whether the solder balls 6 after the reflow soldering process have voids, solder bridges, too large solder joints, insufficient solder joints, and the like is observed. Similarly, if the detection result is normal, the chips identical to the upper test chip 21 'and the lower test chip 22' can be manufactured according to the steps S1-S2, and the manufacturing process of chip soldering, assembling and reflowing are firstly performed; if it is detected that the solder ball 6 is abnormal, step S4 is performed.
Certainly, in other embodiments of the present invention, the conductivity of the package structure a' may also be detected, and the soldering quality of the solder balls 6 may also be detected by using the X-Ray technology, so as to ensure the accuracy of the soldering performance of the package structure. The method can be used for detecting the welding performance of the welding rod, and the specific technical means for detecting the welding performance is not limited.
In step S4, providing a product package structure a identical to the test package structure a', specifically including:
as shown in fig. 2(d), a substrate 1 identical to the test substrate 1 'and a stacked chip set 2 identical to the test stacked chip set 2' are provided, the stacked chip set 2 including at least an upper chip 21 identical to the upper test chip 21 'and a lower chip 22 identical to the lower test chip 22'.
The lower chip 22 is formed between the substrate 1 and the upper chip 21 to form a product packaging structure a, specifically, the upper surface of the substrate 1 is provided with a plurality of electrical pads, the functional surface of the lower chip 22 is soldered to the upper surface of the substrate 1 through solder balls 6 by using a flip-chip ball-bonding process, the electrical connection between the lower chip 22 and the substrate 1 is realized, the functional surface of the upper chip 21 is flip-chip bonded to the upper surface of the lower chip 22 through solder balls 6, and the electrical connection between the upper chip 21 and the lower chip 22 is realized. Here, the chip type selection of the upper chip 21 and the lower chip 22 and the specific arrangement of the upper chip 21 are the same as those in the test package structure a', and redundant description is omitted here. In fig. 2(d), a package structure in which the upper chip 21 is two chips soldered to the lower chip 22 side by side will be described as an example.
In step S4, a chip warpage preventing device is provided, and the product packaging structure a is fixedly disposed above the base 3, specifically including:
as shown in fig. 2(e), in the chip warpage preventing apparatus according to the embodiment of the invention, a substrate fixing member 7 is further provided, the product package structure a and the substrate fixing member 7 are placed above the base 3, the substrate fixing member 7 is at least placed at a diagonal of the substrate 1, two substrate fixing members 7 are respectively placed at two sides of a diagonal corner end of the substrate 1, and the substrate 1 is fixed by the two substrate fixing members 7 respectively placed at two sides of the diagonal corner end. Specifically, two substrate fixing parts 7 are respectively arranged on two sides of each corner end of two opposite corners of the substrate 1, and the substrate 1 is fixedly clamped in the substrate fixing parts 7 and used for fixing the substrate 1 in the subsequent packaging process.
In the embodiment of the present invention, the substrate fixing member 7 may be provided with a height slightly higher than the height of the upper surface of the substrate 1 to ensure that it can fix the substrate 1 better. However, the specific height of the substrate holder 7 is not limited herein, and it is only necessary that the height of the top end of the substrate holder 7 is lower than the height of the upper surface of the upper chip 21, and the substrate 1 can be held without interfering with the lower surface of the cover plate 5 placed above the upper chip 21 in the subsequent process.
Preferably, the substrate fixing member 7 is a Pin needle, but in some other embodiments of the present invention, the substrate fixing member 7 may be a fixing member made of some other high temperature resistant material, and may still fix the substrate 1 at a high temperature.
In some other embodiments of the present invention, the substrate 1 may be fixed on the base 3, and then the chip bonding process is performed on the upper surface of the substrate 1 to form the product package structure a, and the process sequence of the two processes is not limited herein.
In step S4, placing the supporting members 4 on two sides of the product packaging structure a, respectively, covering the cover plate 5 on the upper surface of the product packaging structure a, and placing the product packaging structure on the supporting members 4, specifically including:
as shown in fig. 2(f), the cover plate 5 is a rectangular silicon wafer, and the cover plate 5 is placed on the upper surface of the upper chip 21, i.e., the lower surface thereof is in contact with the upper surface of the upper chip 21, for applying a certain pressure to the upper chip 21, and the greater the weight thereof, the greater the pressure applied to the upper chip 21. The size of the cover plate 5 can be designed according to the specific arrangement mode of the upper chips 21, and preferably, the cover plate 5 is arranged to cover the upper surface of each upper chip 21 so as to ensure that the stress at each point of each upper chip 21 is uniform. The thickness of the cover plate 5 may be determined according to actual design requirements, and in the subsequent reflow process, the pressure applied by the cover plate 5 to the upper chip 21 may not only prevent the lower chip 22 from warping, but also ensure that the pressure applied to the upper chip 21 does not collapse the solder balls 6 while the effective soldering between the upper chip 21 and the lower chip 22 is not affected. Of course, in other embodiments, the material of the cover plate 5 may also be other high temperature resistant materials, such as glass sheets and the like.
As shown in fig. 2(g), the supporting member 4 disposed on one side of the base plate 1 according to the embodiment of the present invention includes a set of first supporting members 41 and two sets of second supporting members 42, the first supporting members 41 are disposed on two opposite sides of the cover plate 5 along the length direction, the two sets of second supporting members 42 are disposed on two opposite sides of the cover plate 5 along the width direction, and the first supporting members 41 and the second supporting members 42 disposed on the same side of the base plate 1 form a triangular structure on a plane.
Specifically, the tops of the first support 41 and the second support 42 are provided to be recessed inward toward the cover plate 5 side to form a step 43, and the height of the upper surface of the step 43 is made to be consistent with the height of the upper surface of the upper chip 21. The two ends of the cover plate 5 in the length direction are simultaneously placed on the upper surfaces of the steps 43 of the first support 41 and the second support 42, and the cover plate 5 can be fixedly clamped in the steps of the first support 41 and the second support 42. Thus, the step surfaces of the first supporters 41 disposed at the opposite sides of the cover plate 5 in the longitudinal direction fix the cover plate 5 in the longitudinal direction thereof, and the step surfaces of the second supporters 42 disposed at the opposite sides of the cover plate 5 in the width direction fix the cover plate 5 in the width direction thereof.
Preferably, the first supporting member 41 and the second supporting member 42 are Pin needles, but the material for manufacturing the first supporting member 41 and the second supporting member 42 is not limited in the present invention, and a material capable of resisting high temperature and having a certain supporting force at high temperature may be selected.
In some possible embodiments of the present invention, the chip warpage preventing apparatus is provided, wherein the first supporting member 41, the second supporting member 42 and the substrate fixing member 7 are movably fixed at any position on the base 3, the specific positions of the first supporting member 41 and the second supporting member 42 fixed on the base 3 can be determined according to the specific length of the cover plate 5 and the specific position of the cover plate 5 on the upper surface of the upper chip 21, and the steps of the first supporting member 41 and the second supporting member 42 disposed on both sides of the cover plate 5 can limit the movement of the cover plate 5 in the length direction and the width direction. The specific number and arrangement of the supporting members 4 provided for supporting and fixing the cover plate 5 are specifically adjusted according to the size of the cover plate 5, and the like. The specific position at which the substrate fixing member 7 is fixed to the base 3 is specifically adjusted according to the specific size of the substrate 1, and the substrate fixing members 7 placed on both sides of each of the two diagonal corners of the substrate 1 can restrict the movement of the substrate 1 in the longitudinal direction and the width direction thereof.
And finally, step S5, performing a reflow soldering process on the product package structure fixedly mounted in the provided chip warpage preventing device, wherein a certain pressure is applied to the upper chip 21 by the cover plate 5, and the movement of the upper chip 21 and the lower chip 22 in the horizontal direction at a high temperature can be relatively avoided, and the problem of soldering failure between the upper chip 21 and the lower chip 22 due to a large warpage of the lower chip 22 caused by temperature change in the reflow soldering process is prevented.
However, since the solder balls 6 are melted at a high temperature, the size, thickness and weight of the cover plate 5 are designed to be very important for the pressure applied to the upper chip 21 and the lower chip 22, and the bridging phenomenon is easily generated between the upper chip 21 and the lower chip 22 and between the lower chip 22 and the substrate 1 due to an excessive pressure, so that the size, thickness and weight of the cover plate 5 need to be selected very accurately, and the process difficulty is high.
Therefore, in step S4 of the method for manufacturing a package structure of the present invention, another structure of the chip anti-warpage device is provided, as shown in fig. 2(h), before the first supporting member 41 and the second supporting member 42 are fixed on the base 3, an elastic member 8 is installed at a partial region of the supporting member 4. Specifically, an elastic member 8 is mounted at the bottom end of each of the first supporting member 41 and the second supporting member 42, and the elastic member 8 can make the first supporting member 41 and the second supporting member 42 perform telescopic movement in the height direction thereof.
When the solder balls 6 are melted at high temperature, the supporting force of the solder balls 6 on the upper chip 21 and the lower chip 22 is reduced, and when the pressure of the cover plate 5 on the upper chip 21 and the lower chip 22 is greater than the supporting force of the solder balls 6 on the upper chip 21 and the lower chip 22 at high temperature, at this time, the elastic members 8 gradually contract, that is, the elastic members 8 move downward in the height direction thereof, and the supporting force of the elastic members 8 on the cover plate 5 is increased, so that the bridging phenomenon between the upper chip 21 and the lower chip 22 and between the lower chip 22 and the substrate 1 is avoided. Of course, in this embodiment, the weight of the cover plate 5 and the elastic strength of the elastic member 8 are designed differently according to different products, and the present invention is not limited thereto. In the chip warpage preventing device provided with the elastic part 8, the size, the thickness and the weight of the cover plate are selected without accurate control, so that the process difficulty is greatly reduced.
Of course, in the chip warpage preventing apparatus with the elastic member 8 mounted thereon, the elastic member 8 is not limited to be mounted on the bottom end of the supporting member 4, but may be fixedly mounted on the upper surface of the step 43 of each supporting member, and the cover plate 5 is placed over the elastic member 8 at both ends in the length direction thereof and is fixedly clamped in the step 43 of each supporting member. It should be noted that, when the elastic member 8 is mounted on the upper surface of the step 43 of each support member, the height of the upper surface of the step 43 is lower than that of the upper surface of the upper chip 21, and the height of the upper surface of the elastic member 8 mounted on the step 43 is required to be consistent with that of the upper surface of the upper chip 21.
Alternatively, in other possible embodiments of the present invention, the supporting member 4 is integrally supported as an elastic member, a circular hole corresponding to the size of the supporting member 4 is formed on the lower surface of the cover plate 5, and the top end of the supporting member 4 can be fixedly clamped in the circular hole to support and fix the cover plate 5.
The specific structural relationship among the support member 4, the elastic member 8 and the cover plate 5 in the chip warpage preventing device provided by the invention is not limited to this, and only the cover plate 5 needs to be supported and fixed, and the cover plate 5 can be moved in the height direction.
Step S5 is performed on the package structure fixedly mounted in the chip warpage preventing apparatus with the elastic element 8 as shown in fig. 2(h), the elastic element 8 mounted at the bottom end of the supporting element 4 can prevent the supporting force of the solder ball on the upper chip 21 and the lower chip 22 from decreasing due to the melting state of the solder ball at high temperature in the reflow process, and at this time, the elastic element 8 can exert a certain supporting force on the cover plate 5, thereby avoiding the bridging phenomenon between the upper chip 21 and the lower chip 22 and between the lower chip 22 and the substrate 1.
As shown in fig. 3 and 4, the invention further provides a chip warpage prevention device, which is applied to a manufacturing method of a package structure. In a 3D stacking project, the lower chip is thin, and the lower chip is likely to have large warpage at normal temperature or high temperature, and when the soldering performance between the chips cannot be ensured after the reflow soldering process is performed on the manufactured test packaging structure, the chip warpage prevention device provided by the invention needs to be used, and particularly when the size of the upper chip is small, the pressure on the lower chip cannot inhibit the lower chip from warping, which easily causes the problem of soldering failure between the upper chip and the lower chip. Therefore, the chip anti-warping device provided by the invention is applied to the condition that the upper chip is small in size and light in weight.
The chip warpage preventing device provided in an embodiment of the invention comprises a base 3 and at least two supporting members 4 arranged on the base 3, wherein the base 3 is used for placing a substrate 1 and a stacked chip group 2 arranged on the substrate 1.
The stacked chip group 2 includes at least an upper chip 21 and a lower chip 22, and the lower chip 22 is disposed between the substrate 1 and the upper chip 21. The lower chip 22 is preferably a TSV chip, the thickness of the TSV chip can be selected to be 100-200 μm, the upper chip 21 is other functional chips, and the thickness of the TSV chip can be selected according to actual design requirements. In one embodiment of the present invention, the upper die 21 is two dies soldered side by side to the lower die 22, as shown in the figure. Of course, in other embodiments of the present invention, the upper chip 21 may be a plurality of chips soldered to the lower chip 22 side by side, or a plurality of chips soldered in a stacked manner in a vertical direction, and the present invention is not limited herein, and the following description will be given by taking as an example a package structure in which the upper chip 21 is two chips soldered to the lower chip 22 side by side.
Specifically, the lower chip 22 has a functional surface provided with a pad and a non-functional surface opposite to the functional surface, the functional surface of the lower chip 22 is disposed toward the substrate 1, flip-chip bonded to the upper surface of the substrate 1 through a solder ball 6, and electrically connected to the substrate 1. Similarly, the upper chip 21 has a functional surface provided with pads and a non-functional surface opposite to the functional surface, the functional surface of the upper chip 21 is disposed toward the lower chip 22, flip-chip bonded to the upper surface of the lower chip 22 through solder balls 6, and electrically connected to the lower chip 22. In this embodiment, the solder balls 6 are specifically solder balls, which are melted at high temperature for soldering, and are solid at normal temperature, and play a certain role in supporting the lower chip 22 and the upper chip 21.
The supporting members 4 are respectively disposed on two sides of the substrate 1, the chip warpage preventing apparatus further includes a cover plate 5, and the cover plate 5 covers the upper surface of the upper chip 21 and is mounted on the supporting members 4. Specifically, the cover plate 5 is a rectangular silicon wafer, the lower surface of which is in contact with the upper surface of the upper chip 21, and is used for applying a certain pressure to the upper chip 21, and the larger the weight of the cover plate is, the larger the pressure applied to the upper chip 21 is. The size of the cover plate 5 can be designed according to the specific arrangement mode of the upper chips 21, and preferably, the cover plate 5 is arranged to cover the upper surface of each upper chip 21 so as to ensure that the stress of each point of each upper chip 21 is uniform. The thickness of the cover plate 5 may be determined according to actual design requirements, and in the subsequent reflow process, the pressure applied by the cover plate 5 to the upper chip 21 may not only prevent the lower chip 22 from warping, and may not affect the effective soldering between the upper chip 21 and the lower chip 22, but also ensure that the pressure applied by the cover plate 5 to the upper chip 21 does not collapse the solder balls 6. Of course, in other embodiments, the material of the cover plate 5 may also be other high temperature resistant materials, such as glass sheets and the like.
Specifically, the supporting members 4 disposed on both sides of the base plate 1 include a first supporting member 41 and a second supporting member 42, the first supporting member 41 is disposed on opposite sides of the cover plate 5 along the length direction, and the second supporting member 42 is disposed on opposite sides of the cover plate 5 along the width direction.
The supporting members 4 disposed on one side of the substrate 1 include a set of first supporting members 41 and two sets of second supporting members 42, the two sets of second supporting members 42 are respectively disposed on two opposite sides of the cover plate 5 along the width direction, and the first supporting members 41 and the second supporting members 42 located on the same side of the substrate 1 form a triangular structure on a plane.
More specifically, the tops of the first support 41 and the second support 42 are recessed inward toward the cover plate 5 to form a step 43, the height of the upper surface of the step 43 is consistent with the height of the upper surface of the upper chip 21, the two ends of the cover plate 5 in the length direction are simultaneously mounted on the upper surfaces of the steps 43 of the first support 41 and the second support 42, and the cover plate 5 is fixedly clamped in the steps of the first support 41 and the second support 42. That is, the step surfaces of the first supporters 41 located at opposite sides in the length direction of the cover plate 5 fix the cover plate 5 in the length direction thereof, and the step surfaces of the second supporters 42 located at opposite sides in the width direction of the cover plate 5 fix the cover plate 5 in the width direction thereof.
In the embodiment of the present invention, the first supporting member 41 and the second supporting member 42 are Pin needles, but the material for manufacturing the first supporting member 41 and the second supporting member 42 is not limited in the present invention, and the material capable of resisting high temperature and having a certain supporting force at high temperature may be selected.
Furthermore, the chip warpage preventing device still includes base plate mounting 7, and base plate mounting 7 sets up in base 3 top, and base plate mounting 7 sets up in 1 diagonal of base plate at least, is provided with two base plate mounting 7 respectively in the corner end both sides at 1 diagonal of base plate, and base plate 1 fixed joint is in base plate mounting 7. In the present embodiment, two substrate fixing members 7 are respectively disposed on two sides of each corner end of two opposite corners of the substrate 1, so as to fix the substrate 1 in the subsequent packaging process.
Specifically, the height of the top end of the substrate fixing member 7 may be slightly higher than the height of the upper surface of the substrate 1, so as to ensure that the substrate fixing member can fix the substrate 1 better. However, the specific height of the substrate holder 7 is not limited in the present invention, and it is only necessary that the height of the tip of the substrate holder 7 is lower than the height of the upper surface of the step 43, and the substrate 1 can be held without interfering with the lower surface of the cover plate 5.
The substrate fixing member 7 is also a Pin needle, but of course, in other embodiments of the present invention, the substrate fixing member 7 may also be a fixing member made of other high temperature resistant materials, and can still fix the substrate 1 at high temperature.
In some possible embodiments of the present invention, the first supporting member 41, the second supporting member 42 and the substrate fixing member 7 may be movably fixed at any position on the base, the specific position where the first supporting member 41 and the second supporting member 42 are fixed on the base 3 may be determined according to the specific length of the cover plate 5 and the specific position where the cover plate is placed on the upper surface of the upper chip 21, and the steps of the first supporting member 41 and the second supporting member 42 located at both sides of the cover plate 5 may limit the movement of the cover plate 5 in the length direction and the width direction thereof. The specific number and arrangement of the supporting members 4 provided for supporting and fixing the cover plate 5 are specifically adjusted according to the size of the cover plate 5 and the like. The specific position of the substrate fixing member 7 fixed on the base 3 may be determined according to the specific size of the substrate 1, and the substrate fixing members 7 located at both sides of each of the two opposite corners of the substrate 1 may limit the movement of the substrate 1 in the length direction and the width direction thereof.
At normal temperature, since the solder balls 6 are solid and can support the pressure of the cover plate 5 on the upper chip 21 and the lower chip 22, and at high temperature, the solder balls 6 will be in a molten state with the temperature rise, the size, thickness and weight of the cover plate 5 are very important for the pressure applied to the upper chip 21 and the lower chip 22, and the bridging phenomenon between the upper chip 21 and the lower chip 22 and between the lower chip 22 and the substrate 1 is easily caused by the excessive pressure, so the selection of the size, thickness and weight of the cover plate 5 in the chip warpage preventing device in the above embodiment needs to be very precise, and the process difficulty is large.
Fig. 5 shows a chip warpage preventing apparatus according to another embodiment of the present invention, which is different from the structure shown in fig. 3, in order to prevent the solder balls 6 on the lower surfaces of the upper chip 21 and the lower chip 22 from melting at a high temperature to cause the bridging phenomenon between the upper chip 21 and the lower chip 22, and between the lower chip 22 and the substrate 1, an elastic member 8 is disposed on a partial region of the supporting member 4, and the elastic member 8 can make the supporting member 4 perform a stretching motion in the height direction thereof, specifically, the elastic member 8 is disposed at the bottom end of the supporting member 4, that is, the bottom ends of the first supporting member 41 and the second supporting member 42 are both provided with the elastic member 8. Since the solder balls 6 are melted at high temperature, the supporting force for the upper chip 21 and the lower chip 22 is reduced, when the pressure of the cover plate 5 on the upper chip 21 and the lower chip 22 is greater than the supporting force of the solder balls 6 on the upper chip 21 and the lower chip 22 at high temperature, at this time, the elastic members 8 gradually contract, that is, the elastic members 8 move downward in the height direction thereof, and the supporting force of the elastic members 8 on the cover plate 5 rises, so that the bridging phenomenon between the upper chip 21 and the lower chip 22 and between the lower chip 22 and the substrate 1 is avoided. In this embodiment, the weight of the cover plate 5 and the elastic strength of the elastic member 8 are designed differently according to different products, and the present invention is not limited thereto.
Of course, the elastic member 8 is not limited to be disposed at the bottom end of the supporting member 4, and it can also be fixedly disposed on the upper surface of the step 43 of each supporting member, and the cover plate 5 is placed above the elastic member 8 at both ends in the length direction and is fixedly clamped in the step 43 of each supporting member. It should be noted that, when the elastic element 8 is disposed on the upper surface of the step 43 of each support, the height of the upper surface of the step 43 is lower than the height of the upper surface of the upper chip 21, and the height of the upper surface of the elastic element 8 disposed on the step 43 is required to be consistent with the height of the upper surface of the upper chip 21.
Alternatively, in other possible embodiments of the present invention, the supporting member 4 is an elastic member, the lower surface of the cover plate 5 is provided with a circular hole corresponding to the size of the supporting member 4, and the top end of the supporting member 4 can be fixedly clamped in the circular hole to support and fix the cover plate 5.
The present invention is not limited to this for the specific structural relationship among the support member 4, the elastic member 8, and the cover plate 5, and only needs to be able to support and fix the cover plate 5, and to be able to move the cover plate 5 in its height direction.
In summary, in the invention, the reflow soldering process is performed on the formed test package structure at one time, and if the soldering performance of the test package structure is normal after the reflow soldering process, the same chips in the subsequent product manufacturing process as those in the test package structure can all adopt the manufacturing process of soldering first and then reflowing; however, when the soldering performance of the test packaging structure fails after the reflow soldering process, the product packaging structure which is the same as the test packaging structure is fixedly installed in the chip warpage preventing device provided by the invention in the subsequent product manufacturing process, and then the reflow soldering process is performed, so that even if the upper chip is small in size and light in weight, the upper chip is pressed by using the weight of the cover plate, the lower chip of the chip packaging structure can be well restrained from warping to a greater extent in the reflow soldering process, the situation that the soldering problem occurs between the upper chip and the lower chip is prevented, and the 3D packaging soldering quality is improved.
It should be understood that although the present description refers to embodiments, not every embodiment contains only a single technical solution, and such description is for clarity only, and those skilled in the art should make the description as a whole, and the technical solutions in the embodiments can also be combined appropriately to form other embodiments understood by those skilled in the art.
The above-listed detailed description is only a specific description of a possible embodiment of the present invention, and they are not intended to limit the scope of the present invention, and equivalent embodiments or modifications made without departing from the technical spirit of the present invention should be included in the scope of the present invention.

Claims (16)

1. A manufacturing method of a package structure is characterized by comprising the following steps:
providing a test substrate and a test stacking chip set, wherein the test stacking chip set at least comprises an upper test chip and a lower test chip, and the lower test chip is formed between the test substrate and the upper test chip to form a test packaging structure;
carrying out a reflow soldering process on the test packaging structure;
testing the welding performance between the upper test chip and the lower test chip after the reflow soldering process;
when the welding performance fails, providing a chip anti-warping device and a product packaging structure which is the same as the test packaging structure, wherein the chip anti-warping device comprises a base, at least two supporting pieces and a cover plate, the product packaging structure is fixedly placed above the base, the supporting pieces are respectively placed on two sides of the product packaging structure, and the cover plate is covered on the upper surface of the product packaging structure and is placed on the supporting pieces in a carrying manner;
and carrying out reflow soldering process on the product packaging structure fixedly loaded in the chip warpage preventing device.
2. The method for manufacturing the package structure according to claim 1, wherein the forming the lower test chip between the test substrate and the upper test chip forms a test package structure, and specifically comprises:
flip-chip bonding the functional surface of the lower test chip to the upper surface of the test substrate through solder balls;
and flip-chip bonding the functional surface of the upper test chip to the upper surface of the lower test chip through solder balls.
3. The method for manufacturing the package structure according to claim 2, wherein the testing of the soldering performance between the upper test chip and the lower test chip in the package structure after the reflow soldering process specifically comprises:
testing the conductivity between the upper test chip and the lower test chip;
and detecting the welding quality of the solder ball by using an X-Ray technology.
4. The method for manufacturing the package structure according to claim 3, wherein the providing of the product package structure identical to the test package structure specifically includes:
providing a substrate identical to the test substrate and a stacked chip set identical to the test stacked chip set, the stacked chip set including at least an upper chip identical to the upper test chip and a lower chip identical to the lower test chip;
and forming the lower chip between the substrate and the upper chip to form a product packaging structure.
5. The method for manufacturing the package structure according to claim 4, wherein the step of fixedly placing the product package structure above the base specifically comprises:
the device also comprises a substrate fixing piece, wherein the substrate fixing piece is placed above the base;
and fixedly clamping the substrate in the substrate fixing piece.
6. The method for manufacturing the package structure according to claim 5, wherein the steps of placing the supporting members at two sides of the product package structure, covering the cover plate on the upper surface of the product package structure, and placing the cover plate on the supporting members include:
the supporting pieces arranged on one side of the base plate comprise a group of first supporting pieces and two groups of second supporting pieces, the first supporting pieces are arranged on two opposite sides of the cover plate along the length direction, the two groups of second supporting pieces are arranged on two opposite sides of the cover plate along the width direction, and the first supporting pieces and the second supporting pieces arranged on the same side of the base plate form a triangular structure on the plane;
and covering the cover plate on the upper surface of the upper chip, and carrying and placing the cover plate on the first supporting piece and the second supporting piece simultaneously.
7. The method of claim 6, further comprising:
the top parts of the first supporting piece and the second supporting piece are inwards sunken towards one side of the cover plate to form a step, the height of the upper surface of the step is consistent with that of the upper surface of the upper chip, two ends of the cover plate in the length direction are simultaneously placed on the upper surfaces of the step of the first supporting piece and the step of the second supporting piece in a carrying mode, and the cover plate is fixedly clamped in the steps of the first supporting piece and the second supporting piece.
8. The method for fabricating the package structure according to any one of claims 1 to 7, further comprising:
and an elastic piece is arranged at a part of the support part, and the elastic piece can enable the support part to perform telescopic movement in the height direction.
9. A chip anti-warping device is characterized in that,
the chip warping prevention device comprises a base and at least two supporting pieces arranged on the base, wherein the base is used for placing a substrate and a stacked chip group arranged on the substrate, the stacked chip group at least comprises an upper chip and a lower chip, the lower chip is arranged between the substrate and the upper chip, and the supporting pieces are respectively arranged on two sides of the substrate;
the device also comprises a cover plate, wherein the cover plate is covered on the upper surface of the upper chip and is arranged on the supporting piece in a carrying way.
10. The device of claim 9, wherein the supporting members disposed on two sides of the substrate comprise a first supporting member and a second supporting member, the first supporting member is disposed on two opposite sides of the cover plate along the length direction, and the second supporting member is disposed on two opposite sides of the cover plate along the width direction.
11. The device of claim 10, wherein the supporting members disposed on one side of the substrate include a set of first supporting members and two sets of second supporting members, the two sets of second supporting members are disposed on two opposite sides of the cover plate along the width direction, and the first supporting members and the second supporting members on the same side of the substrate form a triangular structure on a plane.
12. The chip warpage preventing device of claim 11, wherein the top of the first support and the second support are recessed inward toward the substrate to form a step, the height of the upper surface of the step is consistent with the height of the upper surface of the upper chip, the cover plates are mounted on the upper surfaces of the first support and the second support at two ends of the cover plates in the length direction, and the cover plates are fixedly clamped in the steps of the first support and the second support.
13. The device of claim 12, wherein the functional surface of the lower chip is flip-chip bonded to the upper surface of the substrate by solder balls, and the functional surface of the upper chip is flip-chip bonded to the upper surface of the lower chip by solder balls.
14. The chip warpage preventing device of claim 13, further comprising a substrate fixing member disposed above the base, the substrate fixing member being fixedly engaged in the substrate fixing member.
15. The chip anti-warpage device of claim 14, wherein the top height of the substrate holder is lower than the height of the upper surface of the step.
16. The device of any one of claims 9 to 15, wherein the support member is provided with a resilient member in a partial region thereof, the resilient member being adapted to allow the support member to perform a telescopic movement in a height direction thereof.
CN202210863313.4A 2022-07-21 2022-07-21 Packaging structure manufacturing method and chip anti-warping device Pending CN115101434A (en)

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