CN115097288A - DFT reset circuit, reset device and reset method - Google Patents

Abstract

The invention discloses a DFT reset circuit, a reset device and a reset method, relates to the technical field of digital circuits, and aims to reduce occupation of functional pins on a chip when a logic unit to be tested is reset and managed in DFT test. The DFT reset circuit includes: a scanning signal providing unit and a reset signal providing unit. The output end of the scanning signal providing unit is electrically connected with the scanning input end of the logic unit to be tested through the reset signal providing unit, and the output end of the reset signal providing unit is electrically connected with the reset end of the logic unit to be tested. The scan signal providing unit includes a scan pin, and the scan signal providing unit is configured to provide a first scan output signal to the reset signal providing unit according to a scan input signal provided by the scan pin. The reset signal providing unit is used for respectively providing a second scanning output signal to the scanning input end of the logic unit to be tested according to the first scanning output signal and providing a first reset signal to the reset end of the logic unit to be tested.

Description

DFT reset circuit, reset device and reset method

Technical Field

The present invention relates to the field of digital circuits, and in particular, to a DFT reset circuit, a DFT reset device, and a DFT reset method.

Background

At present, with the high-speed development of integrated circuits, the chip integration level is higher and higher, which leads to the logic scale and the working mode being more and more complex, and the Design for test (DFT) based on the chip level is more and more important.

SCAN scanning is one of the most important means in existing DFT test schemes. When the SCAN test is performed, a plurality of functional pins on the chip need to be multiplexed to apply corresponding excitation to the logic unit to be tested. However, the number of functional pins on the chip is limited, which may result in insufficient functional pins on the chip when more test channels are needed.

Disclosure of Invention

The invention aims to provide a DFT reset circuit, a reset device and a reset method, which are used for reducing occupation of functional pins on a chip when a logic unit to be tested is subjected to reset management in a DFT test.

In a first aspect, the present invention provides a DFT reset circuit for performing reset management on a logic unit to be tested of a chip, including: a scanning signal providing unit and a reset signal providing unit. The output end of the scanning signal providing unit is electrically connected with the scanning input end of the logic unit to be tested through the reset signal providing unit, and the output end of the reset signal providing unit is electrically connected with the reset end of the logic unit to be tested. The scan signal providing unit includes a scan pin, and the scan signal providing unit is configured to provide a first scan output signal to the reset signal providing unit according to a scan input signal provided by the scan pin. The reset signal providing unit is used for respectively providing a second scanning output signal to the scanning input end of the logic unit to be tested according to the first scanning output signal and providing a first reset signal to the reset end of the logic unit to be tested.

Compared with the prior art, in the DFT reset circuit provided by the invention, the output end of the scanning signal providing unit is electrically connected with the scanning input end of the logic unit to be tested through the reset signal providing unit, the output end of the reset signal providing unit is electrically connected with the reset end of the logic unit to be tested, and the scanning signal providing unit comprises a scanning pin. Therefore, in the DFT reset circuit provided by the present invention, the scan signal providing unit can provide the first scan output signal to the reset signal providing unit only according to the scan input signal provided by the scan pin, and then under the action of the first scan output signal, the reset signal providing unit can provide the second scan output signal to the scan input terminal of the logic unit to be tested according to the first scan output signal, so as to complete the logic function test of the logic unit to be tested, and can also provide the first reset signal to the reset terminal of the logic unit to be tested, so as to complete the management of the reset test of the logic unit to be tested. In the DFT reset circuit, in the DFT test, the function of replacing the reset pin of the chip by the reset signal providing unit is utilized, so that when the chip is subjected to logic test, a chip functional pin does not need to be occupied specially as the providing pin of the reset signal, and the pin resource of the chip is saved. Therefore, other chip functional pins can be arranged at the position of the pin for providing the reset signal in the prior art, and the problem that the functional pins on the chip are not enough can be solved to a certain extent.

In a second aspect, the present invention further provides a reset apparatus, including the DFT reset circuit provided in the first aspect.

Compared with the prior art, the reset device provided by the invention has the same beneficial effect as the DFT reset circuit in the technical scheme, and the detailed description is omitted here.

In a third aspect, the present invention further provides a reset method, which is applied to the DFT reset circuit provided in the first aspect, and the reset method includes:

the scan signal providing unit provides a first scan output signal to the reset signal providing unit according to a scan input signal provided by the scan pin.

In response to the first scan output signal, the reset signal providing unit provides a second scan output signal to the scan input terminal of the logic unit to be tested, and provides a first reset signal to the reset terminal of the logic unit to be tested.

Compared with the prior art, the beneficial effects of the reset method provided by the invention are the same as those of the DFT reset circuit in the technical scheme, and are not repeated here.

Drawings

The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the invention and not to limit the invention. In the drawings:

FIG. 1 is a diagram of a DFT reset circuit in the prior art;

FIG. 2 is a diagram of a DFT reset circuit in an embodiment of the invention.

Reference numerals:

11-a scan signal terminal, 12-an external function logic signal terminal,

13-reset signal terminal, 14-external test signal terminal,

15-scan enable signal terminal, 16-scan signal output terminal,

2-the logic unit under test, 31-the scan signal providing unit,

32-a reset signal supply unit, 321-a serial register,

3221-or gate, 3231-data selector,

33-a scanning signal output unit.

Detailed Description

In order to facilitate clear description of technical solutions of the embodiments of the present invention, in the embodiments of the present invention, words such as "first" and "second" are used to distinguish identical items or similar items with substantially the same functions and actions. For example, the first threshold and the second threshold are only used for distinguishing different thresholds, and the sequence order of the thresholds is not limited. Those skilled in the art will appreciate that the terms "first," "second," and the like do not denote any order or importance, but rather the terms "first," "second," and the like do not denote any order or importance.

It is to be understood that the terms "exemplary" or "such as" are used herein to mean serving as an example, instance, or illustration. Any embodiment or design described herein as "exemplary" or "e.g.," is not necessarily to be construed as preferred or advantageous over other embodiments or designs. Rather, use of the word "exemplary" or "such as" is intended to present concepts related in a concrete fashion.

In the present invention, "at least one" means one or more, "a plurality" means two or more. "and/or" describes the association relationship of the associated objects, meaning that there may be three relationships, e.g., a and/or B, which may mean: a exists alone, A and B exist simultaneously, and B exists alone, wherein A and B can be singular or plural. The character "/" generally indicates that the former and latter associated objects are in an "or" relationship. "at least one of the following" or similar expressions refer to any combination of these items, including any combination of the singular or plural items. For example, at least one (one) of a, b, or c, may represent: a, b, c, a and b combination, a and c combination, b and c combination, or a, b and c combination, wherein a, b and c can be single or multiple.

Fig. 1 shows a diagram of a DFT reset circuit in the prior art, and as shown in fig. 1, the DFT reset circuit in the prior art occupies at least three functional pins of a chip. The first chip function PIN, i.e. the scanning PIN0 in the figure, and the scanning PIN0 are electrically connected to the scanning input terminal SI of the logic unit 2 to be tested sequentially through the first silicon chip PIN PAD0 and the scanning signal terminal 11, so as to provide a scanning input signal to the logic unit 2 to be tested. The second chip functional PIN, i.e. the output PIN1 in the figure, is used to shift out the scan signal input to the logic unit 2 to be tested, so as to test the functional logic of the logic unit 2 to be tested. The third chip functional PIN is a reset PIN2 in the drawing, the reset PIN2 is directly electrically connected to the reset signal terminal 13 through the third silicon chip PIN PAD2, and different reset signal levels are provided to the reset signal terminal 13 through the third chip functional PIN, that is, an input signal of the reset signal terminal 13 is provided by the third chip functional PIN, and finally, a reset signal logic "0" or a reset signal logic "1" is provided to the reset terminal CDN of the logic unit 2 to be tested through the reset signal terminal 13.

When the scheme is adopted to carry out reset test on the logic unit 2 to be tested in the DFT test, at least three chip functional pins are required to be occupied, and the functional pins of the chip are insufficient under the premise that the number of the chip functional pins is limited.

In order to solve the above problems, the present invention provides a DFT reset circuit for performing reset management on a logic unit 2 to be tested of a chip, including: a scanning signal supply unit 31 and a reset signal supply unit 32. The output end of the scan signal providing unit 31 is electrically connected to the scan input end SI of the logic unit to be tested 2 through the reset signal providing unit 32, and the output end of the reset signal providing unit 32 is electrically connected to the reset end CDN of the logic unit to be tested 2. The scan signal providing unit 31 includes a scan PIN0, and the scan signal providing unit 31 is configured to provide a first scan output signal to the reset signal providing unit 32 according to a scan input signal provided by a scan PIN 0. The reset signal providing unit 32 is configured to provide a second scan output signal to the scan input end SI of the logic unit 2 to be tested according to the first scan output signal, and provide a first reset signal to the reset end CDN of the logic unit 2 to be tested.

In the specific implementation: the scan signal supply unit 31 supplies a first scan output signal to the reset signal supply unit 32 according to a scan input signal supplied from the scan PIN 0. The reset signal providing unit 32 generates a second scan output signal according to the first scan output signal, and transmits the second scan output signal to the scan input terminal SI of the logic unit 2 to be tested. The reset signal providing unit 32 further generates a first reset signal according to the first scan output signal, and transmits the first reset signal to the reset end CDN of the logic unit to be tested 2.

The structure and the implementation of the DFT reset circuit can be known as follows: the output end of the scan signal providing unit 31 is electrically connected to the scan input end SI of the logic unit 2 to be tested through the reset signal providing unit 32, the output end of the reset signal providing unit 32 is electrically connected to the reset end CDN of the logic unit 2 to be tested, and the scan signal providing unit 31 includes a scan PIN 0. Based on this, in the DFT reset circuit provided in the embodiment of the invention, the scan signal providing unit 31 can provide the first scan output signal to the reset signal providing unit 32 only according to the scan input signal provided by the scan PIN0, and then under the action of the first scan output signal, the reset signal providing unit 32 can not only provide the second scan output signal to the scan input SI of the logic unit under test 2 according to the first scan output signal to complete the logic function test of the logic unit under test 2, but also can provide the first reset signal to the reset terminal CDN of the logic unit under test 2 to complete the management of the reset test for the logic unit under test 2. In the prior art, not only the scan input signal needs to be provided by the scan PIN to perform the functional logic test of the logic unit to be tested, but also the reset signal needs to be provided by the reset PIN to perform the management of the reset test of the logic unit to be tested, and in the DFT reset circuit provided by the embodiment of the invention, the function of replacing the reset PIN2 of the chip by the reset signal providing unit 32 is used in the DFT test, so that when the logic test is performed on the chip, a chip functional PIN does not need to be occupied specially as the providing PIN of the reset signal, thereby saving the PIN resources of the chip. Therefore, other chip functional pins can be arranged at the position of the pin for providing the reset signal in the prior art, and the problem that the functional pins on the chip are not enough can be solved to a certain extent.

In one possible implementation, the reset signal providing unit 32 includes a reset signal generating module, a selecting module, and a reset signal outputting module. The output end of the scan signal providing unit 31 is electrically connected to the scan input end SI of the reset signal generating module, and is configured to provide a first scan output signal to the reset signal generating module, and the output end of the reset signal generating module is electrically connected to the scan input end SI of the logic unit to be tested 2, and is configured to provide a second scan output signal to the scan input end SI of the logic unit to be tested 2 according to the first scan output signal. The output end of the reset signal generation module is also electrically connected with the input end of the selection module, the output end of the selection module is electrically connected with the input end of the reset signal output module, and the selection module is used for providing a second reset signal for the reset signal output module under the action of the second scanning output signal. The reset signal output module is electrically connected with the reset end CDN of the logic unit to be tested 2, and is configured to provide a first reset signal to the reset end CDN of the logic unit to be tested 2 according to a second reset signal.

In specific implementation, the first scan output signal provided by the scan signal providing unit 31 is transmitted to the reset signal generating module, and the reset signal generating module generates the second scan output signal according to the scan input signal, and directly transmits the second scan output signal to the scan input terminal SI of the logic unit to be tested 2. Meanwhile, the reset signal generation module can also transmit the second scanning output signal to the selection module, the selection module generates a second reset signal according to the second scanning output signal and transmits the second reset signal to the reset signal output module, and the reset signal output module transmits the first reset signal to the reset end CDN of the logic unit to be tested 2 after generating the first reset signal according to the second reset signal, so as to complete reset management of the logic unit to be tested 2.

In some embodiments, the reset signal generation module includes a daisy chain register 321. The output end of the scan signal providing unit 31 is electrically connected to the scan input end SI of the serial register 321, and the output end of the serial register 321 is electrically connected to the scan input end SI of the logic unit to be tested 2 and the input end of the selection module, respectively, and is configured to provide a second scan output signal to the scan input end SI of the logic unit to be tested 2 and the selection module according to the first scan output signal. The output of the daisy-chain register 321 is also electrically connected to the data input D of the daisy-chain register 321.

Accordingly, after receiving the first scan output signal, the scan input SI of the serial register 321 transmits the first scan output signal to the output Q of the serial register 321, and transmits the first scan output signal to the data input D of the serial register 321. Then, according to practical situations, a signal received by the data input end D of the serial register 321 is transmitted to the output end Q, or a signal received by the scan input end SI of the serial register 321 is transmitted to the output end Q, so as to provide a second scan output signal to the scan input end SI of the logic unit 2 to be tested and the selection module.

In some embodiments, the selection module includes an or gate 3221 and a scan enable signal terminal 15. An output terminal of the reset signal generating module is electrically connected to a first input terminal of the or gate 3221 and is configured to provide a second scan output signal to the or gate 3221, and a scan enable signal terminal 15 is electrically connected to a second input terminal of the or gate 3221 and is configured to provide a scan enable signal to the or gate 3221. An output terminal of the or gate 3221 is electrically connected to the input terminal of the reset signal output module, and the or gate 3221 is configured to provide a second reset signal to the reset signal output module according to the second scan output signal and the scan enable signal. The scan enable signal terminal 15 is further electrically connected to a scan enable terminal SE of the logic unit 2 to be tested, and is configured to provide a scan enable signal to the scan enable terminal SE of the logic unit 2 to be tested.

In practical applications, the scan enable signal terminal 15 is further electrically connected to a scan enable terminal SE of the serial chain register 321 for providing a scan enable signal to the serial chain register 321. In the shift stage, the scan enable signal is a signal "1", the serial register 321 transmits the first scan output signal received by the scan input terminal SI to the or gate 3221 and the logic unit 2 to be tested under the action of the signal "1", based on the logic of the or gate 3221, the second reset signal provided by the or gate 3221 to the reset signal output module is the signal "1", and the logic unit 2 to be tested selects to store the second scan output signal received by the scan input terminal SI in the register under the condition that the scan enable signal is the signal "1". In the capture phase, the scan enable signal is a signal "0", the serial link register 321 transmits the signal received by the data input end D to the or gate 3221 and the logic unit 2 to be tested under the action of the signal "0", at this time, the second reset signal provided by the or gate 3221 to the reset signal output module depends on the output signal of the serial link register 321, when the output signal of the serial link register 321 is the signal "0", the second reset signal is a signal "0", and when the output signal of the serial link register 321 is the signal "1", the second reset signal is a signal "1".

In some embodiments, the reset signal output module includes a data selector 3231 and a reset signal terminal 13. A first input end I0 of the data selector 3231 is electrically connected to the external functional logic signal terminal 12, a second input end I1 of the data selector 3231 is electrically connected to the output end of the selection module through the reset signal terminal 13, the selection terminal S of the data selector 3231 is electrically connected to the external test signal terminal 14, and an output end Z of the data selector 3231 is electrically connected to the reset terminal CDN of the logic unit to be tested 2, and is configured to provide a first reset signal to the reset terminal CDN of the logic unit to be tested 2.

In practice, in DFT test mode, the output signal of external test signal terminal 14 is signal "1", and in the selection of this signal, data selector 3231 selects and outputs the signal received by second input terminal I1, i.e. the second reset signal output by or gate 3221.

As can be seen from the above, in the shift stage, the second reset signal provided by or gate 3221 to data selector 3231 is signal "1", and the first reset signal output by data selector 3231 is also signal "1", which satisfies that the logic unit 2 to be tested is not reset in the shift stage, thereby ensuring the accuracy of the shift.

During the capture phase, the second reset signal provided by or gate 3221 to data selector 3231 may be signal "1" or signal "0", depending on the output signal of daisy chain register 321. If a reset condition needs to be tested, the signal "0" is shifted to the chain register 321, and finally the signal "0" is captured from the data input D to the output Q of the chain register 321. If a test for a no-reset condition is required, signal "1" is shifted into the chain register 321, and finally signal "0" is captured from the data input D to the output Q of the chain register 321.

In one possible implementation manner, the scan signal providing unit 31 further includes a first silicon PAD0 and a scan signal terminal 11. The scan PIN0, the first silicon chip PIN PAD0, and the scan signal terminal 11 are electrically connected in sequence, and an output terminal of the scan signal terminal 11 is electrically connected to the reset signal providing unit 32.

Based on this, when the scan input signal provided by the scan PIN0 is the signal "1", then the first scan output signal output by the scan signal providing unit 31 according to the signal "1" is also the signal "1"; when the scan input signal supplied from the scan PIN0 is the signal "0", the first scan output signal outputted from the scan signal supply unit 31 according to the signal "0" is also the signal "0".

In practice, the first silicon PAD0 has three input/output terminals, I terminal, C terminal, and PAD terminal, and an output enable OEN terminal for controlling the first silicon PAD0 to be in an output mode or an input mode. When the output enable OEN terminal is electrically connected with the signal '1', the first silicon chip pin PAD0 is in an input mode, namely, the signal is received from the PAD terminal, and the signal is output from the C terminal; when the output enable OEN terminal is electrically connected to the signal "0", the first die PAD0 is in output mode, i.e., receives a signal from the I terminal and outputs a signal from the PAD terminal.

Further, the DFT reset circuit further includes a scan signal output unit 33, where the scan signal output unit 33 is electrically connected to the output end Q of the logic unit 2 to be tested, and is used to output a third scan output signal of the logic unit 2 to be tested, where the third scan output signal is generated after the second scan output signal passes through the logic unit 2 to be tested. The scan signal output unit 33 includes an output PIN1, a second silicon chip PIN PAD1, and a scan signal output terminal 16. The output end of the logic unit 2 to be tested, the scanning signal output end 16, the second silicon chip PIN PAD1 and the output PIN PIN1 are electrically connected in sequence.

Based on this, in the shift stage, the scan enable signal is signal "1", the scan input signal provided by the scan PIN0 is consistent with the first scan output signal, the serial register 321 selects to store the first scan output signal received by the scan input terminal SI in the serial register 321 under the action of signal "1", finally the first scan output signal is transmitted to the output terminal Q of the serial register 321 and then to the scan input terminal SI of the logic unit to be tested 2, and after receiving the second scan output signal, the logic unit to be tested 2 outputs the third scan output signal to the scan signal output unit 33, so as to complete the shift test on the logic unit to be tested 2.

In the above embodiment, the DFT reset circuit further includes a clock signal terminal. The clock signal terminal is electrically connected to the clock input terminal CP of the reset signal providing unit 32 and the clock input terminal CP of the logic unit 2 to be tested, respectively, and is configured to provide a clock signal to the reset signal providing unit 32 and the logic unit 2 to be tested. Specifically, the clock signal terminal is electrically connected to the clock input terminal CP of the serial register 321 and the clock input terminal CP of the register in the logic unit 2 to be tested, and is configured to provide a clock signal to the serial register 321 and the logic unit 2 to be tested. When the register is a rising edge register, the signal received by the scan input SI is transmitted to the output end only when the rising edge of the clock signal arrives, and when the register is a falling edge register, the signal received by the scan input SI is transmitted to the output end Q only when the falling edge of the clock signal arrives, that is, the second scan output signal is captured from the scan input SI of the logic unit 2 to be tested to the output end of the logic unit 2 to be tested along with the cycle change of the clock signal, and is finally shifted out through the scan signal output unit 33, and the third scan output signal is observed through the output PIN1 of the scan signal output unit 33, so as to complete the logic test of the logic unit 2 to be tested.

The embodiment of the invention also provides a reset device which comprises the DFT reset circuit provided in the embodiment.

Compared with the prior art, the beneficial effects of the reset device provided by the embodiment of the invention are the same as those of the DFT reset circuit provided by the above embodiment, and are not described herein again.

An embodiment of the present invention further provides a reset method, which is applied to the DFT reset circuit provided in the embodiment, where the reset method includes:

the scanning signal providing unit provides a first scanning output signal to the reset signal providing unit according to a scanning input signal provided by the scanning pin.

In response to the first scan output signal, the reset signal providing unit provides a second scan output signal to the scan input terminal of the logic unit to be tested, and provides a first reset signal to the reset terminal of the logic unit to be tested.

Compared with the prior art, the beneficial effects of the reset method provided by the embodiment of the invention are the same as those of the DFT reset circuit provided by the embodiment, and are not described herein again.

While the invention has been described in connection with various embodiments, other variations to the disclosed embodiments can be understood and effected by those skilled in the art in practicing the claimed invention, from a review of the drawings, the disclosure, and the appended claims. In the claims, the word "comprising" does not exclude other elements or steps, and the word "a" or "an" does not exclude a plurality. A single processor or other unit may fulfill the functions of several items recited in the claims. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage.

While the invention has been described in conjunction with specific features and embodiments thereof, it will be evident that various modifications and combinations can be made thereto without departing from the spirit and scope of the invention. Accordingly, the specification and figures are merely exemplary of the invention as defined in the appended claims and are intended to cover any and all modifications, variations, combinations, or equivalents within the scope of the invention. It will be apparent to those skilled in the art that various changes and modifications may be made in the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.

Claims (10)

1. A DFT reset circuit is used for carrying out reset management on a logic unit to be tested of a chip, and is characterized by comprising: a scanning signal providing unit and a reset signal providing unit;

the output end of the scanning signal providing unit is electrically connected with the scanning input end of the logic unit to be tested through the reset signal providing unit, and the output end of the reset signal providing unit is electrically connected with the reset end of the logic unit to be tested;

the scanning signal providing unit comprises a scanning pin, and the scanning signal providing unit is used for providing a first scanning output signal to the reset signal providing unit according to a scanning input signal provided by the scanning pin;

the reset signal providing unit is used for respectively providing a second scanning output signal to the scanning input end of the logic unit to be tested according to the first scanning output signal and providing a first reset signal to the reset end of the logic unit to be tested.

2. The DFT reset circuit as recited in claim 1, wherein said reset signal providing unit comprises a reset signal generating module, a selecting module and a reset signal output module, wherein:

the output end of the scanning signal providing unit is electrically connected with the scanning input end of the reset signal generating module and is used for providing the first scanning output signal for the reset signal generating module, and the output end of the reset signal generating module is electrically connected with the scanning input end of the logic unit to be tested and is used for providing the second scanning output signal for the scanning input end of the logic unit to be tested according to the first scanning output signal;

the output end of the reset signal generation module is also electrically connected with the input end of the selection module, the output end of the selection module is electrically connected with the input end of the reset signal output module, and the selection module is used for providing a second reset signal to the reset signal output module under the action of the second scanning output signal;

the reset signal output module is electrically connected with the reset end of the logic unit to be tested and used for providing the first reset signal for the reset end of the logic unit to be tested according to the second reset signal.

3. The DFT reset circuit as recited in claim 2, wherein said reset signal generation module comprises a chain register, wherein:

the output end of the scanning signal providing unit is electrically connected with the scanning input end of the serial chain register, and the output end of the serial chain register is respectively electrically connected with the scanning input end of the logic unit to be tested and the input end of the selection module and is used for providing the second scanning output signal to the scanning input end of the logic unit to be tested and the selection module according to the first scanning output signal; the output end of the serial link register is also electrically connected with the data input end of the serial link register.

4. The DFT reset circuit as recited in claim 2 wherein the select module comprises an or gate and a scan enable signal terminal, wherein:

the output end of the reset signal generation module is electrically connected with the first input end of the or gate and is used for providing the second scanning output signal for the or gate, and the scanning enable signal end is electrically connected with the second input end of the or gate and is used for providing the scanning enable signal for the or gate;

the output end of the or gate is electrically connected with the input end of the reset signal output module, and the or gate is used for providing the second reset signal to the reset signal output module according to the second scanning output signal and the scanning enabling signal;

the scan enable signal terminal is further electrically connected with the scan enable terminal of the logic unit to be tested and is used for providing a scan enable signal to the scan enable terminal of the logic unit to be tested.

5. The DFT reset circuit as recited in claim 2, wherein the reset signal output module comprises a data selector and a reset signal terminal, wherein:

the first input end of the data selector is electrically connected with an external functional logic signal end, the second input end of the data selector is electrically connected with the output end of the selection module through the reset signal end, the selection end of the data selector is electrically connected with an external test signal end, and the output end of the data selector is electrically connected with the reset end of the logic unit to be tested and used for providing the first reset signal for the reset end of the logic unit to be tested.

6. The DFT reset circuit as recited in claim 1, wherein the scan signal providing unit further comprises a first silicon pin and a scan signal terminal;

the scanning pin, the first silicon chip pin and the scanning signal end are electrically connected in sequence, and the output end of the scanning signal end is electrically connected with the reset signal providing unit.

7. The DFT reset circuit of claim 1, further comprising a scan signal output unit electrically connected to an output of the logic unit under test for outputting a third scan output signal of the logic unit under test, wherein the third scan output signal is generated after the second scan output signal passes through the logic unit under test;

the scanning signal output unit comprises an output pin, a second silicon chip pin and a scanning signal output end, wherein:

the output end of the logic unit to be tested, the scanning signal output end, the second silicon chip pin and the output pin are electrically connected in sequence.

8. The DFT reset circuit as recited in claim 1, further comprising clock signal terminals electrically connected to the clock input terminal of the reset signal providing unit and the clock input terminal of the logic unit under test, respectively, for providing clock signals to the reset signal providing unit and the logic unit under test.

9. A reset device comprising the DFT reset circuit of any one of claims 1 to 8.

10. A reset method applied to the DFT reset circuit of any one of claims 1 to 8, the reset method comprising:

the scanning signal providing unit provides a first scanning output signal to the reset signal providing unit according to a scanning input signal provided by the scanning pin;

in response to the first scan output signal, the reset signal providing unit provides a second scan output signal to the scan input terminal of the logic unit to be tested, and provides a first reset signal to the reset terminal of the logic unit to be tested.

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