CN115088084A - 交错堆叠的垂直晶体半导体沟道 - Google Patents

交错堆叠的垂直晶体半导体沟道 Download PDF

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CN115088084A
CN115088084A CN202180014221.2A CN202180014221A CN115088084A CN 115088084 A CN115088084 A CN 115088084A CN 202180014221 A CN202180014221 A CN 202180014221A CN 115088084 A CN115088084 A CN 115088084A
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semiconductor
semiconductor channel
channel
vertical nanowires
silicon
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康宗圣
李桃
A·拉曼
P·约瑟夫
I·塞沙德里
E·A·德西尔瓦
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International Business Machines Corp
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Abstract

一种半导体结构(100)包括具有多个垂直纳米线(106)的第一半导体沟道和具有多个垂直纳米线(106)的第二半导体沟道。第一半导体沟道和第二半导体沟道被配置为处于堆叠配置。第一半导体沟道的多个垂直纳米线(106)被配置为相对于第二半导体沟道的多个垂直纳米线(106)处于交替位置。

Description

交错堆叠的垂直晶体半导体沟道
背景技术
在垂直方向上堆叠场效应晶体管(FET)给出了用于互补金属氧化物半导体(CMOS)区域缩放的附加尺寸。在典型的CMOS布局中，百分之九十的时间第一晶体管连接到至少第二晶体管。例如，n型晶体管的漏极连接到p型晶体管的漏极以形成反相器。还考虑了其他布置，例如连接到第二晶体管的源极的第一晶体管的漏极、连接到第二晶体管的漏极的第一晶体管的漏极或连接到第二晶体管的源极的第一晶体管的源极之间的连接，其中第一和第二晶体管可以是n型或p型晶体管的任何组合。
垂直场效应晶体管(VFET)具有可帮助堆叠工艺的独特结构。与平面CMOS器件相反，VFET被定向为具有设置在底部源极/漏极上的垂直鳍状物沟道和设置在鳍状物沟道上的顶部源极/漏极。栅极在垂直鳍状物沟道的旁边垂直延伸。VFET已作为将CMOS缩放到5纳米(nm)节点及以上的潜在装置选项而被推行。
发明内容
本发明的实施例包括用于形成交错堆叠的垂直半导体沟道的结构和方法。例如，一个示例性实施例包括一种半导体结构，该半导体结构包括：第一半导体沟道，其包括多个垂直纳米线；以及包括多个垂直纳米线的第二半导体沟道。第一半导体沟道和第二半导体沟道被配置为处于堆叠配置。第一半导体沟道的多个垂直纳米线被配置为相对于第二半导体沟道的多个垂直纳米线处于交替位置。
另一示例性实施例包括一种逻辑器件，其包括一个或多个半导体结构。所述一个或多个半导体结构中的至少一个包括第一半导体沟道，所述第一半导体沟道包括多个垂直纳米线；以及包括多个垂直纳米线的第二半导体沟道。第一半导体沟道和第二半导体沟道被配置为处于堆叠配置。第一半导体沟道的多个垂直纳米线被配置为相对于第二半导体沟道的多个垂直纳米线处于交替位置。
另一示范性实施例包含一种集成电路逻辑装置，其包括一个或一个以上半导体结构。所述一个或多个半导体结构中的至少一个包括第一半导体沟道，所述第一半导体沟道包括多个垂直纳米线；以及包括多个垂直纳米线的第二半导体沟道。第一半导体沟道和第二半导体沟道被配置为处于堆叠配置。第一半导体沟道的多个垂直纳米线被配置为相对于第二半导体沟道的多个垂直纳米线处于交替位置。
另一示例性实施例包括一种方法，该方法包括在半导体衬底上形成包括多个垂直纳米线的第一半导体沟道和包括多个垂直纳米线的第二半导体沟道。第一半导体沟道和第二半导体沟道被配置为堆叠配置。第一半导体沟道的多个垂直纳米线被配置为相对于第二半导体沟道的多个垂直纳米线处于交替位置。
另一示例性实施例包括一种方法，该方法包括从衬底的表面形成多个分层的硅-绝缘体-硅纳米线。所述多个纳米线包括在其顶表面上的硬掩模。该方法还包括在交替分层的硅-绝缘体-硅纳米线的外表面上形成衬垫。衬垫形成在绝缘体层的延伸到硬掩模并暴露分层的硅-绝缘体-硅纳米线的底部硅层的一部分上。该方法还包括在其它交替分层的硅-绝缘体-硅纳米线的外表面上形成第一氧化物层。第一氧化层形成在绝缘体层的延伸到衬底的顶表面并暴露分层的硅-绝缘体-硅纳米线的顶部硅层的一部分上。该方法还包括热氧化分层的硅-绝缘体-硅纳米线的暴露的底部硅层和分层的硅-绝缘体-硅纳米线硅层的暴露的顶部硅层。
通过结合附图阅读的本发明的说明性实施例的以下详细描述，本发明的这些和其它特征、目的和优点将变得显而易见。
附图说明
图1是根据一个或多个示例性实施例的在第一中间制造阶段的半导体结构的示意性截面侧视图。
图2是根据一个或多个示例性实施例的在第二中间制造阶段的半导体结构的示意性截面侧视图。
图3是根据一个或多个示例性实施例的在第三中间制造阶段的半导体结构的示意性截面侧视图。
图4是根据一个或多个示例性实施例的在第四中间制造阶段的半导体结构的示意性截面侧视图。
图5是根据一个或多个示例性实施例的在制造的第五中间阶段的半导体结构的示意性截面侧视图。
图6是根据一个或多个示例性实施例的在第六中间制造阶段的半导体结构的示意性截面侧视图。
图7是根据一个或多个示例性实施例的在制造的第七中间阶段的半导体结构的示意性截面侧视图。
图8是根据一个或多个示例性实施例的在制造的第八中间阶段的半导体结构的示意性截面侧视图。
图9是根据一个或多个示例性实施例的在制造的第九中间阶段的半导体结构的示意性截面侧视图。
图10是根据一个或多个示例性实施例的在制造的第十中间阶段的半导体结构的示意性截面侧视图。
图11是根据一个或多个示例性实施例的在制造的第十一中间阶段的半导体结构的示意性截面侧视图。
图12是根据一个或多个示例性实施例的在第十二制造中间阶段的半导体结构的示意性截面侧视图。
具体实施方式
本公开一般涉及半导体制造技术，并且具体地涉及用于制造在制造垂直场效应晶体管器件中使用的交错堆叠的垂直半导体沟道的结构和方法。垂直堆叠VFET使得底部FET的源极/漏极(S/D)触点的连接变得困难，因为将需要制造“L”形导电材料。示例性实施例的垂直堆叠的晶体半导体结构(或垂直鳍状物阵列)，其中半导体鳍状物在间距上交错，允许以简单和直接的方式连接最终的底部FET的S/D触点。
应该理解，附图中所示的各个层、结构和区域是未按比例绘制的示意图。另外，为了便于解释，通常用于形成半导体器件或结构的类型的一个或多个层、结构和区域可能未在给定附图中明确示出。这并不意味着从实际半导体结构中省略了未明确示出的任何层、结构和区域。
此外，应理解，本文所论述的实施例不限于本文所展示和描述的特定材料、特征和处理步骤。特别地，关于半导体处理步骤，要强调的是，本文提供的描述不旨在包括形成功能性半导体集成电路器件可能需要的所有处理步骤。相反，为了描述的经济性，在形成半导体器件中通常使用的某些处理步骤，例如湿法清洁和退火步骤，在此有目的地不进行描述。
此外，在所有附图中使用相同或相似的附图标记来表示相同或相似的特征、元件或结构，因此，对于每个附图将不重复相同或相似的特征、元件或结构的详细解释。应当理解，本文所用的关于厚度、宽度、百分比、范围等的术语“约”或“基本上”旨在表示接近或近似，而不是精确的。例如，如本文所用，术语“约”或“基本上”暗示可能存在小的误差余量，例如相比所述量的1％或更少。
下面将参考图1-12讨论用于形成半导体结构的说明性实施例。现在参考附图，图1是包括半导体衬底102和硬掩模层104的半导体结构100的截面图。半导体衬底102可以包括常规类型的绝缘体上硅(SOI)衬底晶片，例如本领域技术人员已知的极薄绝缘体上硅(ETSOI)或超薄体和掩埋氧化物(UTBB)绝缘体上硅(SOI)。或者，半导体衬底102可包括体半导体衬底晶片。如图所示，衬底102可以首先包括基层102a，例如硅。可以在基层102a上形成绝缘层102b，例如掩埋氧化物层。硅层102c又形成在绝缘层102b上，尽管硅层102c也可以是任何其它合适的半导体层。在一个实施例中，衬底102是分层的硅-绝缘体-硅衬底。
SOI衬底的顶部半导体层或体衬底的半导体材料可以被掺杂以适合于集成电路应用。在SOI衬底的一个说明性实施例中，顶部半导体层可以是完全耗尽(FD)配置。体衬底可以包括例如多个外延生长的半导体层。这里描述的工艺技术同样适用于SOI和体衬底，以及其它类型的衬底。
硬掩模层104使用任何常规沉积工艺沉积在衬底102上，例如原子层沉积(ALD)、化学气相沉积(CVD)、等离子体增强化学气相沉积(PECVD)、物理气相沉积(PVD)或其它类似工艺。用于硬掩模层104的合适材料包括例如TiN、SiO2、TaN、SiN、AlOx、SiC等。然后，可以通过例如诸如化学机械平坦化(CMP)工艺的平坦化工艺来平坦化硬掩模层104。
图2中示出了形成用于半导体结构100的垂直堆叠的鳍状物的下一步骤，其中对半导体结构100进行构图以形成一组垂直纳米线106。垂直纳米线106具有基本垂直的侧壁。尽管图2中示出了四个垂直纳米线106，但是垂直纳米线106的数量不应被认为是限制性的。为了形成垂直纳米线106，使用任何类型的构图技术，例如直接印刷光刻或侧壁图像转移(SIT)工艺，执行光刻和蚀刻。直接印刷光刻工艺可以是193i光刻或极紫外(EUV)光刻中的一种，这是本领域技术人员所熟悉的。SIT工艺可以称为自对准双图案化(SADP)工艺。在一些实施例中，SIT工艺可以用于图案化硬掩模104的窄线。例如，光刻可以包括在硬掩模层104上形成光致抗蚀剂(未示出)，将光致抗蚀剂曝光于期望的辐射图案，然后利用抗蚀剂显影剂显影曝光的光致抗蚀剂以在硬掩模层104的顶部上提供图案化的光致抗蚀剂。
采用至少一次蚀刻将图案从图案化的光刻胶转移到硬掩模层104和衬底102中。通过深蚀刻入但不穿过衬底102来形成垂直纳米线106。例如，通过蚀刻穿过硬掩模层104、硅层102c、绝缘层102b和基底层102a的一部分来执行蚀刻，以形成垂直纳米线106。蚀刻工艺可以是干法蚀刻(例如，反应离子蚀刻、等离子体蚀刻、离子束蚀刻或激光烧蚀)。蚀刻工艺可以是湿法化学蚀刻(例如，用氢氧化钾，或硫酸和过氧化氢)。可以使用干法蚀刻和湿法化学蚀刻工艺二者。在转移图案之后，利用抗蚀剂剥离工艺，例如灰化，除去图案化的光致抗蚀剂。灰化是使用适当的反应气体来执行，例如O2、N2、H2/N2、O3、CF4或其任何组合。
图3中示出了形成用于半导体结构100的垂直堆叠的鳍状物的下一步骤，其中在衬底102、硬掩模104和垂直纳米线106上形成衬垫108。衬垫108可以是Y衬垫材料，例如介电材料。合适的介电材料包括例如氮化硅、氧化硅、氮氧化硅、介电金属氧化物、介电金属氮化物或其组合。例如，可通过使用ALD工艺沉积衬垫层来形成衬垫108。衬垫层108可具有范围从约1到约3纳米(nm)的厚度。
图4中示出了形成用于半导体结构100的垂直堆叠的鳍状物的下一步骤，其中，然后在衬垫108上和垂直纳米线106上方用氧化物110填充蚀刻区域。合适的氧化物材料包括例如二氧化硅。在一个实施例中，通过在垂直纳米线106上沉积氧化物的均厚层，然后通过例如CMP工艺平坦化氧化物，来形成氧化物填充物110。
图5中示出了形成用于半导体结构100的垂直堆叠的鳍状物的下一步骤，其中使用光刻来图案化氧化物填充物110的一部分以暴露交替的垂直纳米线106和衬垫108的顶部部分。在一个实施例中，可以使用各向异性蚀刻选择性地去除氧化物填充物110。例如，在一个说明性实施例中，各向异性蚀刻可以利用氢氟酸进行，例如以气态无水HF连同氨的形式。在另一说明性实施例中，可通过氢氟烃等离子体蚀刻来执行各向异性蚀刻。例如，等离子体蚀刻可以使用与惰性气体结合的氢氟烃等离子体气体来进行。通常，惰性气体可以是至少90％。在一说明性实施例中，氢氟烃可为C5HF7，且惰性气体可为氩及氧，且当在等离子体蚀刻腔室中激发时，产生高密度等离子体。在说明性实施例中，射频(RF)功率源将功率感应耦合到腔室中，其中正蚀刻的衬底支撑在基座上。基座也被RF电源以高于电感耦合功率的功率偏置。此外，含硅表面可包括在腔室中并维持在至少20℃以从等离子体中清除氟。结果，蚀刻对衬垫108(例如氮化硅)上的氧化物填充物110(例如氧化硅)和光刻图案化的光致抗蚀剂(未示出)表现出高选择性。由于等离子体蚀刻的高选择性，衬垫108保持未蚀刻。因此，在该蚀刻期间，选择性地去除氧化物填充物110以暴露交替的垂直纳米线106的顶部。在一个实施例中，氧化物填充物110被向下去除到每个交替的垂直纳米线106的绝缘层102b的顶表面。
图6中示出了形成用于半导体结构100的垂直堆叠的鳍状物的下一步骤，其中，在交替的垂直纳米线106上的氧化物填充物110和衬垫108的侧壁上沉积间隔件112。可以通过诸如ALD的任何常规技术来沉积间隔件112，并使用诸如反应离子蚀刻(RIE)的各向异性干法蚀刻工艺来回蚀刻。用于间隔件112的合适材料包括(例如)非晶碳(a-C)。如果需要，可以通过例如RIE去除结构100的水平部分上的任何间隔件材料。间隔件112可以具有范围从约1nm到约3nm的厚度。
图7中说明形成用于半导体结构100的垂直堆叠鳍状物的下一步骤，其中进一步去除邻近间隔件112之间的氧化物填充物110以暴露衬垫108的顶部表面。在一个实施例中，可以使用各向异性蚀刻选择性地去除氧化物填充物110。在一个示范具体实施例中，该各向异性蚀刻可通过氢氟烃等离子体蚀刻来执行。例如，等离子体蚀刻可以使用与惰性气体结合的氢氟烃等离子体气体来进行。在一个说明性实施例中，惰性气体可为等离子体蚀刻的至少约90％。在一示范具体实施例中，氢氟烃可为C5HF7，而惰性气体可为氩及氧，且当在等离子体蚀刻腔室中激发时，产生高密度等离子体，如上所述。结果，蚀刻对衬垫108和间隔件112上的氧化物填充物110表现出高选择性。由于等离子体蚀刻的高选择性，衬垫108和间隔件112保持未蚀刻。在另一说明性实施例中，各向异性蚀刻可借助于氢氟酸来执行，例如呈气态无水HF连同氨的形式。
因此，在该蚀刻期间，选择性地去除氧化物填充物110以暴露交替的垂直纳米线106的顶部和相邻间隔件112之间的衬垫108的顶表面。此外，氧化物填充物110保留在间隔件112下方。在一个实施例中，氧化物填充物110被向下去除到每个交替的垂直纳米线106的绝缘层102b的顶表面。
图8中示出了形成用于半导体结构100的垂直堆叠的鳍状物的下一步骤，其中通过各向同性蚀刻选择性地去除在每个交替的垂直纳米线106的衬垫层108的侧壁上形成的每个间隔件112下面的氧化物填充物110。在一个实施例中，可以使用各向同性蚀刻选择性地去除氧化物填充物110。在一个例示实施例中，该各向同性蚀刻可通过氢氟烃等离子体蚀刻来执行。例如，等离子体蚀刻可以使用与惰性气体结合的氢氟烃等离子体气体来进行。通常，惰性气体可以是至少90％。在一示范具体实施例中，氢氟烃可为C5HF7，而惰性气体可为氩及氧，且当在等离子体蚀刻腔室中激发时，产生高密度等离子体，如上所述。结果，蚀刻对衬垫108和间隔件112上的氧化物填充物110表现出高选择性。由于等离子体蚀刻的高选择性，衬垫108和间隔件112保持未蚀刻。在另一说明性实施例中，各向同性蚀刻可借助于例如呈气态无水HF连同氨的形式的氢氟酸来执行。如上所述，通过各向同性蚀刻，通过间隔件112之间的湿法蚀刻剂流，选择性地去除氧化物填充物110。在该蚀刻期间，可以去除相邻垂直纳米线106的侧壁上的氧化物填充物110的一部分。此外，氧化物填充物110的一部分可以在相邻的垂直纳米线106的间隔件112下各向同性地凹陷。
图9中示出了形成用于半导体结构100的垂直堆叠的鳍状物的下一步骤，其中，选择性地去除交替的垂直纳米线106上的氧化物填充物110上方的暴露的衬垫108的一部分和每个垂直纳米线106的硬掩模104上的暴露的衬垫108。在一个例示实施例中，通过各向同性蚀刻选择性地去除该暴露的内衬108。在一个例示实施例中，该各向同性蚀刻可通过碳氟化合物等离子体蚀刻来执行。例如，可以使用与惰性气体结合的碳氟化合物等离子体气体来执行等离子体蚀刻。通常，惰性气体可以是至少90％。在一个说明性实施例中，该碳氟化合物可为CF4，且该惰性气体可为氧及氮，且当在等离子体蚀刻室中激发时，产生高密度等离子体，如上所述。在另一说明性实施例中，碳氟化合物可为CF4且惰性气体可为氩，且当在等离子体蚀刻腔室中激发时，产生如上所述的高密度等离子体。结果，蚀刻对氧化物填充物110和间隔件112上的暴露的衬垫108呈现高选择性。
在图10中示出了形成用于半导体结构100的垂直堆叠的鳍状物的下一步骤，其中去除了间隔件112。可通过任何合适的蚀刻工艺(包括但不限于湿蚀刻工艺或干蚀刻)来去除间隔件112。例如，可以使用RIE或等离子体蚀刻工艺和N2/H2化学物质或在惰性气体例如氩气中的N2/H2化学物质，进行蚀刻。
图11中说明形成用于半导体装置100的垂直堆叠鳍状物的下一步骤，其中使暴露的硅部分102a及102c经受本领域中已知的热氧化工艺。执行热氧化工艺以氧化交替垂直纳米线106的暴露部分102a和交替垂直纳米线106的暴露部分102c。该工艺在交替的垂直纳米线106的暴露部分102a内和交替的垂直纳米线106的暴露部分102c内形成氧化物。如图所示，所形成的氧化物与氧化物填充物110相同。
图12中说明形成用于半导体结构100的垂直堆叠鳍状物的下一步骤，其中接着用氧化物材料填充结构100的暴露部分。氧化物材料可以与氧化物填充物110相同或不同。在一个说明性实施例中，氧化物填充物与氧化物填充物110相同。在一个实施例中，通过在结构100的暴露部分中和垂直纳米线106上沉积氧化物的均厚层，然后通过例如CMP工艺平坦化氧化物，来形成氧化物填充110。所得到的结构100包含垂直结晶纳米线106，其在包含堆叠配置的垂直纳米线106的两层之间在间距上交错。所得结构100具有交错的晶体半导体沟道102a和102c，其具有相同的间距，但在垂直鳍状物阵列的顶层和底层之间移动或平移。
在一个实施例中，在叠层底部的鳍状物可以形成PFET晶体管，而在叠层顶部的鳍状物可以形成NFET晶体管。然而，本发明不限于此，并且可以包括这样的结构，其中在叠层底部的晶体管和在叠层顶部的晶体管可以分别是PFET和PFET、NFET和NFET、或者NFET和PFET。
本文公开的垂直堆叠交错的半导体鳍状物可以经受一个或多个附加处理步骤。例如，第一场效应晶体管可以进一步包括源极/漏极区以及包括栅极电介质层和金属栅极层的栅极结构。堆叠在第一场效应晶体管上的第二场效应晶体管可以进一步包括源极/漏极区以及包括栅极电介质层和金属栅极层的栅极结构。此外，一个或多个导电通孔可以与第一FET器件的栅极结构或第二FET器件的栅极结构连通。
例如，可以通过在第一场效应晶体管的纳米线106的暴露的顶表面上生长外延半导体材料来形成源极/漏极区。执行外延生长工艺以将晶体层沉积到下面的晶体衬底上。下面的衬底充当籽晶。外延层可以从气态或液态前体生长。外延硅材料可以使用气相外延(VPE)、分子束外延(MBE)、液相外延(LPE)或其他合适的工艺来生长。用于形成源极区112的外延材料和掺杂剂的类型将根据FET器件是P型器件还是N型器件而变化。可适于源极/漏极区的外延生长的半导体材料的实例包括(但不限于)硅(单晶、多晶硅或非晶)、锗(单晶、多晶或非晶)或其组合。
在生长半导体材料之后，将使用例如原位掺杂或离子注入或外延期间的原位掺杂来用掺杂剂原子掺杂半导体材料。在该说明性实施例中，半导体材料掺杂有p型掺杂剂，例如硼、铝、镓、铟或其合金，以形成PFET源极区。在如下所述的其它实施例中，半导体材料可以掺杂有n型掺杂剂，例如磷、锑、砷或其合金。在掺杂工艺之后，半导体材料可具有范围从约1×1019原子/cm3至约5×1021原子/cm3的掺杂剂浓度。
应了解，本文所论述的用于制造半导体结构的方法可并入用于制造具有各种模拟和数字电路或混合信号电路的其它类型的半导体装置和集成电路的半导体处理流程内。特别地，集成电路管芯可以用各种器件制造，例如晶体管、二极管、电容器、电感器等。根据实施例的集成电路可以在应用、硬件和/或电子系统中使用。用于实现本发明的实施例的合适的硬件和系统可以包括但不限于个人计算机、通信网络、电子商务系统、便携式通信设备(例如，蜂窝电话)、固态介质存储设备、功能电路等。结合了这种集成电路的系统和硬件被认为是本文所述实施例的一部分。
此外，上述各种层、区域和/或结构可以在集成电路(芯片)中实现。制造者可以以原始晶片形式(即，作为具有多个未封装芯片的单个晶片)、作为裸芯片或以封装形式来分发所得到的集成电路芯片。在后一种情况下，芯片被安装在单个芯片封装(例如塑料载体，具有被固定到母板或其它更高级载体的引线)中或多芯片封装(例如陶瓷载体，具有表面互连或掩埋互连中的一者或两者)中。在任何情况下，芯片然后与其它芯片、分立电路元件和/或其它信号处理设备集成，作为(a)中间产品(诸如母板)或(b)最终产品的一部分。最终产品可以是包括集成电路芯片的任何产品，范围从玩具和其它低端应用到具有显示器、键盘或其它输入设备以及中央处理器的高级计算机产品。
尽管在此已经参考附图描述了说明性实施例，但是应当理解，本发明不限于这些精确的实施例，并且本领域技术人员可以在不脱离本发明的范围的情况下做出各种其他改变和修改。
在上述本发明的优选实施方案中，提供了一种方法，包括：从衬底的表面形成多个分层的硅-绝缘体-硅垂直纳米线；其中所述多个纳米线在其顶表面上具有硬掩模；在交替分层的硅-绝缘体-硅垂直纳米线的外表面上形成衬垫，其中所述衬垫形成在延伸到所述硬掩模并暴露所述分层的硅-绝缘体-硅垂直纳米线的底部硅层的绝缘体层的一部分上；在所述另一交替分层的硅-绝缘体-硅垂直纳米线的外表面上形成第一氧化物层，其中所述第一氧化物层在所述绝缘体层的延伸到所述衬底的顶表面并暴露所述分层的硅-绝缘体-硅垂直纳米线的所述顶部硅层的部分上形成；以及热氧化暴露的硅-绝缘体-硅纳米线层底硅层和硅-绝缘体-硅纳米线层顶硅层。优选地，该方法还包括在衬底和第一氧化物层的外表面上以及在衬垫上沉积第二氧化物层。

Claims (13)

1.一种半导体结构，包括：
包括多个垂直纳米线的第一半导体沟道；以及
包括多个垂直纳米线的第二半导体沟道；
其中所述第一半导体沟道和所述第二半导体沟道被配置为处于堆叠配置；
其中所述第一半导体沟道的所述多个垂直纳米线被配置为相对于所述第二半导体沟道的所述多个垂直纳米线处于交替位置。
2.根据权利要求1所述的半导体结构，其中所述第一半导体沟道设置在体衬底上。
3.根据权利要求2所述的半导体结构，其中所述体衬底包括硅。
4.根据权利要求3所述的半导体结构，其中所述第一半导体沟道的所述多个垂直纳米线和所述第二半导体沟道的所述多个垂直纳米线每个都包括所述体衬底的硅。
5.如权利要求1所述的半导体结构，其中所述第一半导体沟道的所述多个垂直纳米线设置在第一氧化物层中，并且所述第二半导体沟道的所述多个垂直纳米线设置在第二氧化物层中。
6.如权利要求1所述的半导体结构，其中所述第一半导体沟道被配置为直接堆叠在所述第二半导体沟道上。
7.如权利要求1所述的半导体结构，其特征在于，所述第一半导体沟道是n沟道，并且所述第二半导体沟道是p沟道。
8.如权利要求1所述的半导体结构，其特征在于，所述第一半导体沟道是p沟道，并且所述第二半导体沟道是n沟道。
9.根据权利要求1所述的半导体结构，还包括衬垫，所述衬垫设置在所述第一半导体沟道的所述多个垂直纳米线和所述第二半导体沟道的所述多个垂直纳米线中的每一个的一部分上。
10.一种逻辑器件，包括至少一个如前述任一权利要求所述的半导体结构。
11.一种集成电路，包括如权利要求10所述的逻辑器件。
12.一种方法，包括：
在半导体衬底上形成包括多个垂直纳米线的第一半导体沟道和包括多个垂直纳米线的第二半导体沟道；
其中所述第一半导体沟道和所述第二半导体沟道以堆叠配置形成；
其中，所述第一半导体沟道的所述多个垂直纳米线相对于所述第二半导体沟道的所述多个垂直纳米线形成在交替的位置中。
13.根据权利要求12所述的方法，其中所述半导体衬底包括分层的硅-绝缘体-硅衬底。
CN202180014221.2A 2020-03-17 2021-02-17 交错堆叠的垂直晶体半导体沟道 Pending CN115088084A (zh)

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