CN115085852B

CN115085852B - Clock signal transmission device, manufacturing method thereof and optical clock balancing device

Info

Publication number: CN115085852B
Application number: CN202210995622.7A
Authority: CN
Inventors: 王鲁; 柏艳飞; 陈炜; 华士跃; 孟怀宇; 沈亦晨
Original assignee: Nanjing Guangzhiyuan Technology Co ltd
Current assignee: Nanjing Guangzhiyuan Technology Co ltd
Priority date: 2022-08-19
Filing date: 2022-08-19
Publication date: 2022-11-08
Anticipated expiration: 2042-08-19
Also published as: WO2024037573A1; CN115085852A

Abstract

The invention relates to the technical field of clock synchronization, and provides a clock signal transmission device, a manufacturing method thereof and an optical clock balancing device. Illustratively, the clock signal transmission apparatus may include: the optical network on chip comprises an optical signal transmitting end, a plurality of optical signal receiving ends and a plurality of waveguides which connect the optical signal transmitting end and the optical signal receiving ends; the electro-optical conversion module is arranged at the optical signal sending end and used for receiving a clock electrical signal from a clock source and converting the clock electrical signal into a clock optical signal, and the clock optical signal is transmitted to different optical signal receiving ends through different waveguides; and a plurality of photoelectric conversion modules, which are respectively arranged at the plurality of optical signal receiving ends, and are used for converting the respectively received clock optical signals into clock electrical signals. The invention utilizes the on-chip optical network to complete the transmission of the clock signal, and can complete the balance of the delay time of the clock signal reaching each clock receiving end on the optical network.

Description

Clock signal transmission device, manufacturing method thereof and optical clock balancing device

Technical Field

The present invention relates to the field of clock synchronization technologies, and in particular, to a clock signal transmission device, a manufacturing method thereof, and an optical clock balance device.

Background

In a conventional electronic integrated circuit chip, a clock network is formed inside the chip by metal lines and logic devices such as a buffer (buffer) and an inverter (inverter) to perform clock signal transmission. Such a clock network has problems of too high delay and too large influence by PVT (Process-Voltage-Temperature) difference. Especially, when the chip area is large and the distance to be transmitted is long, it is difficult to synchronize the whole chip within one clock cycle.

For example, a chip with a width of 20000um, assuming the clock source is at the center point, it takes about 1ns to complete the clock balance. However, in consideration of the influence of OCV (On-Chip Variation), a delay difference between the nearest clock receiving point and the farthest clock receiving point may reach about 200ps in practice, making it difficult to synchronize clocks at both ends. Thus, additional circuit design is required to achieve clock synchronization across these terminals, which necessarily increases power consumption and design complexity.

Disclosure of Invention

The invention provides a clock signal transmission device, a manufacturing method thereof and an optical clock balancing device, which can finish the transmission of clock signals by utilizing an on-chip optical network and can finish the balance of delay time when the clock signals reach each point on the optical network.

According to an aspect of the present invention, there is provided a clock signal transmission apparatus including:

the on-chip optical network comprises an optical signal transmitting end, a plurality of optical signal receiving ends and a plurality of waveguides for connecting the optical signal transmitting end and the optical signal receiving ends;

the electro-optical conversion module is arranged at the optical signal sending end and used for receiving a clock electrical signal from a clock source and converting the clock electrical signal into a clock optical signal, and the clock optical signal is transmitted to different optical signal receiving ends through different waveguides; and

and the photoelectric conversion modules are respectively arranged at the plurality of optical signal receiving ends and are used for converting the respectively received clock optical signals into clock electrical signals.

In some embodiments, the plurality of waveguides are configured to substantially equalize a transmission time of the clock optical signal from the optical signal transmitting end to a different optical signal receiving end.

In some embodiments, the plurality of waveguides are arranged such that transmission distances of the clock optical signal from the optical signal transmitting end to different optical signal receiving ends are substantially equal.

In some embodiments, different ones of the plurality of waveguides in the same clock balancing system are configured to substantially equalize transmission distances of the clock optical signal from the optical signal transmitting end to different optical signal receiving ends.

In some embodiments, different ones of the plurality of waveguides located in different clock balancing systems are configured to have approximately equal or unequal transmission distances of the clock optical signal from the optical signal transmitting end to different optical signal receiving ends.

In some embodiments, the clock signal transmission apparatus further includes at least one electrical clock balancing module communicatively coupled to at least one of the plurality of photoelectric conversion modules for receiving the clock signal from the at least one photoelectric conversion module and repairing clock balancing.

In some embodiments, the clock signal transmission device is configured to mark a delay time of a clock signal transmitted from the clock source to each optical signal receiving end via the on-chip optical network into an origin of a clock signal of the electrical clock balancing module.

In some embodiments, the electrical clock balancing module comprises a clock tree.

In some embodiments, the clock signal transmission device comprises a photonic integrated circuit chip including the on-chip optical network, the electro-optical conversion module, and the electro-optical conversion module.

According to another aspect of the present invention, there is provided a method of manufacturing a clock signal transmission device, including:

providing an on-chip optical network, wherein the on-chip optical network comprises an optical signal sending end, a plurality of optical signal receiving ends and a plurality of waveguides for connecting the optical signal sending end and the optical signal receiving ends;

the optical signal transmitting end is provided with an electro-optical conversion module, the electro-optical conversion module is arranged to receive a clock electrical signal from a clock source and convert the clock electrical signal into a clock optical signal, and the clock optical signal is transmitted to different optical signal receiving ends through different waveguides; and

a plurality of photoelectric conversion modules are provided at the plurality of optical signal receiving ends, each photoelectric conversion module being configured to convert a respective received clock optical signal into a clock electrical signal.

In some embodiments, the method of manufacturing further comprises: and adjusting the length of each waveguide to enable the transmission time of the clock optical signal from the optical signal transmitting end to different optical signal receiving ends to be approximately equal. In some embodiments, the lengths of the respective waveguides are adjusted such that the transmission distances of the clock optical signal from the optical signal transmitting end to the different optical signal receiving ends are approximately equal.

In some embodiments, the method of manufacturing further comprises: the lengths of the waveguides are adjusted so that different waveguides in the same clock balance system are set to make the transmission distances of the clock optical signal from the optical signal transmitting end to different optical signal receiving ends approximately equal. In some embodiments, the method of manufacturing further comprises: and adjusting the length of each waveguide to enable the transmission distances of the clock optical signals transmitted from the optical signal transmitting end to different optical signal receiving ends by different waveguides positioned in different clock balance systems to be approximately equal or unequal.

In some embodiments, the method of manufacturing further comprises: providing at least one electrical clock balancing module communicatively coupled to at least one of the plurality of photoelectric conversion modules to receive the clock electrical signal from the at least one photoelectric conversion module and to restore clock balance.

In some embodiments, the method of manufacturing further comprises: and configuring the clock signal transmission device to enable the clock signal transmission device to mark the delay time of the clock signal transmitted from the clock source to each optical signal receiving end through the on-chip optical network into the origin of the clock signal of the electric clock balancing module. That is to say, the delay time of transmitting the clock origin generated by the clock source to each optical signal receiving end (including the photoelectric conversion module) through the on-chip optical network is marked in the clock electrical signal origin of the electric clock balancing module.

In some embodiments, the electrical clock balancing module comprises a clock tree. In some embodiments, the clock signal transmission device comprises a photonic integrated circuit chip comprising the on-chip optical network, the electrical-to-optical conversion module, and the optical-to-electrical conversion module.

According to still another aspect of the present invention, there is provided an optical clock balancing apparatus including:

the electro-optical conversion module is used for converting the received clock electrical signal into a clock optical signal;

an on-chip optical network including a plurality of waveguides transmitting the clock optical signal to different clock receiving ends, wherein the plurality of waveguides are configured such that transmission distances over which the different waveguides transmit the clock optical signal to the different clock receiving ends are approximately equal;

and the photoelectric conversion modules are arranged at different clock receiving ends and are used for converting the clock optical signals into clock electrical signals.

In the embodiment of the invention, the clock signal is converted to the on-chip optical network by using the photoelectric conversion module, the transmission of the clock signal is completed by using the on-chip optical network, and the balance of delay time of the clock signal reaching each point can be completed on the on-chip optical network. The use of on-chip buffers and inverters may be reduced by transmitting the clock signal with the on-chip optical network, which may reduce power consumption. The clock signal is transmitted by using the on-chip optical network, the influence of PVT is avoided, and the clock skew (skew) is small. The clock signal is transmitted by using the on-chip optical network, so that the transmission speed is high and the delay is small.

In summary, the chip clock tree is constructed through the on-chip optical network, so that the influence of PVT on clock synchronization can be effectively reduced, clock skew can be reduced, clock delay can be reduced, and power consumption can be reduced. The invention can be used for realizing the clock synchronization of large-scale chips.

Various aspects, features, advantages, etc. of embodiments of the invention are described in detail below with reference to the accompanying drawings. The above aspects, features, advantages, etc. of the present invention will become more apparent from the following detailed description when taken in conjunction with the accompanying drawings.

Drawings

Fig. 1 is a logical configuration diagram of a clock signal transmission apparatus according to an embodiment of the present invention.

Fig. 2 is example 1 of a clock signal transmission apparatus according to an embodiment of the present invention.

Fig. 3 is example 2 of a clock signal transmission apparatus according to an embodiment of the present invention.

Fig. 4 is example 3 of a clock signal transmission apparatus according to an embodiment of the present invention.

Fig. 5 is example 4 of a clock signal transmission apparatus according to an embodiment of the present invention.

Fig. 6 is a block diagram of a clock signal transmission apparatus according to an exemplary embodiment of the present invention.

Detailed Description

Hereinafter, exemplary embodiments will be described in more detail with reference to the accompanying drawings. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided as examples so that this disclosure will be thorough and complete, and will fully convey various aspects and features of the invention to those skilled in the art. Accordingly, processes, elements, and techniques that are not necessary to fully understand aspects and features of the invention may not be described by those of ordinary skill in the art. Unless otherwise indicated, like reference numerals refer to like elements throughout the drawings and the description, and thus, the description thereof may not be repeated. Furthermore, features or aspects within each exemplary embodiment should generally be considered other similar features or aspects that may be used in other exemplary embodiments.

Certain terminology may be used in the following description for reference only and is therefore not intended to be limiting. For example, terms such as "top," "bottom," "upper," "lower," "above …," and "below …" may be used to refer to directions in the drawings to which reference is made. Terms such as "front," "back," "rear," "side," "outer," and "inner" may be used to describe the orientation and/or position of portions of the component within a consistent but arbitrary frame of reference, which may be clearly understood by reference to the text and associated drawings describing the component in question. Such terms may include the words specifically mentioned above, derivatives thereof, and words of similar import. Similarly, the terms "first," "second," and other such numerical terms referring to structures do not imply a sequence or order unless clearly indicated by the context.

It will be understood that when an element or feature is referred to as being "on," "connected to" or "coupled to" another element or layer, it can be directly on, connected or coupled to the other element or feature or one or more intervening elements or features may be present. In addition, it will also be understood that when an element or feature is referred to as being "between" two elements or features, it can be the only element or feature between the two elements or features, or one or more intervening elements or features may also be present.

The terminology used herein is for the purpose of describing particular embodiments and is not intended to be limiting of the invention. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises," "comprising," "includes" and "having," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items. Expressions such as "…" modify the entire list of elements as they precede the list of elements, rather than modifying individual elements of the list.

As used herein, the terms "substantially," "about," and the like are used as approximate terms and not as degree terms, and are intended to take into account the inherent variation in measured or calculated values that would be recognized by one of ordinary skill in the art. Furthermore, the use of "may" in describing embodiments of the invention is meant to be "one or more embodiments of the invention". As used herein, the terms "use," "using," and "used" can be considered synonymous with the terms "utilizing," "utilizing," and "utilized," respectively.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and/or the present specification and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

Fig. 1 shows a logical structure of a clock signal transmission apparatus according to an embodiment of the present invention. In the embodiment of the present invention, the clock signal transmission apparatus includes an on-chip optical network 101, an electrical-to-optical conversion module 102 located at an optical signal transmitting end of the on-chip optical network 101, and a plurality of optical-to-electrical conversion modules 103 located at an optical signal receiving end of the on-chip optical network 101. The electro-optical conversion module 102 receives a clock signal generated by a clock source S and converts the clock signal into a clock optical signal. The on-chip optical network 101 includes a plurality of waveguides and a replication unit (e.g., an optical splitter) through which the clock optical signal is distributed to the plurality of waveguides so as to transmit the clock optical signal to a plurality of optical-to-electrical conversion modules 103 located at different optical signal receiving ends through the plurality of waveguides. The photoelectric conversion module 103 converts the received clock optical signal into a clock electrical signal. In some embodiments, by setting the length of the waveguide, it can be achieved that the transmission distances of the respective optical paths passing through the respective waveguides are equal or substantially equal, and when the clock skew, the maximum fan-out (Max Fanout), and the maximum conversion time (Max conversion) meet the design requirements, the photoelectric conversion module 103 may be directly connected to the clock receiving end D. At this time, the plurality of waveguides of the on-chip optical network 101 constitute an optical clock tree (may be referred to as a "master clock tree") for clock balancing. In some embodiments, when the clock skew, the maximum fan-out, and the maximum conversion time do not meet the design requirements, the electrical clock balancing module 400 may be accessed between the optical-to-electrical conversion module 103 and the corresponding clock receiving end D to repair the clock balance, for example, the electrical clock balancing module 400 may include a clock tree (may be referred to as a "sub-clock tree"), the sub-clock tree may be used to repair the clock balance, or further repair the maximum fan-out and the maximum conversion time. The sub-clock tree included in the electric clock balancing module 400 is an electric clock tree, and is mainly formed by connecting logic devices such as buffers and/or inverters through electric lines. In some embodiments, the clock bias may be adjusted by adjusting the waveguide length, the electrical line length, the sub-clock tree; the maximum fan-out is typically adjustable through the sub-clock trees; the maximum switching time can be adjusted by adjusting the maximum fan-out, transmission distance, line RC (resistance capacitance). In some embodiments, the delay time for transmitting the clock origin to each optical signal receiving end (including the optical-to-electrical conversion module) via the optical chip is marked into the clock signal origin of the electrical clock balancing module 400, so as to modify the clock signal to help complete the timing analysis.

In some embodiments, the clock signal transmission device includes a Photonic Integrated Circuits (PIC) chip including the above-mentioned electro-optical conversion module 102, an on-chip optical network 101 containing the optical clock tree, and a plurality of photoelectric conversion modules 103.

In some embodiments, the optical clock balancing apparatus of the present invention includes the above-mentioned electro-optical conversion module 102, the on-chip optical network 101 including the optical clock tree, and a plurality of electro-optical conversion modules 103. At this time, the optical balance device is used for clock balance. In some embodiments, the optical clock balancing device is implemented as the PIC chip. In an alternative embodiment, the on-chip optical network 101 may not have a clock balancing function, that is, transmission distances of optical paths passing through waveguides are not equal, and at this time, the plurality of optical-to-electrical conversion modules 103 need to be connected to the electrical clock balancing module 400 for clock balancing.

[ example 1 ]

Fig. 2 shows example 1 of the clock signal transmission apparatus according to the embodiment of the present invention. In embodiment 1, as shown in fig. 2, the clock signal transmission apparatus includes a PIC chip 100, where the PIC chip 100 includes an on-chip optical network 101, which includes an optical signal transmitting end, a plurality of optical signal receiving ends, a plurality of waveguides 105 connecting the optical signal transmitting end and the optical signal receiving ends, and a replication unit 104. The PIC chip 100 further includes an electrical-to-optical conversion module 102, which is disposed at the optical signal transmitting end, and is configured to receive a clock electrical signal from a clock source S, convert the clock electrical signal into a clock optical signal, where the clock optical signal is copied or distributed to different waveguides 105 by the copying unit 104, and is transmitted to different optical signal receiving ends through different waveguides 105. The PIC chip 100 further includes a plurality of photoelectric conversion modules 103, which are respectively disposed at the plurality of optical signal receiving ends, and are configured to convert the respective received clock optical signals into clock electrical signals. In some embodiments, the plurality of waveguides 105 are configured to approximately equalize the transmission time of the clock optical signal from the optical signal transmitting end to different optical signal receiving ends, for example, the plurality of waveguides 105 are configured to approximately equalize the transmission distance of the clock optical signal from the electro-optical conversion module 102 to different photoelectric conversion modules 103, thereby achieving clock balance. That is, the plurality of waveguides 105 on the on-chip optical network 101 may form an optical clock tree for clock balancing. Therefore, the photoelectric conversion module 103 can be directly connected to the clock receiving terminal D. In this embodiment, the clock source S may be a Phase Locked Loop (PLL) circuit integrated in an Electronic Integrated Circuit (EIC) chip 200. In other embodiments, the clock source S may also be an external clock source integrated on the EIC chip 200. In some embodiments, the on-chip optical network 101 may be separately formed on a substrate or an interposer, and a plurality of photonic integrated circuit chips are disposed on the substrate or the interposer, wherein an electrical-to-optical conversion module is disposed on one of the photonic integrated circuit chips, and a photoelectric conversion module is disposed on the remaining plurality of photonic integrated circuit chips. According to this embodiment, the on-chip optical network 101 itself includes an optical clock tree that implements clock balancing, and thus, it can be used as a clock balancing system. Therefore, the electro-optical conversion module 102, the on-chip optical network 101, and the photoelectric conversion module 103 may constitute an optical clock balancing device, and perform a clock balancing function. In an alternative embodiment, the plurality of waveguides 105 in the same clock balancing system are configured to enable transmission distances of the clock optical signal from the optical signal transmitting end to different optical signal receiving ends to be approximately equal; the plurality of waveguides in different clock balance systems are arranged to make the transmission distances of the clock optical signals from the optical signal transmitting end to different optical signal receiving ends approximately equal or unequal.

In an exemplary embodiment of the present invention, as shown in fig. 6, the electro-optical conversion module 102 includes a modulator and a light source disposed on the PIC chip 100, wherein a digital-to-analog conversion unit disposed on the EIC chip 200 converts a clock digital electrical signal generated by a clock source S into a clock analog electrical signal, the clock electrical signal is transmitted to the PIC chip 100 through a conductive path, and the modulator disposed on the PIC chip 100 modulates the clock analog electrical signal into an optical signal generated by the light source, so as to obtain a clock optical signal carrying clock information. The clock optical signal is transmitted to the plurality of photoelectric conversion modules 103 through an on-chip optical network including a replica unit and a plurality of waveguides. Each of the photoelectric conversion modules 103 includes a detection unit disposed on the PIC chip 100, wherein the detection unit includes, for example, a photodiode, and is configured to convert a received clock optical signal into a clock analog electrical signal. The clock analog electrical signal is transmitted to the EIC chip 200 through a conductive path, and an analog-to-digital conversion unit arranged in the EIC chip 200 converts the clock analog electrical signal into a clock digital electrical signal which is sent to different clock receiving ends D, so that clock synchronization is realized by the different clock receiving ends D. In this embodiment, different clock receiving terminals D and clock sources S are integrated in the same EIC chip 200. In an alternative embodiment, the clock receiving end D and the clock source S may be on different EIC chips.

[ example 2 ]

Fig. 3 shows example 2 of the clock signal transmission apparatus according to the embodiment of the present invention. In embodiment 2, the clock signal transmission apparatus has substantially the same structure as the clock signal transmission apparatus of embodiment 1, and the main difference therebetween is that the clock signal transmission apparatus of embodiment 2 further includes an electrical clock balancing module 400 integrated in the EIC chip 200, which is directly communicatively connected to the photoelectric conversion module 103. The electrical clock balancing module 400 includes an electrical clock tree, through which a clock receiving end receives a clock electrical signal from the photoelectric conversion module 103, and the electrical clock tree performs clock balancing repair. In some embodiments, the clock signal transmitting means is configured to mark a delay time of a clock signal transmitted from the clock source S to each optical signal receiving end via the on-chip optical network 101 into a clock signal origin of the electrical clock balancing module 400. That is, in embodiment 2, a clock tree is established with the position where each clock optical signal is converted into a clock electrical signal as an origin to perform clock balancing, maximum fan-out, and maximum conversion time restoration, thereby completing connection of the clock receiving end.

In alternative embodiments, the electrical clock balancing module 400 may be disposed on another EIC chip or other electronic device that is independent of the EIC chip 200 on which the clock source S is located.

[ example 3 ] A method for producing a polycarbonate

Fig. 4 shows example 3 of the clock signal transmission apparatus according to the embodiment of the present invention. In the embodiment 3, the clock signal transmission apparatus has substantially the same structure as the clock signal transmission apparatus of the embodiment 2, and the main difference between the two is that the embodiment 3 can directly receive the clock signal of the clock source S through the electric clock balancing module 400 for those clock receiving ends which do not need to be clock balanced. In this embodiment, when there is no necessity for clock balancing at a part of the clock receiving terminals, the clock signal generated by the clock source S may be directly transmitted to the clock receiving terminals through the clock tree of the electrical clock balancing module 400 without transmission through the on-chip optical network of the PIC chip 100.

[ example 4 ]

Fig. 5 shows example 4 of the clock signal transmission apparatus according to the embodiment of the present invention. In embodiment 4, the clock signal transmission apparatus has a structure substantially the same as that of the clock signal transmission apparatus in embodiment 3, and the main difference between the two is that, in embodiment 4, for a part of the clock receiving terminals D, after clock balancing is performed through the on-chip optical network 101 on the PIC chip 100, the clock skew, the maximum fan-out, the maximum conversion time, and the like have reached design requirements, and the part of the clock receiving terminals D can be directly connected to the photoelectric conversion module 103 to receive a clock signal; for the other part of the clock receiving ends, the clock signal needs to be received by the electric clock balancing module 400, and the clock balance is repaired by the electric clock balancing module 400, so that the clock deviation, the maximum fan-out, the maximum conversion time and the like reach the design requirements.

The clock signal transmission device of the present invention has been specifically described above with reference to various embodiments, and a method for manufacturing the clock signal transmission device will be described below.

In some embodiments, a method of manufacturing the clock signal transmission apparatus includes:

s1: providing an on-chip optical network, wherein the on-chip optical network comprises an optical signal sending end, a plurality of optical signal receiving ends and a plurality of waveguides for connecting the optical signal sending end and the optical signal receiving ends;

s2: the optical signal transmitting end is provided with an electro-optical conversion module, the electro-optical conversion module is arranged to receive a clock electrical signal from a clock source and convert the clock electrical signal into a clock optical signal, and the clock optical signal is transmitted to different optical signal receiving ends through different waveguides; and

s3: a plurality of photoelectric conversion modules are provided at the plurality of optical signal receiving ends, each photoelectric conversion module being configured to convert a respective received clock optical signal into a clock electrical signal.

In some embodiments, the method of manufacturing further comprises: and adjusting the length of each waveguide to enable the transmission time of the clock optical signal from the optical signal transmitting end to different optical signal receiving ends to be approximately equal. For example, the lengths of the respective waveguides are adjusted so that the transmission distances of the clock optical signal from the optical signal transmitting end to the different optical signal receiving ends are substantially equal. In an exemplary embodiment, the electro-optical conversion module is used as a clock signal source of the on-chip optical network, completes connection of a farthest end clock signal receiving end through a waveguide, and calculates a transmission distance; completing the connection of other clock receiving ends through other waveguides; the lengths of the optical waveguides are adjusted by waveguide wiring design so that the transmission distances of the respective optical paths are equal or substantially equal according to the longest transmission distance. The on-chip optical network may then be fabricated by forming waveguides on a substrate or substrate used to form the on-chip optical network according to the waveguide routing design.

In some embodiments, the lengths of the waveguides may be adjusted according to the above method, so that different waveguides in the same clock balance system are set to make the transmission distances of the clock optical signals from the optical signal transmitting end to different optical signal receiving ends approximately equal. In some embodiments, the lengths of the waveguides may be adjusted according to the above method, so that the transmission distances of the clock optical signals from the optical signal transmitting end to the different optical signal receiving ends by the different waveguides located in different clock balancing systems are substantially equal or unequal.

In some embodiments, the method of manufacturing further comprises: providing at least one electrical clock balancing module in communicative connection with at least one of the plurality of photoelectric conversion modules to receive a clock electrical signal from the at least one photoelectric conversion module and to restore clock balance. In some embodiments, the electrical clock balancing module includes a clock tree to repair clock skew, maximum fan-out, and maximum transition time to meet design requirements. The clock tree includes buffers, inverters, and/or other logic devices.

In some embodiments, the method of manufacturing further comprises: and configuring the clock signal transmission device to enable the clock signal transmission device to mark the delay time of the clock signal transmitted from the clock source to each optical signal receiving end through the on-chip optical network into the origin of the clock signal of the electric clock balancing module so as to help complete timing analysis.

It should be understood by those skilled in the art that the foregoing is only illustrative of the embodiments of the present invention, and is not intended to limit the scope of the invention as claimed.

Claims

1. A clock signal transmission apparatus, comprising:

the optical network on chip comprises an optical signal transmitting end, a plurality of optical signal receiving ends and a plurality of waveguides which connect the optical signal transmitting end and the optical signal receiving ends;

2. The clock signal transmission apparatus of claim 1, wherein the plurality of waveguides are arranged to substantially equalize transmission times of the clock optical signal from the optical signal transmitting end to different optical signal receiving ends.

3. The clock signal transmission apparatus of claim 2, wherein the plurality of waveguides are arranged such that transmission distances of the clock optical signal from the optical signal transmitting end to different optical signal receiving ends are substantially equal.

4. The clock signal transmission apparatus according to claim 1, wherein different waveguides in the same clock balancing system among the plurality of waveguides are arranged such that transmission distances of the clock optical signal from the optical signal transmitting end to different optical signal receiving ends are substantially equal.

5. The clock signal transmission apparatus according to claim 4, wherein different ones of the plurality of waveguides located in different clock balancing systems are arranged such that transmission distances of the clock optical signal from the optical signal transmitting end to different optical signal receiving ends are substantially equal or unequal.

6. The clock signal transmission device according to claim 1, further comprising at least one electrical clock balancing module communicatively connected to at least one of the plurality of photoelectric conversion modules, for receiving the clock electrical signal from the at least one photoelectric conversion module and repairing clock balancing.

7. The clock signal transmission apparatus according to claim 6, wherein the clock signal transmission apparatus is configured to mark a delay time of a clock signal transmitted from the clock source to each optical signal receiving end via the on-chip optical network into a clock signal origin of the electrical clock balancing module.

8. The clock signal transmission apparatus of claim 6, wherein the electrical clock balancing module comprises a clock tree.

9. The clock signal transmission device according to any one of claims 1 to 8, wherein the clock signal transmission device comprises a photonic integrated circuit chip including the on-chip optical network, the electro-optical conversion module, and the optical-to-electrical conversion module.

10. A method of manufacturing a clock signal transmission device, comprising:

11. The manufacturing method according to claim 10, further comprising:

and adjusting the length of each waveguide to enable the transmission time of the clock optical signal from the optical signal transmitting end to different optical signal receiving ends to be approximately equal.

12. The manufacturing method according to claim 11, wherein the length of each waveguide is adjusted so that the transmission distances of the clock optical signal from the optical signal transmitting end to different optical signal receiving ends are substantially equal.

13. The manufacturing method according to claim 10, further comprising:

the lengths of the waveguides are adjusted so that different waveguides in the same clock balance system are set to make the transmission distances of the clock optical signal from the optical signal transmitting end to different optical signal receiving ends approximately equal.

14. The manufacturing method according to claim 13, further comprising:

and adjusting the length of each waveguide to enable the transmission distances of the clock optical signals transmitted from the optical signal transmitting end to different optical signal receiving ends by different waveguides positioned in different clock balance systems to be approximately equal or unequal.

15. The manufacturing method according to claim 10, further comprising:

providing at least one electrical clock balancing module communicatively coupled to at least one of the plurality of photoelectric conversion modules to receive the clock electrical signal from the at least one photoelectric conversion module and to restore clock balance.

16. The method of manufacturing according to claim 15, further comprising:

and configuring the clock signal transmission device to enable the clock signal transmission device to mark the delay time of the clock signal transmitted from the clock source to each optical signal receiving end through the on-chip optical network into the origin of the clock signal of the electric clock balancing module.

17. The method of manufacturing of claim 15, wherein the electrical clock balancing module comprises a clock tree.

18. The manufacturing method according to any one of claims 10 to 17, wherein the clock signal transmission device includes a photonic integrated circuit chip including the on-chip optical network, the electro-optical conversion module, and the photoelectric conversion module.

19. An optical clock balancing apparatus, comprising: