CN115085731A - Input signal amplitude detection circuit with adjustable wide-range high-linearity output signal - Google Patents

Input signal amplitude detection circuit with adjustable wide-range high-linearity output signal Download PDF

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CN115085731A
CN115085731A CN202210642760.7A CN202210642760A CN115085731A CN 115085731 A CN115085731 A CN 115085731A CN 202210642760 A CN202210642760 A CN 202210642760A CN 115085731 A CN115085731 A CN 115085731A
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resistor
adjustable
input
operational amplifier
detection circuit
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陈中天
张凡武
黄晶晶
方利志
雷鹏
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Dongfeng Motor Corp
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Dongfeng Motor Corp
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/34—Negative-feedback-circuit arrangements with or without positive feedback
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/45—Differential amplifiers
    • H03F3/45071—Differential amplifiers with semiconductor devices only
    • H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
    • H03F3/45179—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using MOSFET transistors as the active amplifying circuit
    • H03F3/45183—Long tailed pairs
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/68—Combinations of amplifiers, e.g. multi-channel amplifiers for stereophonics

Abstract

The invention provides an input signal amplitude detection circuit with adjustable wide-range high-linearity output signals, which performs amplitude detection and peak detection by adopting an operational amplifier with a rail-to-rail structure and an error amplifier with adjustable amplification factor consisting of a resistor array with switch control, improves the conversion efficiency of the input signal amplitude detection circuit, enables the range of output detection voltage to be adjustable, and improves the linearity of signal detection. The invention uses the rail-to-rail operational amplifier in the signal detection circuit, thereby improving the detection range of the input signal. The invention introduces V on the basis of the traditional design cm Will V cm And V dm Performs an operation to cancel the output voltage V pkd In (1)And the common mode component improves the linearity of signal detection. The invention uses the error amplifier with the MOS switch control resistor array to realize the function of adjustable output detection voltage range. The invention can be widely applied to products related to department analog integrated circuits and signal amplitude detection.

Description

Input signal amplitude detection circuit with adjustable wide-range high-linearity output signal
Technical Field
The invention belongs to the technical field of analog integrated circuits, and particularly relates to an input signal amplitude detection circuit with adjustable wide-range high-linearity output signals.
Background
In the serial communication technology, the higher the data transmission rate is, the greater the attenuation of the signal amplitude is under the same transmission distance, so the lower the signal amplitude received by the data receiving end is, the lower the received signal amplitude is, the more error code is easily caused, and the error rate is higher. In order to ensure that the error rate of the signal received by the data receiving end can be controlled to a suitable degree, the amplitude of the received signal is often required to be ensured.
It is necessary to provide a signal amplitude detection circuit at the data receiving end for detecting the amplitude of the received signal. When the amplitude of the received signal is detected to change from a normal value to a lower value which may cause the subsequent circuit to not normally recognize the signal, the signal amplitude detection circuit provides a decision signal to guide the subsequent circuit to perform corresponding processing. The above-described detection circuit is also referred to as a LOS (LOSs Of Signal) detection circuit. By setting the threshold value (i.e., the predetermined signal amplitude) of the LOS detection circuit, it is possible to determine whether the input signal reaches the predetermined signal amplitude.
The traditional signal amplitude detection circuit generally uses the diode characteristics of diodes or some devices to convert differential signals into single-ended nonpolar signals, and then is additionally connected with a comparator to judge whether the signal amplitude is larger than a set detection threshold value, but the conversion efficiency of the method is low, and meanwhile, correct detection results cannot be obtained when the amplitude of single-ended input is small, and the correct detection results are difficult to obtain even if a common amplifier is adopted to amplify input signals. Meanwhile, the gain (single-ended output amplitude and differential input signal amplitude) is limited by the area limitation in the semiconductor manufacturing process and the actual circuit designThe ratio of degrees) will be smaller, making it difficult to achieve the signal amplitude detection function. In designing a signal amplitude detection circuit, a general amplifier (P-type/N-type operational amplifier) is generally used and the OPAMP1 and a switch-controlled resistor array are not used. V is arranged in A voltage, V, is input as a negative terminal ip Is a positive input voltage, V dm Is a differential mode voltage, V th To turn on the voltage, I ss To conduct current, K is transconductance parameter, then output voltage V pkd Comprises the following steps:
Figure BDA0003682719900000011
the input signal has the problems of narrow detection range, unadjustable output detection voltage range, poor signal detection linearity and the like, and can not be widely applied to large-scale analog integrated circuit design.
In view of this, it is urgently needed to provide a new input signal amplitude detection circuit, which solves the problem that the existing input signal amplitude detection circuit has low conversion efficiency, and when the input signal amplitude is small, the output signal amplitude approaches zero, so that the detection cannot be performed.
Disclosure of Invention
The technical problem to be solved by the invention is as follows: the input signal amplitude detection circuit with adjustable wide-range high-linearity output signals is provided and used for improving the conversion efficiency of the input signal amplitude detection circuit, enabling the range of output detection voltage to be adjustable and improving the linearity of signal detection.
The technical scheme adopted by the invention for solving the technical problems is as follows: the input signal amplitude detection circuit with adjustable wide-range high-linearity output signals comprises a MOS tube differential amplifier, a first operational amplifier OPAMP1 and an error amplifier with adjustable amplification factors; the first operational amplifier OPAMP1 is used for locking an input differential mode signal and improving the signal detection linearity; the error amplifier with the adjustable amplification factor is used for realizing the adjustable output detection voltage range; the error amplifier with the adjustable amplification factor comprises a second operational amplifier OPAMP2 and a resistor array with MOS switch control; first operational amplifier OPAMP1And the second operational amplifier OPAMP2 both employ a rail-to-rail configuration; a second operational amplifier OPAMP2 for amplifying the error; the resistor array with MOS switch control comprises an adjustable input resistor R in And an adjustable feedback resistor R f (ii) a Adjustable input resistance R in Comprising a first adjustable input resistor R in1 And a second adjustable input resistor R in2 (ii) a Adjustable feedback resistor R f Comprising a first adjustable feedback resistor R f1 And a second adjustable feedback resistor R f2 (ii) a The same-direction input end of the first operational amplifier OPAMP1 is connected with the differential mode voltage output end of the MOS tube differential amplifier, the reverse-direction input end of the first operational amplifier OPAMP1 is connected with the output end of the first operational amplifier OPAMP1 and the second adjustable input resistor R in2 Of a second adjustable input resistor R in2 Is connected to the non-inverting input of the second operational amplifier OPAMP 2; the circuit also comprises a ninth resistor R9, a tenth resistor R10 and a third MOS transistor M3; one end of the ninth resistor R9 is connected with the negative input end of the MOS tube differential amplifier, the other end of the ninth resistor R9 is connected with one end of the tenth resistor R10, and the other end of the tenth resistor R10 is connected with the positive input end of the MOS tube differential amplifier; the source of the third MOS transistor M3 is connected to a power supply terminal, the gate is connected to the series point of the ninth resistor R9 and the tenth resistor R10, the drain is a common mode voltage output terminal and is connected to the first adjustable input resistor R in1 An input terminal of (1); first adjustable input resistor R in1 Is connected to the inverting input of the second operational amplifier OPAMP 2; first adjustable feedback resistor R f1 Connected in parallel between the inverting input terminal and the output terminal of the second operational amplifier OPAMP 2; second adjustable feedback resistor R f2 One end of the second operational amplifier OPAMP2 is connected to the same-direction input end of the second operational amplifier OPAMP2, and the other end is grounded; the differential mode voltage output by the MOS tube differential amplifier is set to be V dm The common mode voltage output by the MOS tube differential amplifier is V cm Then output voltage V pkd Comprises the following steps:
Figure BDA0003682719900000031
the input voltage of the negative end of the MOS tube differential amplifier is set to be V in The positive input voltage of the MOS tube differential amplifier is V ip The on-state voltage of the MOS tube differential amplifier is V th On-state current of I ss When the transconductance parameter is K, the differential mode voltage V dm Comprises the following steps:
Figure BDA0003682719900000032
common mode voltage V cm Comprises the following steps:
Figure BDA0003682719900000033
substituting the second formula and the third formula into the first formula to obtain the output voltage V pkd Comprises the following steps:
Figure BDA0003682719900000034
according to the scheme, the MOS tube differential amplifier comprises a seventh resistor R7, an eighth resistor R8, a first MOS tube M1 and a second MOS tube M2; one ends of the seventh resistor R7 and the eighth resistor R8 are both connected with a power supply end; the other end of the seventh resistor R7 is connected with the source electrode of the first MOS transistor M1; the other end of the eighth resistor R8 is connected with the source electrode of the second MOS transistor M2; the connection point of the drain electrode of the first MOS transistor M1 and the drain electrode of the second MOS transistor M2 is a differential mode voltage output end; the grid electrode of the first MOS transistor M1 is a negative input end; the gate of the second MOS transistor M2 is the positive input terminal.
According to the scheme, the first adjustable input resistor R in1 Comprises a first resistor R1, a second resistor R2 and a third resistor R3 which are connected in series, and a first switch SW1 which is connected in parallel with two ends of the second resistor R2 and a second switch SW2 which is connected in parallel with two ends of the third resistor R3.
According to the scheme, the second adjustable input resistor R in2 The circuit comprises an eleventh resistor R11, a twenty-second resistor R22 and a thirty-third resistor R33 which are connected in series, an eleventh switch SW11 which is connected in parallel with two ends of the twenty-second resistor R22, and a twenty-second switch SW22 which is connected in parallel with two ends of the thirty-third resistor R33.
According to the scheme, the first adjustable feedback resistor R f1 The circuit comprises a fourth resistor R4, a fifth resistor R5 and a sixth resistor R6 which are connected in series, and a third switch SW3 connected in parallel to two ends of the fifth resistor R5 and a fourth switch SW4 connected in parallel to two ends of the sixth resistor R6.
According to the scheme, the second adjustable feedback resistor R f2 Comprises a forty-fourth resistor R44, a fifty-fifth resistor R55 and a sixty-sixth resistor R66 which are connected in series, and a thirty-third switch SW33 which is connected in parallel with two ends of the fifty-fifth resistor R55 and a forty-fourth switch SW44 which is connected in parallel with two ends of the sixty-sixth resistor R66.
According to the scheme, the circuit also comprises a first capacitor C1 and a second capacitor C2; one end of the first capacitor C1 is connected to the drain of the third MOS transistor M3, and the other end is grounded; one end of the second capacitor C2 is connected to the non-inverting input terminal of the first operational amplifier OPAMP1, and the other end is grounded.
According to the scheme, the carrier mobility is set as mu, and C ox When the unit gate capacitance is W, the width of the MOS tube is W, and the length of the MOS tube is L, the transconductance parameter K is:
Figure BDA0003682719900000041
the invention has the beneficial effects that:
1. the input signal amplitude detection circuit with adjustable wide-range high-linearity output signals performs amplitude detection and peak detection by adopting the operational amplifier with a rail-to-rail structure and the error amplifier with adjustable amplification factor consisting of the resistor array with switch control, improves the conversion efficiency of the input signal amplitude detection circuit, enables the range of output detection voltage to be adjustable, and improves the linearity of signal detection.
2. The invention uses the rail-to-rail operational amplifier in the signal detection circuit, thereby improving the detection range of the input signal.
3. The invention introduces V on the basis of the traditional design cm A V is measured cm And V dm Performs an operation to cancel the output voltage V pkd In a common mode component, improves signal detectionThe linearity of (2).
4. The invention uses the error amplifier with the MOS switch control resistor array to realize the function of adjustable output detection voltage range.
5. The invention can be widely applied to products related to department analog integrated circuits and signal amplitude detection.
Drawings
Fig. 1 is a circuit diagram of a conventional signal amplitude detection circuit.
FIG. 2 shows an introduction V of an embodiment of the present invention cm The signal amplitude detection circuit of (1).
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings and specific embodiments.
Referring to fig. 1, an embodiment of the present invention includes a first operational amplifier OPAMP1 and a second operational amplifier OPAMP2, and an adjustable amplification error amplifier comprised of an array of MOS switch controlled resistors.
The first operational amplifier OPAMP1 and the second operational amplifier OPAMP2 both adopt a rail-to-rail structure and are used for optimizing a signal detection range; the first operational amplifier OPAMP1 is used for locking an input differential mode signal and improving the signal detection linearity; the second operational amplifier OPAMP2 is used to amplify the error.
Let R in The adjustable input resistor consists of a first resistor R1, a second resistor R2, a third resistor R3 and a MOS switch controlled by a first switch SW1 and a second switch SW 2; r f The adjustable feedback resistor consists of a fourth resistor R4, a fifth resistor R5, a sixth resistor R6 and a MOS switch controlled by a third switch SW3 and a fourth switch SW 4; the error amplifier with the MOS switch control resistor array is used for realizing adjustable output detection voltage range; let V dm Is a differential mode voltage, V cm Is a common mode voltage, then the output voltage V pkd Comprises the following steps:
Figure BDA0003682719900000051
let V in A voltage, V, is input as a negative terminal ip Is a positive input voltage, V th To turn on the voltage, I ss To conduct current, K is transconductance parameter, then the differential mode voltage V dm Comprises the following steps:
Figure BDA0003682719900000052
common mode voltage V cm Comprises the following steps:
Figure BDA0003682719900000053
let u be the carrier mobility, C ox When the unit gate capacitance is W, the width of the MOS tube is W, and the length of the MOS tube is L, the transconductance parameter K is:
Figure BDA0003682719900000054
substituting the second formula and the third formula into the first formula to obtain the output voltage V pkd Comprises the following steps:
Figure BDA0003682719900000055
the invention introduces the common-mode voltage V on the basis of the traditional design cm Will common mode voltage V cm And differential mode voltage V dm Operating to cancel the output voltage V pkd The common-mode component realizes wide-range input, high linearity and adjustable output detection voltage of signal amplitude detection; the output detection voltage is adjustable and used for meeting requirements of ADC circuits connected with different sampling ranges, and signal amplitude detection indication is achieved.
The above embodiments are only used for illustrating the design idea and features of the present invention, and the purpose of the present invention is to enable those skilled in the art to understand the content of the present invention and implement it accordingly, and the protection scope of the present invention is not limited to the above embodiments. Therefore, all equivalent changes and modifications made in accordance with the principles and concepts disclosed herein are intended to be included within the scope of the present invention.

Claims (8)

1. Input signal amplitude detection circuit that wide range high linearity output signal is adjustable, its characterized in that: the differential amplifier comprises a MOS tube differential amplifier, a first operational amplifier OPAMP1 and an error amplifier with adjustable amplification factor; the first operational amplifier OPAMP1 is used for locking an input differential mode signal and improving the signal detection linearity; the error amplifier with the adjustable amplification factor is used for realizing the adjustable output detection voltage range;
the error amplifier with the adjustable amplification factor comprises a second operational amplifier OPAMP2 and a resistor array with MOS switch control; the first operational amplifier OPAMP1 and the second operational amplifier OPAMP2 both employ a rail-to-rail configuration; a second operational amplifier OPAMP2 for amplifying the error;
the resistor array with MOS switch control comprises an adjustable input resistor R in And an adjustable feedback resistor R f (ii) a Adjustable input resistance R in Comprising a first adjustable input resistor R in1 And a second adjustable input resistor R in2 (ii) a Adjustable feedback resistor R f Comprising a first adjustable feedback resistor R f1 And a second adjustable feedback resistor R f2 ；
The same-direction input end of the first operational amplifier OPAMP1 is connected with the differential mode voltage output end of the MOS tube differential amplifier, and the reverse-direction input end of the first operational amplifier OPAMP1 is connected with the output end of the first operational amplifier OPAMP1 and the second adjustable input resistor R in2 Of a second adjustable input resistor R in2 Is connected to the non-inverting input of the second operational amplifier OPAMP 2;
the circuit also comprises a ninth resistor R9, a tenth resistor R10 and a third MOS transistor M3; one end of the ninth resistor R9 is connected with the negative input end of the MOS tube differential amplifier, the other end of the ninth resistor R9 is connected with one end of the tenth resistor R10, and the other end of the tenth resistor R10 is connected with the positive input end of the MOS tube differential amplifier; the source of the third MOS transistor M3 is connected to a power supply terminal, the gate is connected to the series point of the ninth resistor R9 and the tenth resistor R10, the drain is a common mode voltage output terminal and is connected to the first adjustable input resistor R in1 An input terminal of (1); first adjustable inputResistance R in1 Is connected to the inverting input of the second operational amplifier OPAMP 2; first adjustable feedback resistor R f1 Connected in parallel between the inverting input terminal and the output terminal of the second operational amplifier OPAMP 2; second adjustable feedback resistor R f2 One end of the second operational amplifier OPAMP2 is connected to the same-direction input end of the second operational amplifier OPAMP2, and the other end is grounded;
the differential mode voltage output by the MOS tube differential amplifier is set to be V dm The common mode voltage output by the MOS tube differential amplifier is V cm Then output voltage V pkd Comprises the following steps:
Figure FDA0003682719890000011
the input voltage of the negative end of the MOS tube differential amplifier is set to be V in The positive input voltage of the MOS tube differential amplifier is V ip The conduction voltage of the MOS tube differential amplifier is V th On-state current of I ss If the transconductance parameter is K, the differential mode voltage is V dm Comprises the following steps:
Figure FDA0003682719890000021
common mode voltage V cm Comprises the following steps:
Figure FDA0003682719890000022
substituting the second formula and the third formula into the first formula to obtain the output voltage V pkd Comprises the following steps:
Figure FDA0003682719890000023
2. the input signal amplitude detection circuit of claim 1, wherein:
the MOS tube differential amplifier comprises a seventh resistor R7, an eighth resistor R8, a first MOS tube M1 and a second MOS tube M2;
one ends of the seventh resistor R7 and the eighth resistor R8 are both connected with a power supply end; the other end of the seventh resistor R7 is connected with the source electrode of the first MOS transistor M1; the other end of the eighth resistor R8 is connected with the source electrode of the second MOS transistor M2; the connection point of the drain electrode of the first MOS transistor M1 and the drain electrode of the second MOS transistor M2 is a differential mode voltage output end; the grid electrode of the first MOS transistor M1 is a negative input end; the gate of the second MOS transistor M2 is the positive input terminal.
3. The input signal amplitude detection circuit of claim 1, wherein:
first adjustable input resistor R in1 Comprises a first resistor R1, a second resistor R2 and a third resistor R3 which are connected in series, and a first switch SW1 which is connected in parallel with two ends of the second resistor R2 and a second switch SW2 which is connected in parallel with two ends of the third resistor R3.
4. The input signal amplitude detection circuit of claim 1, wherein:
second adjustable input resistor R in2 The circuit comprises an eleventh resistor R11, a twenty-second resistor R22 and a thirty-third resistor R33 which are connected in series, an eleventh switch SW11 which is connected in parallel with two ends of the twenty-second resistor R22, and a twenty-second switch SW22 which is connected in parallel with two ends of the thirty-third resistor R33.
5. The input signal amplitude detection circuit of claim 1, wherein:
first adjustable feedback resistor R f1 The circuit comprises a fourth resistor R4, a fifth resistor R5 and a sixth resistor R6 which are connected in series, and a third switch SW3 connected in parallel to two ends of the fifth resistor R5 and a fourth switch SW4 connected in parallel to two ends of the sixth resistor R6.
6. The input signal amplitude detection circuit of claim 1, wherein:
second adjustable feedback resistor R f2 Comprises a forty-fourth resistor R44, a fifty-fifth resistor R55 and a sixty-sixth resistor R66 which are connected in series, and a thirty-third switch SW33 which is connected in parallel with two ends of the fifty-fifth resistor R55 and a forty-fourth switch SW44 which is connected in parallel with two ends of the sixty-sixth resistor R66.
7. The input signal amplitude detection circuit of claim 1, wherein:
further comprising a first capacitance C1 and a second capacitance C2;
one end of the first capacitor C1 is connected to the drain of the third MOS transistor M3, and the other end is grounded;
one end of the second capacitor C2 is connected to the non-inverting input terminal of the first operational amplifier OPAMP1, and the other end is grounded.
8. The input signal amplitude detection circuit of claim 1, wherein:
let u be the carrier mobility, C ox When the unit gate capacitance is W, the width of the MOS tube is W, and the length of the MOS tube is L, the transconductance parameter K is:
Figure FDA0003682719890000031
CN202210642760.7A 2022-06-08 2022-06-08 Input signal amplitude detection circuit with adjustable wide-range high-linearity output signal Pending CN115085731A (en)

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