CN115085712B - Process integration method for SONOS (silicon oxide nitride oxide semiconductor) type pFLSH (pulse frequency absorption laser) switch unit structure - Google Patents
Process integration method for SONOS (silicon oxide nitride oxide semiconductor) type pFLSH (pulse frequency absorption laser) switch unit structure Download PDFInfo
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- 238000000034 method Methods 0.000 title claims abstract description 106
- 230000010354 integration Effects 0.000 title claims abstract description 15
- 239000004065 semiconductor Substances 0.000 title description 11
- 229910052814 silicon oxide Inorganic materials 0.000 title description 3
- -1 silicon oxide nitride Chemical class 0.000 title description 3
- 238000010521 absorption reaction Methods 0.000 title 1
- 230000008054 signal transmission Effects 0.000 claims abstract description 65
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 44
- 229910052757 nitrogen Inorganic materials 0.000 claims description 25
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 22
- 239000002184 metal Substances 0.000 claims description 18
- 230000003647 oxidation Effects 0.000 claims description 18
- 238000007254 oxidation reaction Methods 0.000 claims description 18
- 238000005530 etching Methods 0.000 claims description 13
- 229920005591 polysilicon Polymers 0.000 claims description 10
- 238000005229 chemical vapour deposition Methods 0.000 claims description 6
- 150000004767 nitrides Chemical class 0.000 claims description 6
- 238000009279 wet oxidation reaction Methods 0.000 claims description 6
- 238000000151 deposition Methods 0.000 claims description 5
- 229910052760 oxygen Inorganic materials 0.000 claims description 4
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 claims description 3
- 239000005380 borophosphosilicate glass Substances 0.000 claims description 3
- 230000007797 corrosion Effects 0.000 claims description 3
- 238000005260 corrosion Methods 0.000 claims description 3
- 239000007789 gas Substances 0.000 claims description 3
- 238000002347 injection Methods 0.000 claims description 3
- 239000007924 injection Substances 0.000 claims description 3
- 238000005468 ion implantation Methods 0.000 claims description 3
- 238000004519 manufacturing process Methods 0.000 claims description 3
- 239000000758 substrate Substances 0.000 claims description 3
- 238000007740 vapor deposition Methods 0.000 claims description 3
- 239000010409 thin film Substances 0.000 claims 1
- 230000005855 radiation Effects 0.000 abstract description 10
- 238000002360 preparation method Methods 0.000 abstract description 8
- 238000005516 engineering process Methods 0.000 abstract description 2
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- 230000009286 beneficial effect Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000002708 enhancing effect Effects 0.000 description 1
- 230000036039 immunity Effects 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
- H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
- H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
- H03K17/6871—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors the output circuit comprising more than one controlled field-effect transistor
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/022—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being a laminate, i.e. composed of sublayers, e.g. stacks of alternating high-k metal oxides
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
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- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
- H01L21/0223—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate
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- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
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- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
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Abstract
The invention relates to the technical field of microelectronic integrated circuits, in particular to a process integration method of a SONOS type pFLSH switch unit structure, which comprises the following steps: the device comprises two pMOS selection tubes 1A and 1B, two SONOS type pFLASH tubes 2A and 2B and a pMOS signal transmission tube, wherein the SONOS type pFLASH switch unit structure is a symmetrical structure consisting of two 2T-FLASH structure units T1 and T2, the T1 consists of one pMOS selection tube 1A and one SONOS type pFLASH tube 2A, and the T2 consists of one pMOS selection tube 1B and one SONOS type pFLASH tube 2B; the process integration technology can effectively improve the signal transmission capability and enhance the radiation resistance and durability, thereby realizing the preparation of the high-speed, high-reliability and radiation-resistant FPGA configuration unit.
Description
Technical Field
The invention relates to the technical field of microelectronic integrated circuits, in particular to a process integration method of an SONOS (silicon oxide nitride oxide semiconductor) type pFLASH (plasma-frequency laser diode) switch unit structure.
Background
Currently, mainstream FPGA configuration units in the market mainly include three types: the anti-fuse FPGA has the defects of weak single particle radiation resistance, loss of data and the like, and the anti-fuse FPGA has no reconfigurability and does not meet the development requirements of the FPGA in the future. The FLASH structural unit has the excellent characteristics of high integration level, low power consumption, reconfigurability, single event firmware error immunity resistance and the like, and is one of the better selection schemes of high reliability, radiation resistance and reconfigurable FPGA.
The FLASH type FPGA mainly adopts a sensor-Switch type or Push-Pull Switch unit structure, wherein the sensor tube and the Switch tube of the sensor-Switch type FLASH have the problems of poor anti-interference capability and the like because the erasing/writing tube and the signal transmission tube share a floating gate. The Push-Pull type FLASH switch unit has the advantages of strong signal transmission capability and the like because the erasing/writing tube is isolated from the signal transmission switch tube, but the traditional SONOS type cFLASH structure unit still has the disadvantages of poor radiation resistance, poor durability and the like.
The invention utilizes the natural radiation resistance performance advantage of the SONOS type pFLASH, adopts a stacked gate oxide process to prepare a gate oxide layer of the pMOS selection tube, adopts a low-temperature thermal oxidation nitrogen (N) doping process to prepare a bottom oxide of an ONO dielectric layer and a gate oxide of a pMOS signal transmission tube in the SONOS type pFLASH tube, and adopts an HTO process to prepare a top oxide of the ONO dielectric layer in the SONOS type pFLASH tube, thereby achieving the aim of preparing the SONOS type pFLASH switch unit with high reliability and high integration level.
Disclosure of Invention
Aiming at the defects of the prior art, the invention provides a process integration method of an SONOS type pFLASH switch unit structure, and the process integration technology can effectively improve the signal transmission capability and enhance the radiation resistance and durability, thereby realizing the preparation of a high-speed, high-reliability and radiation resistance FPGA configuration unit.
The invention is realized by the following technical scheme:
the invention provides a process integration method of a SONOS type pFLASH switch unit structure, which comprises the following steps: two pMOS selection tubes 1A and 1B, two SONOS type pFLSH tubes 2A and 2B and a pMOS signal transmission tube; the SONOS type pFLASH switch unit structure is a symmetrical structure consisting of two 2T-FLASH structure units T1 and T2, wherein T1 is composed of a pMOS selection tube 1A and a SONOS type pFLASH tube 2A, and T2 is composed of a pMOS selection tube 1B and a SONOS type pFLASH tube 2B; the connection mode of the SONOS type pFLSH pipe and the pMOS selection pipe is that the drain terminal of the SONOS type pFLSH pipe is connected with the source terminal of the pMOS selection pipe, the drain terminal of the SONOS type pFLSH pipe 2A is connected with the source terminal of the pMOS selection pipe 1A, the drain terminal of the SONOS type pFLSH pipe 2B is connected with the source terminal of the pMOS selection pipe 1B, the grid terminal of the SONOS type pFLSH pipe 2A is connected with the grid terminal of the SONOS type pFLSH pipe 2B, and the source terminals of the SONOS type pFLSH pipe 2A and the SONOS type pFLSH pipe 2B are connected with the grid terminal of the pMOS signal transmission pipe; wherein the SONOS type pFLASH tubes 2A and 2B and the pMOS selection tubes 1A and 1B share an N well 5; this pFLASH switch element still includes except that the port of the source end of the drain terminal of pFLASH pipe, pMOS select tube: drain ends 3A and 3B and gate ends 4A and 4B of two pMOS selection tubes 1A and 1B, and drain ends and source ends of pMOS signal transmission tubes; n-type ion implantation is carried out on a P-type substrate, and an N-well 5 of a pMOS selection tube 1A, a pMOS selection tube 1B, a SONOS type pFLSH tube 2A, a SONOS type pFLSH tube 2B area and an N-well 11 of a pMOS signal transmission tube are formed; the method comprises the following steps:
the method comprises the following steps: preparing a bottom oxide layer of an oxide-nitride-oxide ONO dielectric layer in an SONOS type pFLASH tube by adopting a low-temperature thermal oxidation nitrogen (N) doping process method, wherein the process temperature range is 700-850 ℃, and N is adopted2O or NO is annealed to a thickness of
Step two: depositing nitride on the bottom oxide layer of ONO dielectric layer to a thickness of
Forming a layer of oxide with a thickness of
Forming a top oxide of an ONO dielectric layer in the SONOS type pFLSH tube by an etching process at the temperature of 700-800 ℃;
step three: preparing an oxide layer by adopting a low-temperature thermal oxidation nitrogen (N) doping process method, removing the oxide layer outside the gate end regions of the pMOS selection tubes 1A and 1B, and preparing the oxide layer by adopting the low-temperature thermal oxidation nitrogen (N) doping process method again to form stacked gate oxide layers of the pMOS selection tubes 1A and 1B and a gate oxide layer of the pMOS signal transmission tube;
step four: the polycrystalline silicon layers of the pMOS selection tubes 1A and 1B, the polycrystalline silicon layers of the SONOS type pFLSH tubes 2A and 2B and the polycrystalline silicon layer of the pMOS signal transmission tube are prepared by adopting a doped polycrystalline silicon process, wherein the process temperature is as follows: 500-700 deg.C, the thickness of the polysilicon layer is
Step five: forming drain terminals 3A and 3B of a pMOS selection tube and a source terminal of a SONOS type pFLSH tube in a pMOS selection tube 1A and 1B, a SONOS type pFLSH tube 2A and 2B and a pMOS signal transmission tube through P type ion injection, or forming a gate terminal of the pMOS signal transmission tube, a drain terminal of the pMOS signal transmission tube and a source terminal of the pMOS signal transmission tube;
step six: depositing a layer of oxide or nitride on the grid, and forming side walls on two sides of the grid end of the pMOS selection tubes 1A and 1B, the SONOS type pFLSH tubes 2A and 2B and the pMOS signal transmission tube through anisotropic etching;
step seven: forming a layer of borophosphosilicate glass by chemical vapor deposition; positioning drain ends 3A and 3B of a pMOS (programmable gate array) selection tube, gate ends 4A and 4B of the pMOS selection tube, a gate end of an SONOS type pFLSH tube and a source end of the SONOS type pFLSH tube, or positioning a gate end of a pMOS signal transmission tube, a drain end of the pMOS signal transmission tube and a first layer of metal connecting port of the source end of the pMOS signal transmission tube, and forming a through hole by corrosion;
step eight: and forming a layer of metal by adopting chemical vapor deposition, and forming a first metal connecting layer after corroding the metal in the redundant region.
Preferably, in the third step, the gate oxide layer of the pMOS select transistor is prepared by a stacked gate oxide process, and the stacked gate oxide process is a low-temperature wet oxidation process and a nitrogen (N) doping process.
Preferably, the low-temperature thermal oxidation nitrogen (N) doping process is a low-temperature wet oxidation process and a nitrogen (N) doping process, and is mainly used for a bottom oxide of an oxide-nitride-oxide ONO dielectric layer in an SONOS-type pFLASH tube and a pMOS signal transmission tube oxide.
Preferably, in the preparation process of the HTO process, the HTO film is prepared by adopting a low-pressure vapor deposition LVCVD device, and the preparation gas is N2O and SiH4。
The invention has the beneficial effects that:
the invention adopts a process integration method of the SONOS type pFLASH switch unit, and realizes the isolation of an erasing/writing tube and a signal transmission switch tube by utilizing the natural radiation resistance advantage of a p-type device and a Push-Pull type structure; the gate oxide layer quality of a pMOS selection tube, the bottom oxide of an ONO dielectric layer in an SONOS type pFLSH tube and the gate oxide layer quality of a pMOS signal transmission tube are improved by adopting a low-temperature thermal oxidation nitrogen (N) doping process; the defect of the top oxide layer of an ONO dielectric layer in the SONOS type pFLSH tube is reduced by utilizing an HTO process method, and the purposes of improving the signal transmission capability and enhancing the radiation resistance and the durability are achieved.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the embodiments or the prior art descriptions will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and other drawings can be obtained by those skilled in the art without creative efforts.
Fig. 1 to 8 are the main process flow for the preparation ofbase:Sub>A SONOS type pFLASH switch cell, according to the convention of the semiconductor industry, all the sectional views of the present invention are not drawn to scale, but only the main process steps of the device structure, wherein thebase:Sub>A-base:Sub>A 'sectional view includesbase:Sub>A pMOS select transistor,base:Sub>A SONOS type pFLASH transistor, and the B-B' sectional view includesbase:Sub>A pMOS signal pass transistor.
Fig. 1 is a schematic structural diagram of a SONOS type pFLASH switch unit according to the present invention.
FIG. 2 shows a cross-sectional view and a top view of a semiconductor process to complete an N-well implant; where a is a top view of the completed N-well 5, b is a top view of the completed N-well 11, c is a cross-sectional view of the completed N-well 5, and d is a cross-sectional view of the completed N-well 11.
FIG. 3 shows a cross-sectional view and a top view of a semiconductor process completing the growth of an underlying oxide; wherein a is a top view of the completed N-well 5, b is a top view of the completed N-well 11, c is a cross-sectional view of the bottom oxide layer of the completed N-well 5, and d is a cross-sectional view of the bottom oxide layer of the N-well 11.
FIG. 4 shows a cross-sectional view and a top view of a semiconductor process for completing the fabrication of an ONO dielectric layer in a SONOS-type pFLSH transistor; wherein a is a top view of the ONO dielectric layer completing the N well 5, b is a top view of the ONO dielectric layer completing the N well 11, c is a cross-sectional view of the ONO dielectric layer completing the N well 5, and d is a cross-sectional view of the N well 11.
FIG. 5 shows a cross-sectional view and a top view of a semiconductor process for completing the preparation of a gate oxide layer of a pMOS selection tube and a gate oxide layer of a pMOS signal transmission tube; wherein a is the top view of the gate oxide layer of the selection tube of the pMOS, b is the top view of the gate oxide layer of the signal transmission tube of the pMOS, c is a sectional view of the gate oxide layer of the selection tube of the pMOS, and d is a sectional view of the gate oxide layer of the signal transmission tube of the pMOS.
FIG. 6 shows a cross-sectional view and a top view of a semiconductor process completing the preparation of polysilicon; wherein, a is the plan view for completing the polysilicon layer of the pMOS selection tube and the pFLSH tube, b is the plan view for completing the polysilicon layer of the pMOS signal transmission tube, c is the sectional view for completing the polysilicon layer of the pMOS selection tube and the pFLSH tube, and d is the sectional view for completing the polysilicon layer of the pMOS signal transmission tube.
FIG. 7 shows a cross-sectional view and a top view of a semiconductor process for completing sidewall and source drain implantation; the method comprises the following steps of forming a polysilicon layer of a pMOS (vertical cavity laser diode) selection tube and a pFLSH (pFLSH) tube, forming a polysilicon layer of a pMOS signal transmission tube, forming a side wall of the pMOS selection tube and the pFLSH tube, and forming a side wall of the pMOS signal transmission tube and a side wall of the pFLSH tube.
FIG. 8 shows a cross-sectional view and a top view of a semiconductor process for completing metal etching (wherein the shaded area is the interconnection of a source terminal of a SONOS type pFLSH tube and a gate terminal of a pMOS signal transmission tube); the metal etching method comprises the following steps of a, b, c and d, wherein a is a top view for finishing metal etching of a pMOS selection tube and a pFLSH tube, b is a top view for finishing metal etching of a pMOS signal transmission tube, c is a cross-sectional view for finishing metal etching of the pMOS selection tube and the pFLSH tube, and d is a cross-sectional view for finishing metal etching of the pMOS signal transmission tube.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Example 1:
as shown in fig. 1: the SONOS type pFLSH switch unit structure comprises two pMOS selection tubes 1A and 1B, two SONOS type pFLSH tubes 2A and 2B and a pMOS signal transmission tube 8; the SONOS type pFLSH switch unit structure is a symmetrical structure consisting of two 2T-FLASH structure units T1 and T2, wherein T1 consists of a pMOS selection tube 1A and a SONOS type pFLSH tube 2A, and T2 consists of a pMOS selection tube 1B and a SONOS type pFLSH tube 2B; the connection mode of the SONOS type pFLSH pipe and the pMOS selection pipe is that the drain terminal of the SONOS type pFLSH pipe is connected with the source terminal of the pMOS selection pipe, the drain terminal of the SONOS type pFLSH pipe 2A is connected with the source terminal of the pMOS selection pipe 1A, the drain terminal of the SONOS type pFLSH pipe 2B is connected with the source terminal of the pMOS selection pipe 1B, the grid terminal of the SONOS type pFLSH pipe 2A is connected with the grid terminal of the SONOS type pFLSH pipe 2B, and the source terminals of the SONOS type pFLSH pipe 2A and the SONOS type pFLSH pipe 2B are connected with the grid terminal of the pMOS signal transmission pipe; wherein the SONOS type pFLSH tubes 2A and 2B and the pMOS selection tubes 1A and 1B share an N well 5; this pFLASH switch element still includes except that the port of the source end of the drain terminal of pFLASH pipe, pMOS select tube: drain terminals 3A and 3B, gate terminals 4A and 4B of two pMOS selection tubes 1A and 1B, and drain terminals and source terminals of pMOS signal transmission tubes.
As shown in fig. 2: n-type ion implantation is carried out on a P-type substrate 12 to form an N well 5 of a region of a pMOS selection tube 1A, 1B, a SONOS type pFLSH tube 2A, 2B and an N well 11 of a pMOS signal transmission tube.
As shown in fig. 3: miningThe bottom oxide layer 13 is prepared by a low-temperature thermal oxidation nitrogen (N) doping process method, the process temperature range is 700-850 ℃, and N is adopted2O or NO is annealed to a thickness of
As shown in fig. 4: a nitride deposition 14 is performed over the bottom oxide layer 13 to a thickness of
Forming a layer of oxide with a thickness of
The temperature range is 700-800 ℃, and the top oxide 15 of the ONO dielectric layer in the SONOS type pFLASH tube is formed by the etching process.
As shown in fig. 5: and preparing an oxide layer by adopting a low-temperature thermal oxidation nitrogen (N) doping process, removing the oxide layer outside the gate end regions of the pMOS selection tubes 1A and 1B, and preparing the oxide layer by adopting the low-temperature thermal oxidation nitrogen (N) doping process again to form a stacked gate oxide layer 16 of the pMOS selection tubes 1A and 1B and a gate oxide layer 17 of the pMOS signal transmission tube.
As shown in fig. 6: the polycrystalline silicon layer 18 of the pMOS selection tubes 1A and 1B, the polycrystalline silicon layer 19 of the SONOS type pFLASH tubes 2A and 2B and the polycrystalline silicon layer 20 of the pMOS signal transmission tube 8 are prepared by adopting a doped polycrystalline silicon process, wherein the process temperature is as follows: 500-700 deg.C, the thickness of the polysilicon layer is
The gate oxide layer of the pMOS selection tube is prepared by adopting a stacked gate oxide process, wherein the stacked gate oxide process is a low-temperature wet oxidation process and a nitrogen (N) doping process.
The low-temperature thermal oxidation nitrogen (N) doping process is a low-temperature wet oxidation process and a nitrogen (N) doping process, and is mainly used for a bottom oxide of an oxide-nitride-oxide ONO dielectric layer in an SONOS type pFLASH tube and a pMOS signal transmission tube oxide.
Prepared in HTO processIn the process, the HTO film is prepared by adopting low-pressure vapor deposition LVCVD equipment, and the preparation gas is N2O and SiH4。
As shown in fig. 7: forming drain terminals 3A and 3B of the pMOS selection tubes and source terminals of the SONOS pFLSH tubes in the pMOS selection tubes 1A and 1B, the SONOS pFLSH tubes 2A and 2B and the pMOS signal transmission tube 8 or forming a gate terminal 6 of the pMOS signal transmission tube, a drain terminal 9 of the pMOS signal transmission tube and a source terminal 10 of the pMOS signal transmission tube through P-type ion injection; an oxide or nitride is deposited on the grid, and side walls 21 are formed on two sides of the grid end of the pMOS selection tubes 1A and 1B, the SONOS type pFLASH tubes 2A and 2B and the pMOS signal transmission tube 8 through anisotropic etching.
As shown in fig. 8: forming a layer of borophosphosilicate glass 22 by chemical vapor deposition; positioning drain ends 3A and 3B of a pMOS (programmable gate array) selection tube, gate ends 4A and 4B of the pMOS selection tube, a gate end 7 of an SONOS type pFLSH tube and a source end of the SONOS type pFLSH tube, or positioning a gate end 6 of a pMOS signal transmission tube, a drain end 9 of the pMOS signal transmission tube and a first layer of metal connecting port position of a source end 10 of the pMOS signal transmission tube, and forming a through hole by corrosion; a layer of metal 23 is formed by chemical vapor deposition and a first metal connection layer is formed after etching the metal in the excess area.
To sum up, the invention relates to a process integration method of an SONOS type pFLASH switch unit structure, wherein a gate end oxide layer of a pMOS selection tube is prepared by adopting a stacked gate oxygen process method, a bottom layer oxide of an ONO dielectric layer in the SONOS type pFLASH tube is prepared by adopting a low-temperature thermal oxidation nitrogen (N) doping process method, a top layer oxide is prepared by adopting an HTO process method, and a pMOS signal transmission tube gate oxide layer is prepared by adopting a low-temperature thermal oxidation nitrogen (N) doping process method.
The above examples are only intended to illustrate the technical solution of the present invention, but not to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions of the embodiments of the present invention.
Claims (4)
1. A process integration method of a SONOS type pFLSH switch unit structure comprises the following steps: two pMOS selection tubes 1A and 1B, two SONOS type pFLSH tubes 2A and 2B and a pMOS signal transmission tube; the SONOS type pFLSH switch unit structure is a symmetrical structure consisting of two 2T-FLASH structure units T1 and T2, wherein the T1 consists of a pMOS selection tube 1A and a SONOS type pFLSH tube 2A, and the T2 consists of a pMOS selection tube 1B and a SONOS type pFLSH tube 2B; the connection mode of the SONOS type pFLSH pipe and the pMOS selection pipe is that the drain end of the SONOS type pFLSH pipe is connected with the source end of the pMOS selection pipe, the drain end of the SONOS type pFLSH pipe 2A is connected with the source end of the pMOS selection pipe 1A, the drain end of the SONOS type pFLSH pipe 2B is connected with the source end of the pMOS selection pipe 1B, the grid end of the SONOS type pFLSH pipe 2A is connected with the grid end of the SONOS type pFLSH pipe 2B, and the source ends of the SONOS type pFLSH pipe 2A and the SONOS type pFLSH pipe 2B are connected with the grid end of the pMOS signal transmission pipe; wherein the SONOS type pFLSH tubes 2A and 2B and the pMOS selection tubes 1A and 1B share an N well 5; this pFLASH switch element still includes except that the port of the source end of the drain terminal of pFLASH pipe, pMOS select tube: drain ends 3A and 3B and gate ends 4A and 4B of two pMOS selection tubes 1A and 1B, and drain ends and source ends of pMOS signal transmission tubes; n-type ion implantation is carried out on a P-type substrate to form N wells 5 of pMOS selection tubes 1A and 1B, SONOS type pFLASH tubes 2A and 2B and an N well 11 of a pMOS signal transmission tube; the method is characterized by comprising the following steps:
the method comprises the following steps: preparing a bottom oxide layer of an oxide-nitride-oxide ONO dielectric layer in an SONOS type pFLASH tube by adopting a low-temperature thermal oxidation nitrogen (N) doping process method, wherein the process temperature range is 700-850 ℃, and N is adopted2O or NO is annealed to a thickness of
Step two: depositing nitride on the bottom oxide layer of ONO dielectric layer to a thickness of
Forming a layer of oxide with a thickness of
Forming a top oxide of an ONO dielectric layer in the SONOS type pFLASH tube by an etching process at the temperature of 700-800 ℃;
step three: preparing an oxide layer by adopting a low-temperature thermal oxidation nitrogen (N) doping process method, removing the oxide layer outside the gate end regions of the pMOS selection tubes 1A and 1B, and preparing the oxide layer by adopting the low-temperature thermal oxidation nitrogen (N) doping process method again to form stacked gate oxide layers of the pMOS selection tubes 1A and 1B and a gate oxide layer of the pMOS signal transmission tube;
step four: the polycrystalline silicon layers of the pMOS selection tubes 1A and 1B, the polycrystalline silicon layers of the SONOS type pFLSH tubes 2A and 2B and the polycrystalline silicon layer of the pMOS signal transmission tube are prepared by adopting a doped polycrystalline silicon process, wherein the process temperature is as follows: 500-700 deg.C, the thickness of the polysilicon layer is
Step five: forming drain terminals 3A and 3B of a pMOS selection tube and a source terminal of a SONOS type pFLSH tube in a pMOS selection tube 1A and 1B, a SONOS type pFLSH tube 2A and 2B and a pMOS signal transmission tube through P type ion injection, or forming a gate terminal of the pMOS signal transmission tube, a drain terminal of the pMOS signal transmission tube and a source terminal of the pMOS signal transmission tube;
step six: depositing a layer of oxide or nitride on the grid, and forming side walls on two sides of the grid ends of the pMOS selection tubes 1A and 1B, the SONOS type pFLASH tubes 2A and 2B and the pMOS signal transmission tube through anisotropic etching;
step seven: forming a layer of borophosphosilicate glass by chemical vapor deposition; positioning drain ends 3A and 3B of a pMOS (programmable gate array) selection tube, gate ends 4A and 4B of the pMOS selection tube, a gate end of an SONOS type pFLSH tube and a source end of the SONOS type pFLSH tube, or positioning a gate end of a pMOS signal transmission tube, a drain end of the pMOS signal transmission tube and a first layer of metal connecting port of the source end of the pMOS signal transmission tube, and forming a through hole by corrosion;
step eight: and forming a layer of metal by adopting chemical vapor deposition, and forming a first metal connecting layer after corroding the metal in the redundant region.
2. The process integration method of the SONOS-type pFLASH switch unit structure as claimed in claim 1, wherein in the third step, the gate oxide layer of the pMOS select tube is prepared by a gate-stack oxidation process, and the gate-stack oxidation process is a low-temperature wet oxidation process and a nitrogen (N) doping process.
3. The process integration method of the SONOS-type pFLASH switch cell structure of claim 1, wherein said low temperature thermal oxidation nitrogen (N) doping process is a low temperature wet oxidation process and a nitrogen (N) doping process, which is mainly used for the bottom oxide of the oxide-nitride-oxide ONO dielectric layer and the pMOS signal pass transistor oxide in the SONOS-type pFLASH transistor.
4. The integrated process for fabricating a SONOS-type pflas switch cell structure as claimed in claim 1, wherein the HTO thin film is formed by low pressure vapor deposition LVCVD during the fabrication process, and the fabrication gas is N2O and SiH4。
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