CN115084177A - Preparation method of CMOS image sensor - Google Patents
Preparation method of CMOS image sensor Download PDFInfo
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- CN115084177A CN115084177A CN202210745538.XA CN202210745538A CN115084177A CN 115084177 A CN115084177 A CN 115084177A CN 202210745538 A CN202210745538 A CN 202210745538A CN 115084177 A CN115084177 A CN 115084177A
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- image sensor
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- 238000002360 preparation method Methods 0.000 title abstract description 10
- 150000002500 ions Chemical class 0.000 claims abstract description 55
- 239000000758 substrate Substances 0.000 claims abstract description 28
- 238000000034 method Methods 0.000 claims description 39
- 238000004519 manufacturing process Methods 0.000 claims description 26
- 229920002120 photoresistant polymer Polymers 0.000 claims description 18
- 238000000151 deposition Methods 0.000 claims description 4
- 229910052698 phosphorus Inorganic materials 0.000 claims description 3
- 239000011574 phosphorus Substances 0.000 claims description 3
- -1 phosphorus ion Chemical class 0.000 claims description 3
- 238000002513 implantation Methods 0.000 abstract description 16
- 238000002955 isolation Methods 0.000 abstract description 11
- 238000005468 ion implantation Methods 0.000 description 7
- 230000003247 decreasing effect Effects 0.000 description 6
- 239000000463 material Substances 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 230000009977 dual effect Effects 0.000 description 2
- 238000007687 exposure technique Methods 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 238000012876 topography Methods 0.000 description 2
- 230000004075 alteration Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14643—Photodiode arrays; MOS imagers
Abstract
The invention provides a preparation method of a CMOS image sensor, which comprises the following steps: providing a substrate; forming a buried layer on the substrate; growing a P-type epitaxial layer on the buried layer; and injecting N-type ions into part of the P-type epitaxial layer to form a photodiode of the CMOS image sensor. Compared with the prior art, the invention can not cause the problem of higher depth-to-width ratio of P-type ion isolation implantation. Further, the occurrence of white pixels, full well capacitance and/or image sticking (Lag) is reduced, while providing advantages for further reduction of the photodiode size.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a preparation method of a CMOS image sensor.
Background
A CMOS Image Sensor (CIS) product is a semiconductor device for collecting and processing a pattern, and a PhotoDiode (PD) is applied to the CIS product as a photoelectric conversion device, so that the CIS product can convert an optical signal into an electrical signal for storage and display. With the gradual development of the application requirements of the consumer CIS towards the ultra-high resolution, the requirements on the size of the image element are smaller and smaller due to the limitation of the size of the lens. At present, the minimum pixel size of the mass-produced image element in the industry is 0.7um, and the PD needs P-type ion implantation as isolation, so the P-type ion implantation for the inter-PD isolation becomes a key factor for restricting the continuous reduction of the pixel size of the CIS.
The CD for P-type ion implantation is typically around 0.2um, limited by the Full Well Capacitance (FWC), and the minimum pixel size is 0.7 um. If further pixel scaling is required, the FWC does not meet the specification unless the P-type implant size for isolation can be reduced. In the prior art, a method for manufacturing a small pixel (0.7um) CMOS image sensor is P-type ion isolation implantation + N-type ion isolation implantation. The specific method comprises the following steps: first, referring to fig. 1, a substrate 110 is provided, wherein the substrate 110 may be a wafer; next, forming an epitaxial layer 120 on the substrate 110, and dividing the surface of the epitaxial layer 120 into a first part epitaxial layer and a second part epitaxial layer; next, referring to fig. 2, a photoresist 130 is used to cover the first portion of the epitaxial layer, and P-type ions are implanted into the second portion of the epitaxial layer to form a P-type ion region; then, removing the photoresist; next, referring to fig. 3, the second portion of the epitaxial layer is covered by photoresist 140, and N-type ions are implanted into the first portion of the epitaxial layer to form N-type ion regions. Thereby completing the fabrication of the photodiode in the image sensor. And after the photodiode is manufactured, the other parts of the image sensor are continuously finished.
However, since the size of the image sensor is decreasing, the size of the photodiode is also decreasing, so that the CD of the P-type ion implantation is decreasing, and after the CD is decreased to a certain size, the aspect ratio of the P-type ion isolation implantation is higher, and the methods for solving the problem of the high aspect ratio in the prior art are divided into two methods: the first uses a dual mask (double exposure technique) to increase the pitch size, thereby increasing the width of the ion-implanted face, i.e., decreasing the ratio of depth to width; the second method is to reduce the size of the photoresist covering the first part of the epitaxial layer by using a novel shrink material after the photoresist covering the first part of the epitaxial layer is exposed, or sacrifice the performance of the full-well capacitor, the ghost, the white pixel and the like by using the CD (the deep P-type implantation CD is larger, and the shallow P-type implantation CD is smaller) for isolating the space of the deep P-type implantation, so that the width of the surface implanted with ions is increased, namely, the ratio of the depth to the width is reduced. However, in both methods, since the photoresist is thick, a problem of poor topography or poor uniformity of the photodiode may occur, which may cause a problem of a white pixel, a full well capacitance and/or a residual image (Lag) and may also restrict further reduction in the size of the photodiode.
Disclosure of Invention
The invention aims to provide a preparation method of a CMOS image sensor, which can avoid the problem of high depth-to-width ratio of P-type ion isolation implantation. Further, the occurrence of white pixels, full well capacitance and/or image sticking (Lag) can be reduced, and at the same time, advantages can be provided for further reduction in the size of the photodiode.
In order to achieve the above object, the present invention provides a method for manufacturing a CMOS image sensor, including:
providing a substrate;
forming a buried layer on the substrate;
growing a P-type epitaxial layer on the buried layer; and
and injecting N-type ions into part of the P-type epitaxial layer to form a photodiode of the CMOS image sensor.
Optionally, in the method for manufacturing a CMOS image sensor, the substrate includes a wafer.
Optionally, in the method for manufacturing a CMOS image sensor, the buried layer includes an oxide layer.
Optionally, in the method for manufacturing a CMOS image sensor, the buried layer is formed by depositing an oxide.
Optionally, in the method for manufacturing a CMOS image sensor, the method for implanting N-type ions into a part of the P-type epitaxial layer includes:
dividing the P-type epitaxial layer into a first part of P-type epitaxial layer and a second part of P-type epitaxial layer which are adjacent;
and implanting N-type ions into the first part of the P-type epitaxial layer.
Optionally, in the preparation method of the CMOS image sensor, the method for implanting N-type ions into the first portion of the P-type epitaxial layer includes:
covering the second part of the P-type epitaxial layer by using photoresist;
injecting N-type ions into the first part of the P-type epitaxial layer; and
and removing the photoresist.
Optionally, in the preparation method of the CMOS image sensor, the angle at which N-type ions are implanted into the first portion of P-type epitaxial layer is perpendicular to the first portion of P-type epitaxial layer.
Optionally, in the preparation method of the CMOS image sensor, the dose of implanted N-type ions is: 10 11 /cm 2 ～10 12 /cm 2 。
Optionally, in the preparation method of the CMOS image sensor, the N-type ions include: a phosphorus ion.
Optionally, in the method for manufacturing a CMOS image sensor, the buried layer has a thickness of 300 to 500 angstroms.
Optionally, in the preparation method of the CMOS image sensor, the thickness of the P-type epitaxial layer is 700 to 900 angstroms.
In the method for manufacturing a CMOS image sensor provided by the present invention, the method for manufacturing a CMOS image sensor includes: providing a substrate; forming a buried layer on the substrate; growing a P-type epitaxial layer on the buried layer; and injecting N-type ions into part of the P-type epitaxial layer to form a photodiode of the CMOS image sensor. Compared with the prior art, the invention can not cause the problem of higher depth-to-width ratio of P-type ion isolation implantation. Further, the occurrence of white pixels, full well capacitance and/or image sticking (Lag) is reduced, while providing advantages for further reduction of the photodiode size.
Drawings
Fig. 1 to 3 are schematic views illustrating a method for manufacturing a CMOS image sensor according to the related art;
fig. 4 is a flowchart of a method of fabricating a CMOS image sensor according to an embodiment of the present invention;
fig. 5 to 7 are schematic views illustrating a method of fabricating a CMOS image sensor according to an embodiment of the present invention;
in the figure: 110-substrate, 120-epitaxial layer, 130-photoresist, 140-photoresist, 210-substrate, 220-buried layer, 230-P type epitaxial layer, 240-photoresist.
Detailed Description
The following describes in more detail embodiments of the present invention with reference to the schematic drawings. The advantages and features of the present invention will become more apparent from the following description. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.
In the following, the terms "first," "second," and the like are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the terms so used are interchangeable under appropriate circumstances. Similarly, if the method described herein comprises a series of steps, the order in which these steps are presented herein is not necessarily the only order in which these steps may be performed, and some of the described steps may be omitted and/or some other steps not described herein may be added to the method.
As the size of the image sensor is reduced, the size of the photodiode is also reduced, so that the CD of the P-type ion implantation is reduced, and after the CD is reduced to a certain size, the aspect ratio of the P-type ion isolation implantation is higher, and the methods for solving the problem of the higher aspect ratio in the prior art are divided into two methods: the first uses a dual mask (double exposure technique) to increase the pitch size, thereby increasing the width of the ion-implanted face, i.e., decreasing the ratio of depth to width; the second method is to reduce the size of the photoresist covering the first part of the epitaxial layer by using a novel shrink material after the photoresist covering the first part of the epitaxial layer is exposed, or sacrifice the performance of the full-well capacitor, the ghost, the white pixel and the like by using the CD (the deep P-type implantation CD is larger, and the shallow P-type implantation CD is smaller) for isolating the space of the deep P-type implantation, so that the width of the surface implanted with ions is increased, namely, the ratio of the depth to the width is reduced. However, in both methods, since the photoresist is thick, a problem of poor topography or poor uniformity of the photodiode may occur, which may cause a problem of a white pixel, a full well capacitance and/or a residual image (Lag) and may also restrict further reduction in the size of the photodiode. Therefore, there is a need for a method of fabricating a CMOS image sensor that does not require consideration of the aspect ratio of the implanted P-type ions or a method of fabricating a CMOS image sensor that does not require implantation of P-type ions.
Referring to fig. 4, the present invention provides a method for manufacturing a CMOS image sensor, including:
s11: providing a substrate;
s12: forming a buried layer on the substrate;
s13: growing a P-type epitaxial layer on the buried layer; and
s14: and injecting N-type ions into part of the P-type epitaxial layer to form a photodiode of the CMOS image sensor.
Referring to fig. 5, a substrate 210 is provided, where the substrate 210 may be a silicon substrate or a germanium substrate, where the silicon substrate may be a single crystal silicon substrate or a polycrystalline silicon substrate, and in an embodiment of the present invention, the substrate 210 may be a wafer.
Next, with reference to fig. 5, a buried layer 220 is formed on the substrate 210, wherein the buried layer 220 has a thickness of 300 to 500 angstroms, such as 400 angstroms, and the buried layer 220 may have other thicknesses in other embodiments of the present invention. In an embodiment of the present invention, the buried layer includes an oxide layer, that is, the material of the buried layer is an oxide layer, where the oxide may be silicon dioxide, and may be other oxides elsewhere. In the embodiment of the present invention, the buried layer is formed by depositing an oxide, the deposition method may be a chemical vapor deposition method, and the chemical vapor deposition method is the prior art and will not be described herein.
Next, referring to fig. 6, a P-type epitaxial layer 230 is formed on the buried layer 220 by growing, wherein the thickness of the P-type epitaxial layer 230 is 700 a to 900 a, for example, 800 a, and in other embodiments of the present invention, the P-type epitaxial layer 230 may have other thicknesses. As the name implies, the P-type epitaxial layer is an epitaxial layer containing P-type ions, the concentration of the P-type ions in the P-type epitaxial layer can be freely controlled during the growth process, and meanwhile, the size, such as the thickness, the length and the width, of the P-type epitaxial layer can be freely controlled by means of the growth process. In the prior art, a P-type ion region is obtained in an epitaxial layer by implanting P-type ions, and the implantation of the ions is limited by the size of the epitaxial layer, otherwise, the problem of high aspect ratio is easily caused during the ion implantation. Furthermore, to solve the problem of high aspect ratio, a series of measures are taken, which in turn cause the CIS to generate a series of quality problems, such as white pixels, full well capacitance and/or image sticking (Lag). The embodiment of the invention is not limited by the size of the P-type epitaxial layer 230 by growing the P-type epitaxial layer 230. And a P-type ion region is not obtained in the epitaxial layer by implanting P-type ions into the epitaxial layer, and the problem of high aspect ratio during ion implantation is not considered, so that the CIS does not have a series of quality problems in order to solve the problem of the aspect ratio.
Next, referring to fig. 7, N-type ions are implanted into a portion of the P-type epitaxial layer 230, in an embodiment of the present invention, a specific method for implanting N-type ions into a portion of the P-type epitaxial layer may be: dividing the P-type epitaxial layer 230 into a first part P-type epitaxial layer and a second part P-type epitaxial layer which are adjacent; and implanting N-type ions into the first part of the P-type epitaxial layer. Specifically, the method for implanting N-type ions into the first part of P-type epitaxial layer includes: masking the second portion of the P-type epitaxial layer with photoresist 240; injecting N-type ions into the first part of the P-type epitaxial layer; and removing the photoresist. The angle of implanting N-type ions into the first portion of P-type epitaxial layer is perpendicular to the first portion of P-type epitaxial layer, and the dose of implanting N-type ions may be: 10 11 /cm 2 ～10 12 /cm 2 The implanted N-type ions may be: phosphorus ions, in other embodiments of the present invention, the dose of implanted N-type ions and the type of implanted N-type ions may be determined according to the requirements of a specific CMOS image sensor, the dose of implanted N-type ions of embodiments of the present invention and the CMOS image of the prior artThe sensor is implanted with the same dose of N-type ions.
In summary, in the method for manufacturing a CMOS image sensor provided in the embodiments of the present invention, the method for manufacturing a CMOS image sensor includes: providing a substrate; forming a buried layer on the substrate; growing a P-type epitaxial layer on the buried layer; and injecting N-type ions into part of the P-type epitaxial layer to form a photodiode of the CMOS image sensor. Compared with the prior art, the embodiment of the invention does not have the problem of high depth-to-width ratio of P-type ion isolation implantation. Further, the occurrence of white pixels, full well capacitance and/or image sticking (Lag) is reduced, while providing advantages for further reduction of the photodiode size.
The above description is only a preferred embodiment of the present invention, and does not limit the present invention in any way. It will be understood by those skilled in the art that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the invention as defined by the appended claims.
Claims (11)
1. A method for fabricating a CMOS image sensor, comprising:
providing a substrate;
forming a buried layer on the substrate;
growing a P-type epitaxial layer on the buried layer; and
and injecting N-type ions into part of the P-type epitaxial layer to form a photodiode of the CMOS image sensor.
2. The method of fabricating a CMOS image sensor as in claim 1, wherein the substrate comprises a wafer.
3. The method of fabricating a CMOS image sensor according to claim 1, wherein the buried layer comprises an oxide layer.
4. The method of fabricating a CMOS image sensor according to claim 3, wherein the buried layer is formed by depositing an oxide form.
5. The method for manufacturing a CMOS image sensor according to claim 1, wherein the method for implanting N-type ions into a portion of the P-type epitaxial layer comprises:
dividing the P-type epitaxial layer into a first part of P-type epitaxial layer and a second part of P-type epitaxial layer which are adjacent;
and implanting N-type ions into the first part of the P-type epitaxial layer.
6. The method for manufacturing the CMOS image sensor according to claim 5, wherein the method for implanting N-type ions into the first portion of the P-type epitaxial layer comprises:
covering the second part of the P-type epitaxial layer by using photoresist;
injecting N-type ions into the first part of the P-type epitaxial layer; and
and removing the photoresist.
7. The method according to claim 6, wherein an angle of implanting N-type ions into the first portion of P-type epitaxial layer is perpendicular to the first portion of P-type epitaxial layer.
8. The method of manufacturing a CMOS image sensor according to claim 7, wherein a dose of the implanted N-type ions is: 10 11 /cm 2 ～10 12 /cm 2 。
9. The method of manufacturing a CMOS image sensor according to claim 7, wherein the N-type ions include: a phosphorus ion.
10. The method of fabricating the CMOS image sensor according to claim 1, wherein the buried layer has a thickness of 300 to 500 angstroms.
11. The method of claim 1, wherein the P-type epitaxial layer has a thickness of 700 to 900 angstroms.
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| CN202210745538.XA CN115084177A (en) | 2022-06-27 | 2022-06-27 | Preparation method of CMOS image sensor |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114220886A (en) * | 2021-12-14 | 2022-03-22 | 中国电子科技集团公司第四十四研究所 | Pull-through type silicon APD array and pixel inter-spacing method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN114220886A (en) * | 2021-12-14 | 2022-03-22 | 中国电子科技集团公司第四十四研究所 | Pull-through type silicon APD array and pixel inter-spacing method thereof |
| CN114220886B (en) * | 2021-12-14 | 2023-11-24 | 中国电子科技集团公司第四十四研究所 | Pull-through silicon APD array and pixel interval separation method thereof |
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