CN115084098B - Test structure and test method - Google Patents
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- CN115084098B CN115084098B CN202210850740.9A CN202210850740A CN115084098B CN 115084098 B CN115084098 B CN 115084098B CN 202210850740 A CN202210850740 A CN 202210850740A CN 115084098 B CN115084098 B CN 115084098B
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- 238000012360 testing method Methods 0.000 title claims abstract description 209
- 238000010998 test method Methods 0.000 title claims abstract description 10
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 92
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 92
- 239000002184 metal Substances 0.000 claims abstract description 91
- 229910052751 metal Inorganic materials 0.000 claims abstract description 91
- 238000000034 method Methods 0.000 claims abstract description 30
- 230000005856 abnormality Effects 0.000 claims abstract description 24
- 230000002159 abnormal effect Effects 0.000 claims abstract description 19
- 239000000758 substrate Substances 0.000 claims description 20
- 239000002019 doping agent Substances 0.000 claims 2
- 239000004065 semiconductor Substances 0.000 abstract description 5
- 230000035945 sensitivity Effects 0.000 abstract description 4
- 239000010410 layer Substances 0.000 description 60
- 238000001514 detection method Methods 0.000 description 9
- 238000010586 diagram Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000010894 electron beam technology Methods 0.000 description 3
- 238000000137 annealing Methods 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 238000007689 inspection Methods 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000011165 process development Methods 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000010941 cobalt Substances 0.000 description 1
- 229910017052 cobalt Inorganic materials 0.000 description 1
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 1
- 239000013256 coordination polymer Substances 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910021334 nickel silicide Inorganic materials 0.000 description 1
- RUFLMLWJRZAWLJ-UHFFFAOYSA-N nickel silicide Chemical compound [Ni]=[Si]=[Ni] RUFLMLWJRZAWLJ-UHFFFAOYSA-N 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 238000005070 sampling Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 239000002344 surface layer Substances 0.000 description 1
- 229910021341 titanium silicide Inorganic materials 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 238000012795 verification Methods 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
- H01L22/34—Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/10—Measuring as part of the manufacturing process
Abstract
The invention provides a test structure and a test method, which relate to the technical field of semiconductors and are used for detecting whether metal silicide is abnormal or not, wherein the test structure comprises a plurality of test transistors and an interconnection structure; each test transistor is provided with an independent input end, and the output ends of the plurality of test transistors are connected in parallel; each test transistor comprises an active region, a source terminal, a drain terminal and at least two grid electrode structures, wherein the at least two grid electrode structures are positioned on the active region between the source terminal and the drain terminal, and metal silicide layers are respectively arranged in the source terminal and the drain terminal. In the invention, the test transistor is provided with at least two grid structures, and then a plurality of test transistors are arranged in parallel to form the test structure, so that whether the metal silicide layer is abnormal or not is detected through electrical property test in the interconnection process by utilizing the sensitivity of the metal silicide of the transistor with at least two grid structures to related processes, thereby achieving the purpose of quickly, accurately and timely detecting the abnormality of the metal silicide layer.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a test structure and a test method.
Background
At present, in a semiconductor manufacturing process, an etching process is used to form contact holes (CT) in an interlayer dielectric layer (ILD), and then conductive metal materials such as tungsten (W) are deposited in the contact holes for electrical connection between semiconductor devices, which is a widely used process. In order to reduce the hole resistance of the contact hole structure and the contact resistance of the contact hole structure electrically connected to the gate and source/drain of the device, a layer of metal silicide (silicide) is usually formed on the surface of the gate and source/drain where the contact hole is to be formed by metal deposition and rapid annealing.
If the metal silicide is abnormal, it is generally difficult to perform defect scan (defect scan) to detect the presence or absence of the metal silicide abnormality in the silicon substrate because the metal silicide abnormality is usually present in the region below the metal silicide. The existing electron beam detection (ebeam scan) method is used for detecting the metal silicide abnormity in the middle-stage (or rear-stage) process of the interconnection structure, so that the scanning speed is low (only few parts of products can be subjected to sampling inspection), and the detection accuracy of the electron beam detection on the metal silicide is relatively low. On the other hand, if the metal silicide abnormality is not detected in the electron beam detection, the metal silicide abnormality can be detected only by the CP test or the FT test, and the yield is seriously influenced.
Disclosure of Invention
The invention aims to provide a test structure and a test method so as to achieve the aim of quickly, accurately and timely detecting the abnormality of metal silicide.
In order to solve the above technical problem, the present invention provides a test structure, disposed on a substrate, for detecting whether an abnormality exists in a metal silicide layer, where the test structure includes a plurality of test transistors and an interconnection structure; each test transistor has an independent input end, and the output ends of the plurality of test transistors are connected in parallel; each test transistor comprises an active region, a source terminal, a drain terminal and at least two grid structures, wherein the source terminal and the drain terminal are positioned in the active region, the at least two grid structures are positioned on the active region between the source terminal and the drain terminal, and the source terminal and the drain terminal are respectively provided with the metal silicide layer; the interconnection structure is positioned on the metal silicide layer and is electrically connected with the source end and the drain end to be used as an input end and an output end of the test transistor.
Optionally, the substrate includes a test region and a device region, the test structure is formed on the test region of the substrate, a device transistor is formed on the device region, and the device transistor and the test transistor have the same transistor size and doping concentration.
Optionally, a connection end is formed in an active region between the gate structures, the metal silicide layer is formed in the connection end, the source end, the drain end, and the connection end each include an LDD region and a heavily doped region, and the metal silicide layer is formed in the heavily doped region.
Optionally, the interconnection structure includes a contact plug and a first layer of interconnection lines located on the contact plug, the first layer of interconnection lines includes a gate interconnection line, a body terminal interconnection line, an output interconnection line and a plurality of input interconnection lines, the gate interconnection line is electrically connected to the gate structures of the plurality of test transistors, the output interconnection line is electrically connected to the output terminals of the plurality of test transistors, each input interconnection line is electrically connected to the input terminal of each test transistor, and the body terminal interconnection line is electrically connected to the body terminals of the plurality of test transistors.
According to another aspect of the present invention, there is also provided a test method, including: providing a test structure formed on a substrate, the test structure comprising a plurality of test transistors and an interconnect structure; each test transistor has an independent input end, and the output ends of the plurality of test transistors are connected in parallel; each test transistor comprises an active region, a source terminal, a drain terminal and at least two grid structures, wherein the source terminal and the drain terminal are positioned in the active region, the at least two grid structures are positioned on the active region between the source terminal and the drain terminal, and metal silicide layers are respectively arranged in the source terminal and the drain terminal; the interconnection structure is positioned on the metal silicide layer and is electrically connected with the source end and the drain end to be used as an input end and an output end of the test transistor; applying a test voltage to the input terminals of the plurality of test transistors to obtain a first leakage current when the test structure is in an off state; comparing whether the first leakage current is larger than a first set current or not to judge whether the metal silicide layer is abnormal or not; if the metal silicide layer is abnormal, applying the test voltage to each test transistor to obtain a corresponding second leakage current when the test transistors are in a turn-off state, and comparing whether the second leakage current is larger than a second set current to judge whether the metal silicide layer of the test transistors is abnormal or not, wherein the second set current is smaller than or equal to the first set current.
Optionally, the substrate includes a test region and a device region, the test structure is formed on the test region of the substrate, a device transistor is formed on the device region, and the device transistor and the test transistor have the same transistor size and doping concentration.
Optionally, the test transistor is an NMOS transistor, a drain of the NMOS transistor is used as an input terminal, a source of the NMOS transistor is used as an output terminal, and a gate structure and a body terminal of the test transistor are both connected to 0 v voltage, so that the test transistor is in an off state.
Optionally, the test voltage is 1.05 times of a standard driving voltage of the device transistor, the second setting current is 50 times of a standard off-state current of the device transistor, and the first setting current is obtained by multiplying the second setting current by the number of test transistors in the test structure.
Optionally, the interconnection structure includes a contact plug and a first layer of interconnection line located on the contact plug, and after the first layer of interconnection line is formed, whether the metal silicide layer is abnormal is detected.
In summary, the test structure and the test method provided by the present invention use a transistor with at least two gate structures as a test transistor, and use an interconnection structure to connect output terminals of a plurality of test transistors in parallel and independently set input terminals of the plurality of test transistors to form a test structure, so as to improve the accuracy of detecting the abnormality of a metal silicide layer by using the sensitivity of the metal silicide of the transistors with at least two gate structures to the related processes.
Drawings
It will be appreciated by those skilled in the art that the drawings are provided for a better understanding of the invention and do not constitute any limitation to the scope of the invention.
FIG. 1 is a schematic diagram of a test structure according to a first embodiment;
FIG. 2 is a diagram illustrating a test transistor according to an embodiment;
fig. 3 is a flowchart of a testing method according to the second embodiment.
In the drawings: 10-an active region; 11-drain terminal; 12-a source end; 13-a connection end; 14-body end; 15-LDD region; 16-heavily doped region; 17-a metal silicide layer; 21-a gate structure; 22-side wall structure; 23-an interconnect structure; 23 a-contact plug; 23 b-a first layer of interconnect lines; 231-input interconnect; 232-gate interconnect lines; 233-output interconnection lines; 234-body end interconnect; d1-a first direction; d2-second direction.
Detailed Description
The inventors have found that, in the manufacturing process of a transistor having two gate structures, the yield of the metal silicide layer of the transistor is lower than that of a metal silicide layer of a single gate structure with similar size under the same or similar process conditions, i.e., the metal silicide layer of the transistor having two gate structures is more sensitive to the process related to the metal silicide layer.
In summary, the present invention provides a test structure and a test method, wherein a transistor having at least two gate structures is used as a test transistor, and an interconnection structure is used to connect output terminals of a plurality of test transistors in parallel and independently set input terminals of the plurality of test transistors to form the test structure, so as to improve the accuracy of detecting the abnormality of the metal silicide layer by using the sensitivity of the metal silicide of the transistors having at least two gate structures to the related processes.
To further clarify the objects, advantages and features of the present invention, a more particular description of the invention will be rendered by reference to specific embodiments thereof which are illustrated in the appended drawings. It is to be noted that the drawings are in greatly simplified form and are not to scale, but are merely intended to facilitate and clarify the explanation of the embodiments of the present invention. Further, the structures illustrated in the drawings are often part of actual structures. In particular, the drawings may have different emphasis points and may sometimes be scaled differently.
As used in this disclosure, the singular forms "a," "an," and "the" include plural referents, the term "or" is generally employed in a sense including "and/or," the terms "a," "an," and "the" are generally employed in a sense including "at least one," the terms "at least two" are generally employed in a sense including "two or more," and further, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or to imply that the number of indicated technical features is essential. Thus, a feature defined as "first," "second," or "third" may explicitly or implicitly include one or at least two of the feature unless the content clearly dictates otherwise.
Example one
Fig. 1 is a schematic diagram of a test structure according to a first embodiment.
As shown in fig. 1, the test structure provided in this embodiment for detecting whether there is an abnormality in a metal silicide layer includes a plurality of test transistors and an interconnection structure 23, where each test transistor has an independent input terminal, and output terminals of the plurality of test transistors are connected in parallel. Each test transistor comprises an active region 10, a source terminal, a drain terminal and at least two gate structures 21. The active region 10 is provided on the substrate; the drain terminal 11 and the source terminal 12 are formed in the active region 10, and a metal silicide layer 17 is arranged in each of the drain terminal 11 and the source terminal 12; at least two gate structures 21 are arranged between the drain terminal 11 and the source terminal 12; the interconnect structure 23 is located on the metal silicide layer 17, and the interconnect structures 23 on the drain terminal 11 and the source terminal 12 are used as the input terminal and the output terminal of the test transistor.
The substrate comprises a test area and a device area, wherein the device area is provided with a device transistor which is formed synchronously with the test transistor, and whether the device transistor is abnormal with a metal silicide layer is judged by detecting whether the test transistor is abnormal with the metal silicide layer, namely whether the process related to the metal silicide layer is abnormal is judged. Preferably, the test transistor has the same transistor dimensions and doping concentration (including device type, e.g., NMOS or PMOS) as the device transistor, so that the electrical parameters of the two are as identical as possible, thereby facilitating the detection of the metal silicide abnormality. The transistor size includes the length and width of the channel of the transistor, the length and width of the source and drain regions, and the like. It should be noted that the gate structure of the device transistor may have a similar structure to that of the test transistor, but the number of the gate structures of the device transistor and the test transistor may be different (the width of the gate structures of the device transistor and the test transistor is different), for example, the device transistor has one gate structure, but the test transistor is provided with at least two gate structures on the same channel width, and the at least two gate structures are arranged in parallel and spaced apart from each other on the channel (the active region between the source terminal and the drain terminal).
Specifically, referring to fig. 2, the test transistor is formed on an active region 10 of the test region, a drain terminal 11 and a source terminal 12 are formed in a surface of the active region 10, and the drain terminal 11 and the source terminal 12 have a conductivity type opposite to that of the active region 10 to form electrical isolation. The two gate structures 21 are located on the active region 10 and are arranged in parallel (spaced) between the source terminal 12 and the drain terminal 11, and a connection terminal 13 formed in synchronization with the drain terminal 11 and the source terminal 12 is formed in the active region 10 between the two gate structures 21. The source terminal 12, the drain terminal 11 and the connection terminal 13 respectively include an LDD region 15 and a heavily doped region 16 which are formed synchronously, the heavily doped region 16 is located on a surface layer of the LDD region 15, a doping type of the LDD region 15 is the same as a doping type of the heavily doped region 16, a doping type concentration of the LDD region 15 is less than a doping concentration of the heavily doped region 16, and a portion of the LDD region 15 can extend below the gate structure 21 by utilizing oblique ion implantation to reduce or prevent a short channel effect.
Referring to fig. 2, a metal silicide layer 17 is formed in the heavily doped regions 16 of the source terminal 12, the drain terminal 11 and the connection terminal 13, and the contact resistance is reduced by using the metal silicide layer 17, wherein the material of the metal silicide layer 17 may be, for example, one or at least two of titanium silicide, cobalt silicide or nickel silicide. The drain terminal 11, the source terminal 12 and the gate structure 21 are provided with an interconnection structure 23, the interconnection structure 23 includes a contact plug and an interconnection line, and each terminal of the test transistor is electrically led out by using the interconnection structure 23, for example, the drain terminal is led out as an input terminal, the source terminal is led out as an output terminal, and the gate structure 21 is led out as a control terminal. Preferably, the interconnection structure 23 includes the contact plug 23a and the first-layer interconnection line 23b, so that the metal silicide layer 17 can be inspected by using the test structure after the first-layer interconnection line 23b is formed, thereby improving the timeliness of the inspection.
It will be understood that if an abnormality occurs in the metal silicide layer 17 in the source terminal 12, the drain terminal 11 or the connection terminal 13, for example, the metal silicide layer 17 abnormally grows through the LDD region 15 and communicates with the active region 10, leakage will be directly caused. As mentioned above, the test transistor with two gate structures 21 has a smaller size and a larger number of metal silicide layers 17 than the test transistor with only one gate structure for the same transistor size (e.g. channel width), thereby making the test transistor more sensitive to the process related to the metal silicide layers 17, i.e. easier to detect the metal silicide layer 17 anomalies. The processes related to the metal silicide layer 17 may include, for example, an LDD process for forming the LDD region 15, a heavy ion implantation process for forming the heavily doped region 16, a metal silicide forming process (including a metal sputtering process, an annealing process, and a wet etching process), and the like. Taking the LDD process and the metal silicide forming process as an example, the LDD region 15 (connection terminal 13) between the two gate structures 21 is affected by the loading effect (loading effect) of the gate structures 21 protruding from both sides, and the metal silicide layer 17 between the gate structures 21 is more likely to have abnormal growth (especially expanding in the lateral or oblique direction). Of course, it is also feasible if three or more gate structures are arranged between the drain terminal and the source terminal of the test transistor, and the test transistor can simultaneously satisfy other process conditions, such as formation process conditions of the sidewall structure, the drain terminal or the source terminal, and the like.
Specifically, for example, the testing transistor is an NMOS transistor, the source terminal 12, the drain terminal 11, and the connection terminal 13 may include an N-type LDD region 15, and an N-type heavily doped region 16 located on a surface of the LDD region 15. The gate structures 21 may each include a gate dielectric layer and a gate conductive layer on the gate dielectric layer, the gate conductive layer may be made of, for example, polysilicon, and a sidewall structure 22 is disposed on a sidewall of the gate structure 21. The active region 10 is further provided with a body end 14, the body end 14 is located on one side of the source end 12 far away from the gate structure 21, the body end 14 can be a P-type heavily doped region 16, and a metal silicide layer 17 is formed on the heavily doped region 16 and the gate structure 21 to reduce contact resistance when the metal silicide layer is electrically led out.
With reference to fig. 1, the active regions 10 of at least thirty test transistors are preferably arranged in order along the second direction D2 of the substrate and extend along the first direction D1, so that the gate structures 21, the output terminals and the body terminals 14 of all the test transistors are all electrically led out together by using the interconnection lines extending along the second direction D2, thereby optimizing the layout for facilitating the electrical test. Wherein, the first direction D1 may be orthogonal to the second direction D2. The test transistor in this embodiment is an NMOS transistor having two gates, the drain 11 of the NMOS transistor may be an input terminal of the test transistor, the source 12 of the NMOS transistor may be an output terminal of the test transistor, the first layer of interconnect 23b includes a gate interconnect 232, a body terminal interconnect 234, an output interconnect 233, and at least thirty input interconnects 231, the gate interconnect 232 is electrically connected to the gate structures 21 of at least thirty test transistors, the output interconnect 233 is electrically connected to the output terminals of at least thirty test transistors, the body terminal interconnect 234 is electrically connected to the body terminals 14 of at least thirty test transistors, and at least thirty input interconnects 231 are electrically connected to the input terminals of at least thirty test transistors, that is, each test transistor has an independent input.
In other embodiments, the number of the test transistors in the test structure may also be specifically set according to the available area of the test area, and the number of the test transistors in the test structure may be preferably greater than or equal to thirty, so as to improve the detection probability of the metal silicide abnormality by a larger number of test transistors. In particular, the test structure of the present embodiment is also applicable to a semiconductor device in a process development (process verification) stage to detect whether an abnormality exists in the metal silicide, so as to fully utilize a relatively sufficient area on the substrate in the process development stage to realize timely and accurate detection of the abnormality in the metal silicide.
Example two
Fig. 3 is a flowchart of a testing method according to the second embodiment.
As shown in fig. 3, the testing method provided in this embodiment includes:
s01: providing a test structure formed on a substrate, the test structure comprising a plurality of test transistors and an interconnect structure; each test transistor has an independent input end, and the output ends of the plurality of test transistors are connected in parallel; each test transistor comprises an active region, a source terminal, a drain terminal and at least two grid structures, wherein the source terminal and the drain terminal are positioned in the active region, the at least two grid structures are positioned on the active region between the source terminal and the drain terminal, and metal silicide layers are respectively arranged in the source terminal and the drain terminal; the interconnection structure is positioned on the metal silicide layer and electrically connected with the source end and the drain end to serve as an input end and an output end of the test transistor;
s02: applying a test voltage to the input terminals of the plurality of test transistors to obtain a first leakage current when the test structure is in an off state;
s03: comparing whether the first leakage current is larger than a first set current or not to judge whether the metal silicide layer is abnormal or not; if the metal silicide layer is abnormal, applying the test voltage to each test transistor to obtain a corresponding second leakage current when the test transistors are in a turn-off state, and comparing whether the second leakage current is larger than a second set current to judge whether the metal silicide layer of the test transistors is abnormal or not, wherein the second set current is smaller than or equal to the first set current.
In step S01, the substrate includes a test region and a device region, a device transistor is formed on the device region, and the test transistor on the test region and the device transistor in the device region are formed simultaneously. In addition, the device transistor and the test transistor have the same transistor size and doping concentration, so that the device transistor and the test transistor have the same electrical parameters as much as possible, and the detection accuracy is improved. Preferably, the interconnection line of the interconnection structure of the test transistor may be a first layer interconnection line, so that the abnormality of the metal silicide layer can be detected after the first layer interconnection line is formed, thereby improving the timeliness of the detection. For the specific features of the test structure, reference may be made to the contents of the first embodiment, which will not be described herein.
In step S02, taking the testing transistors as NMOS transistors as an example, the gate structures (gate interconnection lines) of all the testing transistors may be connected to 0 v, and the body terminals (body terminal interconnection lines) of all the testing transistors may be connected to 0 v, so that the testing structures (all the testing transistors) are in an off state (off state), and then the testing voltages are synchronously applied to the input terminals (drain terminals, input interconnection lines) of all the testing transistors, so as to obtain the first leakage currents from the output terminals (source terminals, ground, output interconnection lines) of all the testing transistors. It will be appreciated that the measured first leakage current is the sum of the leakage currents in the off-state of all the test transistors.
In step S03, whether the off-state leakage current exceeds the standard is determined by comparing whether the first leakage current is greater than the first set current, and whether the process related to the metal silicide is normal is determined, and whether the metal silicide is abnormal is determined according to the determined result. That is, if the first leakage current is less than or equal to the first set current, the metal silicide is determined to be normal, and if the first leakage current is greater than the first set current, the metal silicide in the test transistor is determined to be abnormal. When the metal silicide abnormality is judged to exist, a test voltage is applied to each test transistor respectively to obtain a second leakage current of each test transistor, the second leakage current is compared with a second set current to judge whether the test transistor has the metal silicide abnormality or not, and the test transistor with the metal silicide abnormality is found out until the test transistor with the metal silicide abnormality is found out, so that the subsequent further electrical analysis and physical analysis are carried out on the test transistor with the metal silicide abnormality. Of course, in practice, it may be determined whether the leakage current caused by the metal silicide abnormality exceeds the standard by combining other technical means, for example, by detecting the micro short (light short) between the interconnection structures to eliminate the leakage current caused by the short.
Specifically, taking the test transistor as an NMOS transistor as an example, the test voltage may be 1.05 times of the standard driving voltage of the test transistor (device transistor), and the second set current is the standard off-state current (I) of the device transistor off ) The first set current may be the second set current multiplied by the number of test transistors in the test structure by a factor of 50. In a preferred embodiment, the test voltage may be 1.1 times the standard driving voltage of the test transistor, and the second set current is the standard off-state current (I) of the device transistor off ) 100 times higher, the standard off-state current may be, for example, 10 -12 In amperes. It should be understood that the standard off-state current of the test transistor is relatively close (in the same order of magnitude) to the standard off-state current of the device transistor for the same transistor size and doping concentration of the test transistor and the device transistor, e.g., the standard off-state current may be 10 -11 Ampere-10 -12 In amperes.
The invention provides a test structure and a test method, wherein a transistor with at least two grid structures is used as a test transistor, an interconnection structure is used for connecting output ends of a plurality of test transistors in parallel and independently arranging input ends of the test transistors to form the test structure, so that the sensitivity of metal silicide of the transistor with at least two grid structures to related processes is utilized, and the accuracy of detecting the abnormity of a metal silicide layer is improved.
The above description is only for the purpose of describing the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention, and any variations and modifications made by those skilled in the art based on the above disclosure are within the scope of the appended claims.
Claims (9)
1. A test structure is arranged on a substrate and used for detecting whether an abnormality exists in a metal silicide layer, and is characterized in that the test structure comprises a plurality of test transistors and an interconnection structure; each test transistor has an independent input end, and the output ends of the plurality of test transistors are connected in parallel; each test transistor comprises an active region, a source terminal, a drain terminal and at least two grid structures, wherein the source terminal and the drain terminal are positioned in the active region, the at least two grid structures are positioned on the active region between the source terminal and the drain terminal, and the source terminal and the drain terminal are respectively provided with the metal silicide layer; the interconnection structure is positioned on the metal silicide layer and electrically connected with the source end and the drain end to serve as an input end and an output end of the test transistor;
the source end, the drain end and the connecting end respectively comprise an LDD (lightly doped drain) region and a heavily doped region, and the metal silicide layer is formed in the heavily doped region.
2. The test structure of claim 1, wherein the substrate comprises a test region and a device region, the test structure being formed on the test region of the substrate, the device region having a device transistor formed thereon, the device transistor having a same transistor size and dopant concentration as the test transistor.
3. The test structure of claim 1, wherein the interconnect structure includes a contact plug and a first layer of interconnect lines on the contact plug, the first layer of interconnect lines including a gate interconnect line electrically connecting the gate structures of the plurality of test transistors, a body terminal interconnect line electrically connecting the input terminals of each of the plurality of test transistors, an output interconnect line electrically connecting the gate structures of the plurality of test transistors, and a plurality of input interconnect lines electrically connecting the body terminals of the plurality of test transistors.
4. The test structure of any of claims 1-3, wherein the test transistors are NMOS transistors, the test structure having at least thirty of the NMOS transistors with active regions of at least thirty of the NMOS transistors extending in a first direction and uniformly arranged in a second direction on the substrate, the first direction orthogonal to the second direction.
5. A method of testing, comprising:
providing a test structure formed on a substrate, the test structure comprising a plurality of test transistors and an interconnect structure; each test transistor has an independent input end, and the output ends of the plurality of test transistors are connected in parallel; each test transistor comprises an active region, a source terminal, a drain terminal and at least two grid structures, wherein the source terminal and the drain terminal are positioned in the active region, the at least two grid structures are positioned on the active region between the source terminal and the drain terminal, and metal silicide layers are respectively arranged in the source terminal and the drain terminal; the interconnection structure is positioned on the metal silicide layer and electrically connected with the source end and the drain end to serve as an input end and an output end of the test transistor, wherein a connecting end is formed in an active area between the grid structures, the metal silicide layer is formed in the connecting end, the source end, the drain end and the connecting end respectively comprise an LDD (lightly doped drain) area and a heavily doped area, and the metal silicide layer is formed in the heavily doped area;
applying a test voltage to the input terminals of the plurality of test transistors to obtain a first leakage current when the test structure is in an off state;
comparing whether the first leakage current is larger than a first set current or not to judge whether the metal silicide layer is abnormal or not;
if the metal silicide layer is abnormal, applying the test voltage to each test transistor to obtain a corresponding second leakage current when the test transistors are in a turn-off state, and comparing whether the second leakage current is larger than a second set current to judge whether the metal silicide layer of the test transistors is abnormal or not, wherein the second set current is smaller than or equal to the first set current.
6. The method of claim 5, wherein the substrate comprises a test region and a device region, the test structure is formed on the test region of the substrate, and the device region has a device transistor formed thereon, the device transistor having a same transistor size and dopant concentration as the test transistor.
7. The method of claim 6, wherein the test transistor is an NMOS transistor having its drain terminal as an input terminal and its source terminal as an output terminal, and wherein the gate structure and the body terminal of the test transistor are both tied to 0 volts to turn the test transistor off.
8. The method of claim 7, wherein the test voltage is 1.05 times a standard drive voltage of the device transistor, the second set current is 50 times a standard off-state current of the device transistor, and the first set current is the second set current multiplied by a number of test transistors in the test structure.
9. The method according to claim 5, wherein the interconnect structure includes a contact plug and a first layer of interconnect lines on the contact plug, and wherein after the first layer of interconnect lines is formed, whether an abnormality exists in the metal silicide layer is detected.
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| CN1727872A (en) * | 2004-07-29 | 2006-02-01 | 上海华虹Nec电子有限公司 | Method of using ion beam to analyze defective workmanship of metal silicides |
| KR100821836B1 (en) * | 2006-12-05 | 2008-04-14 | 동부일렉트로닉스 주식회사 | Method for detecting bad formation of silicide |
| CN102569115A (en) * | 2010-12-23 | 2012-07-11 | 无锡华润上华半导体有限公司 | Detection method of semiconductor device defect |
| CN110176406A (en) * | 2019-06-12 | 2019-08-27 | 武汉新芯集成电路制造有限公司 | The defect inspection method of metal silicide and the forming method of semiconductor structure |
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| US7443189B2 (en) * | 2005-02-02 | 2008-10-28 | Texas Instruments Incorporated | Method to detect and predict metal silicide defects in a microelectronic device during the manufacture of an integrated circuit |
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| CN1727872A (en) * | 2004-07-29 | 2006-02-01 | 上海华虹Nec电子有限公司 | Method of using ion beam to analyze defective workmanship of metal silicides |
| KR100821836B1 (en) * | 2006-12-05 | 2008-04-14 | 동부일렉트로닉스 주식회사 | Method for detecting bad formation of silicide |
| CN102569115A (en) * | 2010-12-23 | 2012-07-11 | 无锡华润上华半导体有限公司 | Detection method of semiconductor device defect |
| CN110176406A (en) * | 2019-06-12 | 2019-08-27 | 武汉新芯集成电路制造有限公司 | The defect inspection method of metal silicide and the forming method of semiconductor structure |
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