CN115080478A

CN115080478A - Embedded platform display system

Info

Publication number: CN115080478A
Application number: CN202210648272.7A
Authority: CN
Inventors: 黄克亚
Original assignee: Suzhou University
Current assignee: Suzhou University
Priority date: 2022-06-09
Filing date: 2022-06-09
Publication date: 2022-09-20
Anticipated expiration: 2042-06-09
Also published as: CN115080478B

Abstract

The invention relates to an embedded platform display system, which comprises a microcontroller, a digital display, a TFT-LCD, an off-chip Flash memory, a CMSIS-DAP debugger, a PC and a national standard Chinese character font library, wherein the digital display and the TFT-LCD are respectively connected with the microcontroller through an FSMC bus; the microcontroller expands an off-chip Flash memory through an SPI interface and is connected with a PC through a CMSIS-DAP debugger; the PC sends the national standard Chinese character library to the microcontroller, and the microcontroller writes the Chinese character library into an off-chip Flash memory; when displaying Chinese characters, searching character module data in a character library buffer area of a main memory according to Chinese character internal codes, and successfully reading and displaying through IAP; and searching the unsuccessful access off-chip Flash memory to acquire the character module data, writing the character module data into a character library buffer area, and loading the character module data into a memory for display. The microcontroller has the advantages of high utilization rate of pin resources, integrity and high speed of Chinese display, transparent display platform, strong universality and good transportability.

Description

Embedded platform display system

Technical Field

The invention relates to the technical field of embedded system application, in particular to an embedded platform display system.

Background

The embedded system needs to be equipped with a display device to indicate the program running state and output the control result, and a Thin film transistor liquid crystal display (TFT-LCD) is the mainstream display device of the embedded system due to its advantages of low power consumption, small radiation, bright color, rich display content, and the like. However, TFT-LCDs are complex to control and require the use of underlying drivers provided by the vendor. The digital display has high brightness, stability, reliability and low price, is widely applied in the fields of household appliances, industrial control, sensing detection and the like, is provided with an embedded platform of two display devices, namely a TFT-LCD and a digital display, can integrate the advantages of the digital display and the TFT-LCD, and further enriches the application range of the embedded platform.

In the development process of an embedded platform simultaneously provided with two display devices, namely a TFT-LCD and a digital display, a parallel interface is usually used for connecting the digital display, the TFT-LCD and a Microcontroller (MCU) in order to improve the data transmission speed and reduce the design difficulty of software and hardware, but the parallel interface needs to occupy a large amount of I/O interface resources. Taking a 6-bit digital display as an example, there are 6 bit selection signals and 8 segment selection signals, and the TFT-LCD display module has 6 control signals and 16 bit data lines. When designing a system, for convenience of programming, it is generally desirable that the bit selection signal, the segment selection signal, and the LCD data line occupy continuous 16-bit ports, and these I/O pins are discretely distributed around the chip, occupying more pins, crossing too many wires, bringing difficulties to pin resource allocation and PCB wiring of the microcontroller, and reducing the reliability of the experimental apparatus.

Meanwhile, in the application process of the embedded platform, Chinese display is a common requirement, friendly interface can be realized, and the usability of the system is greatly improved. Two technical routes are provided for realizing Chinese character display, one method is to define character matrix data of Chinese characters as constant arrays and store the constant arrays in a main memory of a system, and the main memory is directly accessed during display, so that the speed is high, but only individual Chinese characters can be stored, manual mode extraction is needed, and the universality is poor; the other method is that all Chinese characters contain full-angle English characters, the character models are selected and then stored in an external memory, when the Chinese characters are displayed, the external memory is accessed to obtain character model data, and then the character model data are called into the internal memory to finish displaying.

Disclosure of Invention

Therefore, the technical problem to be solved by the present invention is to overcome the defects in the prior art, and provide an embedded platform display system, which can improve the utilization rate of pin resources, give consideration to integrity and high speed, and has a transparent display platform, strong universality and portability, and is convenient for storage and data sharing.

In order to solve the technical problem, the invention provides an embedded platform display system which comprises a microcontroller, a digital display, a TFT-LCD, an off-chip Flash memory, a CMSIS-DAP debugger, a PC and a national standard Chinese character word stock,

the digital display and the TFT-LCD are respectively connected with the microcontroller through an FSMC bus; the microcontroller expands the off-chip Flash memory through an SPI (serial peripheral interface), and is connected with the PC (personal computer system) through the CMSIS-DAP (China Mobile Internet protocol Security System) debugger; the PC sends the national standard Chinese character library to the microcontroller, and the microcontroller writes the national standard Chinese character library into the off-chip Flash memory in a partitioning manner;

when the embedded platform display system displays Chinese information, searching font data in a font buffer area of a main memory according to Chinese character internal codes, and reading and displaying through IAP if the searching is successful; and if the search is unsuccessful, accessing the off-chip Flash memory to acquire the character module data, writing the character module data into a character library buffer area of the main memory, and loading the character module data into the memory for display.

Preferably, the FSMC bus divides an external memory into a plurality of storage areas through a connection interface, and each storage area can be connected with one type of external equipment; each of the memory regions may be divided into a plurality of zones, each of the zones having a separate register for configuring a zone-coupled memory.

Preferably, the FSMC bus is connected with the TFT-LCD through an interface of the region, the FSMC bus interface is directly connected with a data signal and a control signal of the TFT-LCD, and the FSMC bus generates a control time sequence of the TFT-LCD;

the FSMC bus is connected with the digital display through the interface of the area, the data signals sent to the digital display by the FSMC bus are blocked by the latch module, and the chip selection signals generated by the FSMC bus are sent to the latch module after the phase inversion action of the inverter.

Preferably, the signal lines of the FSMC bus include 26-bit address lines A0-A25, 16-bit data lines D0-D15, chip select signals NE [1], NE [2], NE [3] and NE [4], an output enable NOE and a write enable NEW;

the signal lines of the TFT-LCD include 16-bit data lines D0-D15, a register/memory selection signal RS, a read enable RD, a write enable WR, a chip select signal CS and a reset RST.

Preferably, NE [4] of the FSMC bus is connected with CS of the TFT-LCD, NOE of the FSMC bus is connected with RD of the TFT-LCD, NEW of the FSMC bus is connected with WR of the TFT-LCD, an address line A6 of the FSMC bus is connected with a register/memory selection signal RS of the TFT-LCD, D0-D15 of the FSMC bus are respectively connected with D0-D15 of the TFT-LCD, and the TFT-LCD works in a 16-bit 8080 interface mode.

Preferably, the latch module comprises a plurality of latches, pins of the latches are subjected to high level transmission and low level blocking, one chip selection signal of the FSMC bus is connected with the pins of the latches in the latch module through the phase inverter, and the phase inverter is a single-path CMOS phase inverter formed by PMOS tubes and NMOS tubes.

Preferably, the latch module comprises two latches, wherein 14 signal lines including 8 segment selection lines and 6 bit selection lines of the digital display are latched by the latch module and then controlled by D0-D13 of the FSMC bus, D0-D7 of the FSMC bus are connected with the input end of one latch, and the output end of the one latch is connected with the segment selection lines A-DP of the digital display; D8-D13 of the FSMC bus is connected with the input end of another latch, and the output end of the other latch is connected with bit selection lines DS 1-DS 6 of the digital display.

Preferably, the CMSIS-DAP debugger is an onboard CMSIS-DAP debugger, supports two debugging modes of JTAG/SWD, and supports bidirectional USART communication between the embedded platform and the PC.

Preferably, the PC sends the national standard chinese character library to the microcontroller, and the microcontroller writes the national standard chinese character library in the off-chip Flash memory in blocks, specifically:

the PC machine obtains the character model data by taking the model of the national standard Chinese characters with various fonts, and synthesizes the character model data into a single character library file;

the word stock file is sent to the microcontroller in blocks through a serial port, and the microcontroller writes the word stock file into the off-chip Flash memory by taking a sector as a unit.

Preferably, the display method comprises a Chinese character display function and a Chinese-English mixed display main program,

the process of the Chinese character display function is as follows:

a1: sequentially accessing the word stock buffer zone from the initial address of the word stock buffer zone of the main memory by taking the length of the word stock structure as a step length until the word stock buffer zone is empty and finishes accessing, counting the number of the Chinese characters stored in the word stock buffer zone of the main memory, and executing a counting program only once;

a2: sequentially comparing the internal codes of the Chinese characters to be displayed in the length interval of the number of the stored Chinese characters in the character library buffer area, if the comparison is successful, reading the character module data of the current Chinese characters in the character library buffer area, and displaying the read character module data through IAP (access interface); if the comparison fails, accessing a character library file in the off-chip Flash memory to read new character module data, adding Chinese character internal codes corresponding to the new character module data as index information to the front of the new character module data, writing the Chinese character internal codes into the tail of a character library buffer area of a main memory together, and loading the Chinese character internal codes into an internal memory for display;

the process of Chinese and English mixed display comprises the following steps:

s1: reading a first element in the font data pointed by the character string pointer through the character string pointer;

s2: judging whether the value of the current element is more than or equal to 0x80, if so, determining the current element is a Chinese character, and executing S3; if not, executing S4;

s3: calling the Chinese character display function to display the current Chinese character, judging whether the display of the character module data is finished, if not, shifting a character string pointer downwards by 2 bits to read the next element, and executing S2; if so, completing display;

s4: displaying the current English character by using an IAP English display method, judging whether the display of the character module data is finished, if not, shifting a character string pointer downwards by 1 bit to read the next element, and executing S2; and if so, completing the display.

Compared with the prior art, the technical scheme of the invention has the following advantages:

1. the digital display and the TFT-LCD are simultaneously equipped through the high-speed FSMC bus, so that the digital display is connected in an extended mode, the time division multiplexing of the digital display, a TFT-LCD data line and a control line is realized, the pin resource utilization rate of the microcontroller is high, the wiring difficulty is reduced, the access speed is high, and the system reliability is improved.

2. The method comprises the steps of expanding an off-chip Flash memory by using an SPI interface, storing a word stock by the off-chip Flash memory, storing common Chinese character matrix data in a buffer area of an on-chip main memory, firstly displaying and accessing the external memory to read the matrix, buffering and storing the matrix in the main memory, and displaying again to directly access the main memory. The method has the advantages of taking the completeness and the high speed of Chinese display into consideration, and being transparent in display platform, strong in universality and good in transportability.

Drawings

In order that the present disclosure may be more readily and clearly understood, reference is now made to the following detailed description of the embodiments of the present disclosure taken in conjunction with the accompanying drawings, in which

FIG. 1 is a block diagram of the hardware architecture of the present invention;

FIG. 2 is a diagram illustrating the division of the memory region of the FSMC bus according to the embodiment of the present invention;

FIG. 3 is a schematic diagram of the read timing of the FSMC bus of the present invention;

FIG. 4 is a schematic diagram of the write timing of the FSMC bus of the present invention;

FIG. 5 is a schematic diagram of the read/write timing of the 8080 interface of the TFT-LCD according to the present invention;

FIG. 6 is a block diagram of the connection structure of the FSMC bus of the present invention;

fig. 7 is a circuit diagram showing the connection of the external memory W25Q128 in the embodiment of the present invention;

FIG. 8 is a hardware circuit diagram of a CMSIS-DAP debugger in an embodiment of the present invention;

FIG. 9 is an interface diagram of the embodiment of the present invention when a Chinese character library is prepared;

FIG. 10 is an interface diagram of serial port initialization during initialization of the microcontroller according to an embodiment of the present invention;

FIG. 11 is an interface diagram of the initialization of the SPI interface during the initialization of the microcontroller according to the embodiment of the present invention;

FIG. 12 is a diagram of an interface for initialization setup of the FSMC bus in an embodiment of the present invention;

FIG. 13 is a flow chart of the Chinese character display function of the present invention

Fig. 14 is a flow chart of chinese-english hybrid display in the present invention.

Detailed Description

The present invention is further described below in conjunction with the drawings and the embodiments so that those skilled in the art can better understand the present invention and can carry out the present invention, but the embodiments are not to be construed as limiting the present invention.

As shown in figure 1, the invention discloses an embedded platform display system, which comprises a microcontroller, a digital display, a TFT-LCD, an off-chip Flash memory, a CMSIS-DAP debugger, a PC and a national standard Chinese character word stock.

The digital display and the TFT-LCD are respectively connected with the microcontroller through an FSMC (variable Static Memory Controller, FSMC) bus, and are both hung on the high-speed FSMC bus, so that time division multiplexing of data lines and control lines of the digital display and the TFT-LCD is realized, and the CPU pin resource utilization rate is high and the access speed is high. The microcontroller expands the off-chip Flash memory through an SPI (Serial Peripheral interface), and is connected with the PC through the CMSIS-DAP debugger. And the PC sends the national standard Chinese character library to the microcontroller, and the microcontroller writes the national standard Chinese character library into the off-chip Flash memory in a partitioning manner. When the embedded platform display system displays Chinese information, searching character module data in a character library buffer zone of a main memory according to Chinese character internal codes, and reading and displaying through IAP (in Application programming) if the searching is successful; and if the search is unsuccessful, accessing the off-chip Flash memory, acquiring the character pattern data from a national standard Chinese character library of the off-chip Flash memory, writing the character pattern data into a character library buffer area of the main memory, and loading the character pattern data into the memory for display.

The FSMC bus is used for carrying out expansion connection of the digital display, the same operation is not carried out in the prior art, the FSMC bus is a flexible static storage controller essentially and is used for carrying out memory expansion, the digital display does not have a storage concept, and in addition, the digital display and the TFT-LCD share a data wire and a control wire, and control signals of the digital display need to be latched simultaneously for realizing bus multiplexing. Comparing the digital display latch time sequence with the FSMC bus chip selection time sequence, the invention inverts the chip selection signal of the digital display and then connects the inverted chip selection signal to the latch pin of the latch so as to realize automatic latch, simplifies the software design and can realize the control of the digital display by only one statement.

The Flexible Static Memory Controller (FSMC bus) can be connected with synchronous and asynchronous memories and 16-bit PC Memory cards and supports SRAM, NAND Flash, NOR Flash, PSRAM and other types of memories. All external memories connected by the FSMC bus share address, data and control signals, but have their own chip select signals, so the FSMC bus can only access one external device at a time.

The FSMC bus divides the external memory into a plurality of memory areas through a connection interface, and each memory area can be connected with one type of external equipment; each of the memory regions may be divided into a plurality of zones, each of the zones having a separate register for configuring a zone-coupled memory.

As shown in fig. 2, in this embodiment, the FSMC bus divides the external memory into four memory regions, namely Bank1, Bank2, Bank3 and Bank4, through a connection interface, the memory region Bank1 is divided into four regions, namely Sector1, Sector2, Sector3 and Sector4, the Sector4 in the Bank1 of the FSMC bus is connected to the TFT-LCD, the FSMC bus interface is directly connected to data signals and control signals of the TFT-LCD, and the FSMC bus generates an 8080 control timing sequence of the TFT-LCD; in this embodiment the FSMC bus divides the external memory 1GB space into 4 memory areas (banks) of fixed size 256MB, Bank1 can be connected to up to 4 NOR Flash or PSRAM/SRAM memory devices, Bank2 and Bank3 are used to access NAND Flash memory, one device is connected to each memory area, and Bank4 is used to connect PC Card devices. Bank1 is divided into 4 sectors (sectors), each Sector managing 64MB of space, and each Sector having separate registers to configure the attached memory. The FSMC bus is connected with the digital display through the interface of the area, the data signals sent to the digital display by the FSMC bus are blocked by the latch module, and the chip selection signals generated by the FSMC bus are sent to the latch module after the phase inversion action of the inverter. Because the digital display and the TFT-LCD are both connected on the FSMC bus of the microcontroller, and the signals of the digital display and the TFT-LCD are mutually interfered, the signals sent to the digital display need to be locked by a latch, namely, the data signals of the bus can not influence the digital display any more, and the chip selection signals automatically generated by the FSMC bus and the latch signals of the digital display have opposite high and low levels, so an inverter is needed between the digital display and the TFT-LCD.

The signal lines of the FSMC bus include 26-bit address lines A [25:0], 16-bit data lines D [15:0], chip select signals NE [1], NE [2], NE [3] and NE [4], an output enable NOE and a write enable NEW. A [25:0] represents 26-bit address lines of A0 to A25, and D [15:0] represents 16-bit data lines of D0 to D15. The read timing of the FSMC bus is shown in fig. 3 and the write timing of the FSMC bus is shown in fig. 4, which is a pattern that is well suited for NOR FLASH/PSRAM/SRAM memory connected to Bank1.

The signal lines of the TFT-LCD include 16-bit data lines D [15:0], a register/memory select RS, a read enable RD, a write enable WR, a chip select CS and a reset RST, and are connected to the microcontroller using a standard 16-bit 8080 parallel port. The read and write timing of the 8080 interface of the TFT-LCD is shown in FIG. 5.

Comparing the read-write timing of fig. 3-5 with the FSMC bus and the TFT-LCD control signals, it can be seen that the TFT-LCD can be provided by the FSMC bus interface in addition to the RST signal already connected to the system reset circuit, so that the FSMC bus connected PSRAM/SRAM mode is suitable for connecting the TFT-LCD display module.

The 256MB space of Bank1 is addressed by 28 address lines (HADDR [27:0], HADDR 0-HADDR 27]), and the Bank1 memory Bank selection is shown in Table 1:

table 1 Bank1 memory area selection table

In Table 1, HADDR is the internal AHB bus address, where HADDR [25:0] is from A [25:0] of the external memory address FSMC bus, corresponding to the pin address signal, and HADDR [27:26] addresses 4 sectors, done automatically by the system, with no external pin corresponding signal.

In the embodiment, the microcontroller is an STM32F407ZET6 microcontroller with powerful performance based on an ARM Cortex-M4 inner core, 168MHz main frequency, 512KB in-chip Flash ROM, a complete FSMC bus interface and faster USART and SPI communication speed. The flexible static storage controller FSMC bus is used for connecting the digital display and the TFT-LCD, the utilization rate of CPU pin resources is high, and the access speed is high. The off-chip Flash memory is an off-chip Flash ROM W25Q128, and the off-chip Flash ROM W25Q128 is connected with the chip by using the SPI interface. The onboard CMSIS-DAP debugger supports two debugging modes of JTAG/SWD, and has a serial port communication function. The embedded platform is provided with a double-display terminal, the digital display is a 6-bit 0.56-inch common-anode digital display, and the PNP triode S8550 is used for driving; the liquid crystal display is a 2.8-inch full-color TFT-LCD display module, 240 x 320 pixels, 2.8-3.3V power supply, ILI9341 drive and a 16-bit 8080 parallel interface.

As shown in FIG. 6, NE [4] of the FSMC bus is connected with a chip selection signal CS of the TFT-LCD, NOE of the FSMC bus is connected with a read pin RD of the TFT-LCD, NEW of the FSMC bus is connected with a write pin WR of the TFT-LCD, A6 address lines of the FSMC bus are connected with a register/memory selection signal RS of the TFT-LCD, D [15:0] of the FSMC bus is respectively connected with D [15:0] of the TFT-LCD, and the TFT-LCD works in a 16-bit 8080 interface mode.

The embedded platform display system further comprises a latch module U3 and an inverter U2, the latch module comprises a plurality of latches, the digital display and the TFT-LCD are simultaneously hung on the FSMC bus of the STM32F4, the digital display and the TFT-LCD share a data line, in order to enable output signals of the digital display and the TFT-LCD not to influence each other, data signals sent to the digital display need to be latched, in the embodiment, the latch module comprises 2 latches of 74HC573D type, and pins LE of the latches are subjected to high level transmission and low level blocking. Bank1.Sector3 of the selected FSMC bus is connected with a 6-bit common anode digital display, therefore, NE [3] of the FSMC bus is used as a chip selection signal of the digital display, but NE [3] is active at low level and is opposite to a latch transmission signal, therefore, NE3 of the FSMC bus needs to be connected with a pin LE of a latch of two pieces 74HC573D in the latch module U3 through the inverter U2, only one inverter is needed, the inverter is a single-path CMOS inverter consisting of 1 PMOS tube and 1 NMOS tube, and the single-path CMOS inverter consisting of 1 PMOS tube and 1 NMOS tube is adopted in the implementation of the embedded platform display system in the embodiment.

The latch module comprises two latches, wherein 14 signal wires including 8 segment selection wires and 6 bit selection wires of the digital display are controlled by D [13:0] of the FSMC bus after being latched by the latch module U3, D [7:0] of the FSMC bus is connected with the input end of one latch, the output end of the latch is connected with the segment selection wires A-DP of the digital display, D [13:8] of the FSMC bus is connected with the input end of the other latch, and the output end of the other latch is connected with the bit selection wires DS 1-DS 6 of the digital display.

The design realizes time division multiplexing of the digital display and the TFT-LCD data line and control line, reduces GPIO requirements of the microcontroller, saves CPU resources, reduces PCB wiring difficulty and improves system reliability.

The external memory in the embodiment is selected from a Flash memory, and the Flash memory combines the advantages of a ROM and a RAM, and not only has electrically erasable programmable read-only memoryDevice (E) ² PROM), and can also read data quickly, which has the advantage of non-volatile random access memory. In order to store the word bank data, a NOR Flash memory chip W25Q128 with the capacity of 128Mbit is expanded in the embodiment and is connected to an SPI1 interface of the microcontroller, and a hardware circuit is shown in FIG. 7. The DO, DI, CLK pins of the W25Q128 chip are connected to the SPI1_ MISO (PB4), SPI1_ MOSI (PB5), SPI1_ SCK (PB3) of the microcontroller, respectively. The PB14 pin of the microcontroller being connected to the memory

And pin selection and low level selection. Memory chip

And

the pin is VDD, i.e., no write protection and data retention functions are used.

The CMSIS-DAP debugger is an onboard CMSIS-DAP debugger, supports two debugging modes of JTAG/SWD, and supports bidirectional USART communication between the embedded platform and the PC.

In this embodiment, a hardware circuit of the CMSIS-DAP debugger is shown in fig. 8, a circuit core is an F103T8U6 microcontroller, and by running a monitoring program and simulating two debugging protocols of JTAG/SWD, all debugging modes such as one-key downloading, single step, continuous and the like can be realized. The monitoring program also virtualizes a USART serial interface for bidirectional data communication between the embedded platform and the upper computer. The CMSIS-DAP debugger can realize four-in-one functions of downloading, debugging, communication and power supply of an embedded platform, and has the advantages of being open-source, high-speed, free of driving and the like.

To realize Chinese display, a corresponding Chinese character library is required to be made for each font, and the character library is stored in the off-chip SPI Flash. The project software is large in size and is completed in stages during implementation, the main content of the first stage work is to generate a word stock and store the word stock in the off-chip SPI Flash, and the second stage work is to develop a Chinese character display program. The two-stage operation is closely related and must be considered through the whole process, and the two processes are different programs and need to be designed and operated independently.

In this embodiment, the PC sends the national standard chinese character library to the microcontroller, and the microcontroller writes the national standard chinese character library into the off-chip Flash memory in blocks, which includes the following specific processes: the PC machine gets the module of the national standard Chinese character with various fonts to obtain the character module data, and synthesizes the character module data into a single character library file; the character library file sectors are aligned, blank characters are filled in the middle, the tail end is finished by a carriage return line-changing symbol, the synthesized character library is written into the SPI flash memory, a font character library always starts to be stored from the initial address of a certain sector, transmission software automatically stops transmitting when meeting the ending symbol, and the synthesized character library is more applicable. The word stock file is sent to the microcontroller in blocks through a serial port, and the microcontroller writes the word stock file into the off-chip Flash memory by taking a sector as a unit. Different font word stock files are combined into a total word stock to be stored in an off-chip Flash memory, so that the storage efficiency is greatly improved, and the data sharing is more convenient.

In the present embodiment, the chinese display system uses the GB2312 character set, which includes 8178 characters including chinese characters, full-size english characters, and part of special characters, each character has four fonts, which are 12 × 12, 16 × 16, 24 × 24, and 32 × 32, and in order to implement the first step of chinese display, it is necessary to create a library file with different fonts. The setting interface of the character library in the 16 x 16 of the songhua 16 manufactured by the PCtoLCD2002 software is shown in fig. 9, and the option of the character module is set as: the negative code, reverse and line-by-line modes have different scanning modes for different driving chips. The modulo operation for other character sizes can be realized by only modifying the character width and the character height marked by the square frame line in the figure 9. And then clicking a button of a toolbar for importing a large number of texts or generating a word stock by one text file, keeping a default option, and clicking a button for generating a national standard Chinese word stock to generate a binary word stock file. According to the method, the font library files corresponding to the four fonts are sequentially generated.

The produced Chinese character library is mass data relative to a microcontroller main memory, so that a NOR Flash memory W25Q128 with an SPI interface is added outside the system and used for storing the information of the Chinese character library.

The total capacity of the W25Q128 is 16MB, the access unit of the memory is divided into blocks, sectors and pages, which is complicated, because erasing and writing are performed in units of sectors, it is only necessary to know that the whole memory space is divided into 4096 sectors, and the size of each sector is 4096 bytes, so that the upper 12 bits of the 24-bit address of the memory represent a sector number and the lower 12 bits represent a byte address in the sector. NOR Flash can start with any address, but before writing it must be guaranteed that the unit to be written is originally blank (0xFF), otherwise it must be erased before writing, and the entire sector must be erased for erasing.

The space occupied by the font library in the 4 fonts manufactured in the embodiment is close to 2MB, and considering that other applications are used to frequently read and write from an address 0, for example, SPI communication experiments of embedded courses, the font library is stored in a high 8MB space of a Flash chip, that is, from an address 0x 00800000, and meanwhile, for convenience in erasing and reading and writing, the storage of the font library is aligned according to sectors, and the space occupied by the font library and detailed address allocation information are shown in table 2.

Table 2 font library address allocation table

Because the data volume of the word library file is far beyond the SRAM capacity of the micro controller, the word library file cannot be directly read and written into an external memory, but the micro controller can be used as a transfer station, a data transmission channel is established between a PC (personal computer) and the micro controller, the PC sends data in batches, and the micro controller circularly receives real-time writing. Therefore, the word stock storage software design is divided into an upper computer software development part and a lower computer program design part, and the lower computer program design part comprises a microcontroller end program design part and a storage operation design part.

Designing upper computer software: the upper computer software is developed by adopting a visual programming tool, and a program firstly acquires the available serial port of the PC and initializes the serial port. And then waiting for the lower computer to return to the Flash chip initialization state until the lower computer is ready, loading the word library file, and sending a transmission starting command containing the initial address and the data length to the lower computer. And sequentially transmitting the word library file in 4096B blocks, and inserting software delay after the transmission of each block of data is finished so as to wait for the lower computer to finish data receiving and storing operations. And circularly sending the data until the transmission of the word stock data is finished, and displaying the data receiving and processing state of the lower computer in real time in the whole communication process.

Designing a microcontroller end program: in order to realize that the serial port receives the font library data sent by the upper computer and writes the font library data into the W25Q128, the USART and the SPI interface need to be initialized firstly. As shown in fig. 10, the serial port initialization interface selects USART1, asynchronous operating mode, baud rate 115200bps, data width 8 bits, 1 bit stop bit, no parity bit, and opens serial port reception interrupt. As shown in fig. 11, the SPI interface initialization interface selects SPI1, full duplex mode, Motorola frame format, 8-bit data width, MSB advanced, prescaler coefficient 8, baud rate 10Mbps, high clock, clock phase jump for 2 nd edge, and NSS signal type software setting. Because the system uses the hardware SPI, the library function can be called to realize the receiving and sending of byte data after the initialization, but a driver program needs to be written for reading and writing the SPI interface Flash chip W25Q 128. After the microcontroller completes initialization, the serial port is in a data receiving state, when a data transmission preparation command sent by the upper computer is monitored, a data storage initial address and a data storage length are obtained, all sectors used for storing the word stock are erased, and response information is sent. And when the upper computer confirms that the microcontroller is ready, the data transmission is started immediately. The microcontroller performs a W25Q128 write operation, i.e., a sector write, every time 4096B data is received, while resetting the buffer data pointer. When all data is received, the data length of the last frame needs to be calculated and written into the last sector.

And (3) storage operation: the 4-library file generated by modulo operation in fig. 9 needs to be written into the SPI Flash memories according to the start addresses determined in table 2, which is very troublesome and prone to errors during product production. Therefore, 4 character library files are combined into a total character library through the programming language, the storage efficiency is greatly improved, and the data sharing is more convenient. The sectors of the synthesized word stock are aligned, blank characters are filled in the middle, and the tail ends are finished by a carriage return line feed character.

And connecting the embedded platform and the PC through the CMSIS-DAP debugger, downloading a microcontroller terminal word library storage program, and resetting and running. Starting an upper computer communication software W25Qxx serial port download assistant developed by a visual programming tool, and selecting a chip: W25Q128, input start address: 0x 00800000, opening the synthesized font library file, clicking a file sending button after the lower computer is successfully initialized, starting file transmission, and completing the transmission and writing work of the font library file after a period of time.

In the running process of a user program, application programming (IAP) accesses the built-in flash memory module through an internal I-Code command bus or a D-Code data bus, can update and upgrade the firmware program through a reserved communication interface, and can also use a partial area of a main memory as a data storage area to realize quick access of batch data.

The main memory of the STM32F4 is used for storing code and data constants and is divided into 12 sectors, the first 4 sectors are 16KB in size, then the sector4 is 64KB in size, the sectors 5-11 are 128KB in size, the Flash capacity of microcontrollers of different models is different, the embedded platform designed in the embodiment is provided with an F407ZET6 microcontroller, the capacity of the main memory is 512KB, and the embedded platform has 8 sectors.

The starting address of the system main memory is 0x08000000, from which the CPU runs code when the chip BOOT0, BOOT1 pins are both grounded. The main memory data storage area can not be overlapped with the code area when being set, otherwise, the programs are disordered, and unknown errors are caused. The insurance practice is to place the data area in the last sector of main memory, i.e. sector 7 of F407ZET6, with the address range: 0x 08060000-0 x0807FFFF, total 128KB, when in use, 4 font buffers only occupy the low 96KB of the whole sector, and the detailed address space allocation is shown in Table 3.

Table 3 main memory buffer space allocation table

As can be seen from table 3, the storage space occupied by a single chinese character in each font is added with index information of two bytes in addition to the font information of the chinese character itself, for storing the internal code of the chinese character. Because the design buffers the information of the Chinese character library in the main memory, the font data is randomly stored, and the Chinese character internal code is used as the index information for determining the character corresponding to the font information, which is simple and effective because the Chinese characters are stored and transmitted in the internal code in all computer equipment.

The library information is buffered in main memory, including both IAP write and IAP read operations. The main memory can be written by taking a word, a half word and a byte as a unit, the word writing speed is fastest, and the byte writing speed is slowest. As can be seen from table 3, the length of each font type data is not a multiple of 4 but is still a multiple of 2 after the index information is added, so the font information is buffered and written in units of half-words. The word stock is ring-buffered in the main memory, and since NOR Flash can only write in blank cells, the buffered data is written in sequence, and when the buffer is full, the data needs to be written in from the beginning, but at this time, the whole sector needs to be erased and written in again.

The main memory IAP is relatively simple, and is also a typical working state of the main memory, the Chinese character library is stored in the main memory from a certain address in sequence, and a reading method corresponding to writing can be adopted, namely, one Chinese character structure data is read into the SRAM at one time, and then data processing is carried out. The method in the embodiment is to convert the initial address of the word stock into the structural body pointer of the word stock and then access the word stock in a structural body array mode, the time complexity and the space complexity are minimum, and the strength and the flexibility of the C language pointer are reflected.

When the embedded platform display system realizes the information display of the TFT-LCD, the FSMC bus is initialized firstly, the TFT-LCD needs to be driven when the display displays, and the LCD is hung on the FSMC bus, so the first step is the initialization of the FSMC bus of the LCD. The initialization interface of the TFT-LCD in this embodiment is shown in fig. 12, and all the information required to be configured is indicated by square lines in fig. 12. Firstly, a Mode option is set, NOR Flash/PSRAM/SRAM/ROM/LCD 4 (all refer to peripheral types connectable with an FSMC bus, the first 4 are memories, the 5 th is an LCD interface, and the last number 4 refers to configuration Bank1.Sector4) is configured, namely, Bank1.Sector4 is selected to be connected with TFT-LCD, a chip selection signal: NE4, memory type: LCD Interface, LCD RS signal: a6, data width: 16 bits. Configuring Configuration option content, selecting mode a to separately set read/write timing control LCD display screen, setting time parameter as large as possible when setting read timing since LCD read speed is much slower than write speed, in this embodiment, ADDSET and DATAST are set to 15 and 59, respectively, for STM32F407 microcontroller, 168MHz master frequency, HCLK is about 6ns, corresponding address setup time is 15 x 6 ns-90 ns, and data setup time is (59+1) × 6 ns-360 ns. The time parameter setting of the LCD write timing is suitably smaller, in this embodiment, ADDSET and DATAST are set to 9 and 8, respectively, and the time values corresponding to both parameters are about 54 ns. The above parameter setting can ensure the stable operation of the conventional driving chip ILI9341 of the 2.8-inch TFT-LCD with a sufficient margin.

Configuring and automatically generating an FSMC bus initialization code in STM32CubeMX, defining an LCD structure body, determining a base address, and writing an LCD bottom driver; and basic display and high-level application codes provided by a display screen manufacturer are transplanted, so that the TFT-LCD display control can be realized.

After the overall system planning, the font library module taking and off-chip storage, the main memory IAP reading and writing, the LCD initialization and the drive transplantation and other works are completed, the design of the embedded platform Chinese display system based on the SPI flash memory and the main memory IAP can be developed.

The display method comprises a Chinese character display function and a Chinese and English mixed display main program;

as shown in fig. 13, the process of displaying chinese characters is:

a1: calculating the word number of the word library buffer of the main memory: the word stock buffer areas are sequentially accessed from the initial address of the word stock buffer area of the main memory by taking the length of the word stock structure as a step length until the word stock buffer area is empty (in the embodiment, two continuous bytes are 0xFF), the number of the Chinese characters stored in the word stock buffer area of the main memory is counted, and the counting program is executed only once.

A2: sequentially comparing the internal codes of the Chinese characters to be displayed in the length interval of the number of the stored Chinese characters in the character library buffer area, if the comparison is successful, indicating that the character module data exists in the character library buffer area of the main memory, reading the character module data of the current Chinese characters in the character library buffer area, and displaying the read character module data through IAP; and if the comparison fails, accessing a character library file in the off-chip Flash memory to read new character module data, adding Chinese character internal codes corresponding to the new character module data as index information to the front of the new character module data, writing the Chinese character internal codes into the tail of a character library buffer area of the main memory together, and loading the Chinese character internal codes into the memory for display.

As shown in fig. 14, the process of the chinese-english hybrid display is as follows:

The GB2312 character set is a region bit code and is divided into 94 regions, each region has 94 characters, and the region number and the bit number of each character are added with 0xA1 to form the Chinese character internal code. When the national standard word stock is made, it is stored according to the zone number, so that the internal code is reduced into zone number, then the zone number is multiplied by 94, and added with the zone number, i.e. the offset of said Chinese character in the word stock, so that the absolute address of the displayed Chinese character in W25Q128 can be calculated, from which the character mould data can be read out, and the Chinese character display can be implemented. And adding the Chinese character internal code corresponding to the character die information as index information to the front of the character die data, and writing the index information into the tail of the character library storage area of the IAP main memory buffer area to realize the character library buffer storage of the Chinese character. Since the main memory NOR Flash is a nonvolatile random access memory, and the buffer area is set to be large, and is mostly buffered once, it is always beneficial, and thus there is no need to care about the specific storage location of the word stock.

The invention simultaneously arranges the digital display and the TFT-LCD through the high-speed FSMC bus, realizes the expanded connection of the digital display, realizes the time division multiplexing of the digital display and the TFT-LCD data wire and control wire, has high utilization rate of pin resources of the microcontroller, reduces the wiring difficulty, has high access speed and improves the system reliability. And simultaneously, an off-chip Flash memory is expanded by using an SPI (serial peripheral interface), a word library is stored in the off-chip Flash memory, common Chinese character matrix data are stored in a buffer area of the on-chip main memory, the read matrix is firstly displayed and accessed to the external memory and is stored in the main memory in a buffer way, and the main memory is displayed and directly accessed again. The method has the advantages of taking the completeness and the high speed of Chinese display into consideration, and being transparent in display platform, strong in universality and good in transportability.

The embodiment passes practical tests and realizes the display of all Chinese characters, and the display effect is clear and smooth; compared with the direct parallel port control of the microcontroller, the method has the advantages that the occupation rate of GPIO pin resources is reduced by 38.2%, the refresh rate of the display is improved by 14.4 times, the Chinese display rate is improved by 6.9 times compared with the SPI Flash storage mode, the main memory IAP buffers at one time, the effect of the method is always benefited, and the display system is transparent to users, strong in universality and good in transportability.

As will be appreciated by one skilled in the art, embodiments of the present application may be provided as a method, system, or computer program product. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.

The present application is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the application. It will be understood that each flow and/or block of the flow diagrams and/or block diagrams, and combinations of flows and/or blocks in the flow diagrams and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

It should be understood that the above examples are only for clarity of illustration and are not intended to limit the embodiments. Other variations and modifications will be apparent to persons skilled in the art in light of the above description. This need not be, nor should it be exhaustive of all embodiments. And obvious variations or modifications of the invention may be made without departing from the spirit or scope of the invention.

Claims

1. An embedded platform display system, characterized by: comprises a microcontroller, a digital display, a TFT-LCD, an off-chip Flash memory, a CMSIS-DAP debugger, a PC and a national standard Chinese character library,

2. The embedded platform display system of claim 1, wherein: the FSMC bus divides an external memory into a plurality of storage areas through a connection interface, and each storage area can be connected with one type of external equipment; each of the memory regions may be divided into a plurality of zones, each of the zones having a separate register for configuring a zone-coupled memory.

3. The embedded platform display system of claim 2, wherein: the FSMC bus is connected with the TFT-LCD through an interface of the area, the FSMC bus interface is directly connected with a data signal and a control signal of the TFT-LCD, and the FSMC bus generates a control time sequence of the TFT-LCD;

the FSMC bus is connected with the digital display through the interface of the area, the data signals sent to the digital display by the FSMC bus are blocked by the latch module, and the chip selection signals generated by the FSMC bus are sent to the latch module after the phase reversal effect of the inverter.

4. The embedded platform display system of claim 3, wherein: the signal lines of the FSMC bus include 26-bit address lines A0-A25, 16-bit data lines D0-D15, chip select signals NE [1], NE [2], NE [3] and NE [4], an output enable NOE and a write enable NEW;

5. The embedded platform display system of claim 4, wherein: NE [4] of the FSMC bus is connected with CS of the TFT-LCD, NOE of the FSMC bus is connected with RD of the TFT-LCD, NEW of the FSMC bus is connected with WR of the TFT-LCD, an address line A6 of the FSMC bus is connected with a register/memory selection signal RS of the TFT-LCD, D0-D15 of the FSMC bus are respectively connected with D0-D15 of the TFT-LCD, and the TFT-LCD works in a 16-bit 8080 interface mode.

6. The embedded platform display system of claim 4, wherein: the latch module comprises a plurality of latches, pins of the latches are subjected to high level transmission and low level blocking, a chip selection signal of the FSMC bus is connected with the pins of the latches in the latch module through the phase inverter, and the phase inverter is a single-path CMOS phase inverter formed by PMOS tubes and NMOS tubes.

7. The embedded platform display system of claim 6, wherein: the latch module comprises two latches, wherein 14 signal wires including 8 segment selection wires and 6 bit selection wires of the digital display are controlled by D0-D13 of the FSMC bus after being latched by the latch module, D0-D7 of the FSMC bus are connected with the input end of one latch, and the output end of the latch is connected with the segment selection wires A-DP of the digital display; D8-D13 of the FSMC bus are connected with the input end of another latch, and the output end of the other latch is connected with bit selection lines DS 1-DS 6 of the digital display.

8. The embedded platform display system of claim 1, wherein: the CMSIS-DAP debugger is an onboard CMSIS-DAP debugger, supports two debugging modes of JTAG/SWD, and supports bidirectional USART communication between the embedded platform and the PC.

9. The embedded platform display system according to claim 1, wherein: the PC sends the national standard Chinese character library to the microcontroller, and the microcontroller writes the national standard Chinese character library into the off-chip Flash memory in blocks, which specifically comprises the following steps:

10. The embedded platform display system according to any one of claims 1-9, wherein: the display method comprises a Chinese character display function and a Chinese-English mixed display main program,

the process of the Chinese character display function is as follows:

a2: sequentially comparing the internal codes of the Chinese characters to be displayed in the length interval of the number of the stored Chinese characters in the character library buffer area, reading the character pattern data of the current Chinese characters in the character library buffer area if the comparison is successful, and displaying the read character pattern data through IAP (Internet access interface); if the comparison fails, accessing a character library file in the off-chip Flash memory to read new character module data, adding Chinese character internal codes corresponding to the new character module data as index information to the front of the new character module data, writing the Chinese character internal codes into the tail of a character library buffer area of a main memory together, and loading the Chinese character internal codes into an internal memory for display;

the process of Chinese and English mixed display comprises the following steps: