CN115062568A - Static simulation method, system and computer equipment for semiconductor process cycle - Google Patents

Static simulation method, system and computer equipment for semiconductor process cycle Download PDF

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CN115062568A
CN115062568A CN202210467484.5A CN202210467484A CN115062568A CN 115062568 A CN115062568 A CN 115062568A CN 202210467484 A CN202210467484 A CN 202210467484A CN 115062568 A CN115062568 A CN 115062568A
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time
cycle time
historical
process step
target process
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王晓
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Changxin Memory Technologies Inc
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    • G06F30/33—Design verification, e.g. functional simulation or model checking
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Abstract

The present disclosure relates to a method, system, computer device and computer readable storage medium for static simulation of a semiconductor process cycle. The static simulation method of the semiconductor process period comprises the following steps: acquiring standard cycle time of a target process step; acquiring historical cycle time of a target process step; and acquiring the estimated cycle time of the target process step within a first preset time according to the historical cycle time, the standard cycle time and a time variable, wherein the estimated cycle time is the same as the historical cycle time at the starting time of the first preset time, and the estimated cycle time is the same as the standard cycle time at the ending time of the first preset time. The embodiment of the disclosure can effectively improve the simulation accuracy.

Description

Static simulation method, system and computer equipment for semiconductor process cycle
Technical Field
The present disclosure relates to the field of semiconductor simulation technologies, and in particular, to a static simulation method, system, computer device, and computer-readable storage medium for a semiconductor process cycle.
Background
With the development of the semiconductor industry, analog simulation technology for the semiconductor production process appears. The simulation estimation mode comprises a static simulation mode and a dynamic simulation mode. Meanwhile, the chip material enters a Step for processing, from the last station to the last station, and leaves the current station after the processing is finished, called Step (or operation), and the Time from the beginning to the end is called Step Cycle Time (CT for short).
At present, the static simulation mode is generally a mode of predicting according to time course according to a fixed production flow and a given standard CT of each step when the production simulation is carried out; the dynamic simulation method generally includes, during production simulation, establishing production resources (such as a device list), a product processing flow sequence and a standard processing Time (Process Time) in a system, so that materials are processed in a virtual production environment in a manner similar to a real world processing manner and enter and exit the device, and more materials are automatically queued in front of the device to be processed. Although the dynamic simulation mode can realize high-accuracy simulation prediction, the dynamic simulation mode has high difficulty and high cost. Static state estimation may be used when cost reduction is desired.
However, the accuracy of the current static simulation mode is low, and good simulation prediction of the production process is difficult to perform.
Disclosure of Invention
In view of the above, in view of the above technical problems, embodiments of the present disclosure provide a static simulation method, system, computer device, and computer-readable storage medium capable of improving simulation accuracy of a semiconductor process cycle.
A static simulation method of a semiconductor process cycle comprises the following steps:
acquiring standard cycle time of a target process step;
acquiring historical cycle time of a target process step;
and acquiring the estimated cycle time of the target process step within a first preset time according to the historical cycle time, the standard cycle time and a time variable, wherein the estimated cycle time is the same as the historical cycle time at the starting moment of the first preset time, and the estimated cycle time is the same as the standard cycle time at the ending moment of the first preset time.
In one embodiment, the obtaining an estimated cycle time of the target process step within a first preset time according to the historical cycle time, the standard cycle time, and a time variable includes:
acquiring a gradual change function related to a time variable, wherein when the time variable is sequentially valued within the first preset time, the value of the gradual change function is gradually changed from 1 to 0 or gradually changed from 0 to 1;
and acquiring the estimated cycle time of the target process step within a first preset time according to the historical cycle time, the standard cycle time and the gradual change function.
In one embodiment, the obtaining the target process step after the pre-estimated cycle time within the first preset time further includes:
refreshing the historical cycle time;
and updating the estimated cycle time according to the refreshed historical cycle time.
In one embodiment, the historical cycle time is refreshed according to a preset frequency.
In one embodiment, the predetermined frequency is refreshed every hour.
In one embodiment, the refreshing the historical cycle time includes:
acquiring the running time of each batch which has undergone the target process step within a second preset time before the refreshing time;
and refreshing the historical cycle time according to the running time of each batch which has undergone the target process step within a second preset time before the refreshing time.
In one embodiment, the obtaining the historical cycle time of the target process step includes:
acquiring the running time of each batch which has undergone the target process step within a second preset time before the simulation time;
and acquiring the historical cycle time according to the running time of each batch of the target process steps within second preset time before the simulation time.
In one embodiment, when the time variables take values sequentially within the first preset time, the value of the gradual change function changes smoothly between 0 and 1.
In one embodiment, the operation expression for obtaining the estimated cycle time of the target process step within the first preset time according to the historical cycle time, the standard cycle time and the gradual change function is as follows:
CT 1 ＝L*y 1 (x)+S*(1-y 1 (x))，
wherein, CT 1 For the estimated cycle time, L is the historical cycle time, S is the standard cycle time, y 1 Is a gradual change function, x is a time variable, and y is a time variable when x is sequentially valued within the first preset time 1 The value of (c) is gradually changed from 1 to 0.
In one embodiment, the first preset time is 24 hours.
In one embodiment, the operation expression of the gradual change function is:
y 1 (x)＝(cos((3.14159265/24)*x)+1)/2。
in one embodiment, the operation expression for obtaining the estimated cycle time of the target process step within the first preset time according to the historical cycle time, the standard cycle time and the gradual change function is as follows:
CT 1 ＝L*(1-y 2 (x))+S*y 2 (x)，
wherein, CT 1 For the estimated cycle time, L is the historical cycle time, S is the standard cycle time, y 2 Is a gradual change function, x is a time variable, and y is a time variable when x is sequentially valued within the first preset time 2 The value of (c) is gradually changed from 0 to 1.
In one embodiment, the method comprises the following steps:
the first acquisition module is used for establishing standard cycle time of a target process step;
the second acquisition module is used for acquiring the historical cycle time of the target process step;
and the estimation module is used for acquiring the estimation cycle time of the target process step within first preset time according to the historical cycle time, the standard cycle time and the time variable, wherein the estimation cycle time is the same as the historical cycle time in the starting section of the preset time, and the estimation cycle time is the same as the standard cycle time in the ending section of the preset time.
A computer device comprising a memory storing a computer program and a processor implementing the steps of the method of any preceding claim when the processor executes the computer program.
A computer-readable storage medium, on which a computer program is stored which, when being executed by a processor, carries out the steps of the method of any of the above.
In the static simulation method, the system, the computer equipment and the computer readable storage medium for the semiconductor process period, historical period time is also merged into the estimation of the estimated period time of the target process step besides the standard period time, the estimated period time in the first preset time is obtained according to the historical period time, the historical real time is obtained when the estimated period time starts, and the standard period time is recovered at the later stage. The process is consistent with the actual production process, so that the simulation accuracy can be effectively improved.
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In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the conventional technologies, the drawings used in the description of the embodiments or the conventional technologies will be briefly introduced below, it is obvious that the drawings in the following description are only some embodiments of the present disclosure, and for those skilled in the art, other drawings can be obtained according to the drawings without any creative work.
FIG. 1 is a schematic flow chart illustrating a method for static simulation of a semiconductor process cycle according to an embodiment;
FIG. 2 is a schematic diagram illustrating estimated cycle times for multiple batches of chip material through multiple process steps, according to one embodiment;
FIG. 3 is a graph of predicted cycle time profiles for a plurality of lots for a particular process step in one embodiment;
FIG. 4 is a schematic diagram illustrating the number of lots processed by equipment A after a first time;
FIG. 5 is a graphical representation of the number of process steps that are elapsed while LotA is over the second time;
FIG. 6 is a diagram of a functional image of a fading function in one embodiment;
FIG. 7 is a block diagram of a static simulation system for a semiconductor process cycle in one embodiment;
FIG. 8 is a block diagram of a static simulation system for a semiconductor process cycle in another embodiment.
Description of reference numerals: 100-a first acquisition module, 200-a second acquisition module, 300-a prediction module, 310-a function unit, 320-a prediction unit.
Detailed Description
To facilitate an understanding of the present disclosure, the present disclosure will now be described more fully with reference to the accompanying drawings. Embodiments of the present disclosure are presented in the drawings. This disclosure may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used herein in the description of the disclosure is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure.
It will be understood that the terms "first," "second," and the like as used in this disclosure may be used herein to describe various preset times, but these preset times are not limited by these terms. These terms are only used to distinguish a first element from another preset time.
As used herein, the singular forms "a", "an" and "the" may include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises/comprising," "includes" or "including," etc., specify the presence of stated features, integers, steps, operations, components, parts, or combinations thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, components, parts, or combinations thereof.
In one embodiment, referring to fig. 1, a method for static simulation of a semiconductor process cycle is provided, which includes:
step S100, acquiring standard cycle time of a target process step;
step S200, acquiring historical cycle time of a target process step;
step S300, according to the historical period time, the standard period time and the time variable, acquiring the estimated period time of the target process step within the first preset time, wherein the estimated period time is the same as the historical period time at the starting moment of the first preset time, and the estimated period time is the same as the standard period time at the ending moment of the first preset time.
In step S100, the standard cycle time of the target process step can be obtained by new creation, or can be selected from the existing standard cycle times that have already been established, which is not limited herein.
I.e., the standard CT of the target process step, i.e., the standard time from when the chip material enters the target process step for processing to when the processing is completed and leaves the site of the target process step.
As an example, the chip material may be processed in batches. For example, the chip material may be packaged in standard sealed cassettes (SMIF PODs), each of which may contain 25 pieces, thereby forming a batch of chip material.
At this time, the standard cycle time of the target process step may be: and when a batch of chip materials enters the target process step to be processed, the standard time from the last station to the point of leaving the target process step after the processing is finished is reached.
Specifically, the standard cycle time of the target process step may include a standard processing time and a standard waiting time thereof. Wherein, the standard processing time of the target process step can be as follows: a batch of chip material is processed at the target process step at a standard time from the beginning of entering the tool to the end of exiting the tool (i.e., the end of processing exits the site where the target process step is located). The standard wait time for the target process step may be: a batch of chip material is processed from the end of the last process step of the target process step (i.e., from the end of the last station) to the standard time at which the target process step begins.
When the target process step is the first step in the process, the standard processing time is zero.
In step S200, the historical cycle time may be obtained according to the historical actual CT of the chip material when entering the target process step for processing, that is, the historical actual time from the last station to the station where the chip material leaves the target process step after the chip material enters the target process step for processing.
In particular, the chip material may be processed in batches. At this time, as an example, the historical cycle time may be obtained from an average or median, etc., of historical actual CTs of a plurality of batches of chip materials.
In step S300, the first preset time may be set according to actual conditions. The time variable may be a time point within a first predetermined time. According to the historical cycle time, the standard cycle time and the time variable, the estimated cycle time of the target process step in the first preset time is obtained, and the estimated cycle time of each time point of the target process step in the first preset time can be obtained. The value of the estimated cycle time may be gradually changed from the historical cycle time to the standard cycle time between the start time and the end time of the first preset time.
For example, the first preset time may be set to 24 hours. At this time, the first preset time may include 25 time points from 0 hour to 24 hours. The 0 th time point may represent a start time and the 24 th time point may represent an end time. The value of the estimated cycle time is the same as the historical cycle time at the starting time of the first preset time, namely the value of the estimated cycle time is the historical cycle time at the 0 th time point. The value of the pre-estimated cycle time is the same as the standard cycle time at the end time of the first preset time, namely at the 24 th time point, the value of the pre-estimated cycle time is the standard cycle time. And at the 1 st to 23 rd time points, the value of the estimated cycle time is gradually changed from the historical cycle time to the standard cycle time.
In the static simulation method in this embodiment, in the estimation of the estimated cycle time of the target process step, the historical cycle time is also incorporated in addition to the standard cycle time, and the estimated cycle time in the first preset time is obtained according to the standard cycle time, the historical real time is obtained at the beginning of the estimated cycle time, and the standard cycle time is returned to the later stage. The process is consistent with the actual production process, so that the simulation accuracy can be effectively improved.
The above contents are simulated and pre-estimated for the estimated cycle time of the target process step within the first preset time.
Multiple process steps may be involved in the production process. Each process step can be used as a target process step, so that the production period of the whole production process can be accurately estimated. Specifically, fig. 2 illustrates the estimated cycle time of a plurality of lots (Lot) of chip materials passing through a plurality of process steps (step). FIG. 3 illustrates an estimated cycle time profile for a plurality of batches through a particular process step.
Therefore, the embodiments of the present disclosure have different estimated cycle times for different batches (Lot) of chip materials entering the same process step at different times. For a process step, if there is a recent anomaly, the system will automatically sense the anomaly and recover to normal within a certain time. At the moment, the bottleneck queuing effect can be reflected, so that the bottleneck queuing effect is more consistent with the actual situation, and the production process can be accurately estimated.
In addition, for the whole production process, the method disclosed by the embodiment of the invention can enable the estimated cycle time of each process step to simultaneously consider the standard cycle time and the historical cycle time, so that the number of operation batches (Lot) of one process equipment in a certain time can be accurately estimated. For example, referring to fig. 4, when a device a passes a first time (the first time includes 5 standard cycle times (i.e., 5 STDs)) corresponding to the device, it estimates that the device a has passed 5 lots of operation according to the conventional static simulation method, and it estimates that the device a has passed 4.5 lots of operation according to the method of the present disclosure (the 5 th lot has not been completed, but has been half-way, and is recorded as 0.5 lot).
In addition, for the whole production process, the estimated cycle time of each process step can simultaneously consider the standard cycle time and the historical cycle time, so that the number of the process steps (step) passed by a batch (Lot) in a certain time can be accurately estimated. For example, referring to fig. 5, when LotA passes through the second time (the second time includes 3 standard cycle times corresponding to 3 consecutive different process steps), according to the conventional static simulation method, it is estimated that LotA passes through 3 process steps, but according to the method of the embodiment of the present disclosure, it is estimated that LotA only passes through 2.5 process steps within the time (the 3 rd process step is not completed, but only half of the process is performed, and it is recorded as 0.5 process steps).
Here, it is noted that fig. 2, 3, 4 and 5 are only schematic illustrations for making the technical effects of the embodiments of the present disclosure more vivid, but the illustrations do not limit the present disclosure.
In one embodiment, step S300 includes, including:
step S310, obtaining a gradual change function related to a time variable, wherein when the time variable is sequentially valued within a first preset time, the value of the gradual change function is gradually changed from 1 to 0 or gradually changed from 0 to 1;
step S320, obtaining an estimated cycle time of the target process step within a first preset time according to the historical cycle time, the standard cycle time and the gradual change function.
In step S310, the fade function is a function of a time variable, and the value of the fade function is changed from 1 to 0 or from 0 to 1 within a first preset time. The gradual change function is obtained through new creation, and may also be selected from a plurality of established standby functions, which is not limited herein.
Specifically, it may be set that, when the time variables take values sequentially within a first preset time, the value of the gradual change function smoothly changes between 0 and 1.
In step S320, a calculation expression of the estimated cycle time may be constructed according to the historical cycle time, the standard cycle time, and the gradual change function, so as to obtain the estimated cycle time of the target process step within the first preset time.
As an example, according to the historical cycle time, the standard cycle time and the gradual change function, the operation expression for obtaining the estimated cycle time of the target process step within the first preset time may be:
CT 1 ＝L*y 1 (x)+S*(1-y 1 (x))，
wherein, CT 1 For the estimated cycle time, L is the historical cycle time, S is the standard cycle time, y 1 Is a gradual change function, x is a time variable, and y is a time variable when x is sequentially valued within a first preset time 1 The value of (c) is gradually changed from 1 to 0.
Specifically, the first preset time may be 24 hours.
At this time, the operation expression of the gradation function may be:
y 1 (x)＝(cos((3.14159265/24)*x)+1)/2。
meanwhile, when the first preset time is 24 hours, x may be from 0 to 24.
When x is equal to 0, the number of x,
y 1 (x)＝(cos((3.14159265/24)*0)+1)/2＝(cos(0)+1)/2＝(1+1)/2＝1；
when x is equal to 24, the number of x,
y 1 (x)＝(cos((3.14159265/24)*24)+1)/2＝(cos(3.14159265)+1)/2＝(-1+1)/2＝0。
at this time, the gradation function y 1 (x) Can be seen in fig. 6.
As another example: the operation expression for obtaining the estimated cycle time of the target process step within the first preset time according to the historical cycle time, the standard cycle time and the gradual change function may be:
CT 1 ＝L*(1-y 2 (x))+S*y 2 (x)，
wherein, CT 1 For the estimated cycle time, L is the historical cycle time, S is the standard cycle time, y 2 Is a gradual change function, x is a time variable, and y is a time variable when x is sequentially valued within a first preset time 2 The value of (c) is gradually changed from 0 to 1.
Specifically, the first preset time may be 24 hours.
At this time, the operation expression of the gradation function may be:
y 2 (x)＝(sin(3.14159265*(x/24-1/2))+1)/2。
meanwhile, when the first preset time is 24 hours, x may be from 0 to 24.
When x is equal to 0, the number of x,
y 2 (x)＝(sin(3.14159265*(x/24-1/2))+1)/2＝(sin(-3.14159265/2)+1)/2＝(-1+1)/2＝0；
when x is equal to 24, the number of x,
y 2 (x)＝(sin(3.14159265*(x/24-1/2))+1)/2＝(sin(3.14159265/2)+1)/2＝(1+1)/2＝1。
in the above example, the gradual change function is constructed by a trigonometric function, so that when the time variable takes values in sequence within the first preset time, the value of the gradual change function gradually changes from 1 to 0 or gradually changes from 0 to 1. Of course, the tapering function may have other forms, which are not limited to this.
In this embodiment, the time variable information may be converted by a gradual change function, so as to conveniently obtain an estimated cycle time having a start time identical to the historical cycle time and an end time identical to the standard cycle time.
In one embodiment, after step S300, the method further includes:
in step S400, the historical cycle time is refreshed.
And step S500, updating the estimated cycle time according to the refreshed historical cycle time.
And refreshing the historical period time, namely acquiring the latest historical period time before the refreshing operation so as to replace the original historical period time.
The historical cycle time is refreshed, so that the historical cycle time can be dynamically changed, and the estimated cycle time can be dynamically changed. The times can be estimated more accurately under the condition of estimating and operating simultaneously.
In one embodiment, the historical cycle time is refreshed according to a preset frequency.
The preset frequency can be set according to actual specific requirements. As an example, the preset frequency may be refreshed once per hour.
Specifically, when the estimated cycle time of the target process step within the first preset time (e.g., within 24 hours) is obtained, a historical cycle time may be obtained at the beginning, and then the latest historical cycle time is calculated every hour according to the latest operation condition of the equipment, so as to refresh the historical cycle time, thereby updating the estimated cycle time with a frequency of once per hour within the first preset time.
In this embodiment, the estimated cycle time within the first preset time may be refreshed in time according to the device operation conditions at each time interval within the first preset time.
In one embodiment, step S400 may include:
step S410, acquiring the running time of each batch which has undergone the target process step within a second preset time before the refreshing time;
in step S420, the historical cycle time is refreshed according to the running time of each batch that has undergone the target process step within a second preset time before the refresh time.
In step S410, the second preset time may be set according to actual conditions. The run time of each lot that has gone through the target process step, i.e., the actual CT time of each lot of chip material that has entered into the target process step for processing. It will be appreciated that the chip material may now be processed in batches.
In step S420, a mean value or a median value of the operation times of the respective batches having undergone the target process step within the second preset time may be calculated and used as a new historical cycle time for refreshing.
In one embodiment, step 200 may comprise:
in step S210, the running time of each batch that has undergone the target process step within a second preset time before the simulation time is obtained.
In step S220, the running time of each batch that has undergone the target process step within the second preset time before the simulation time is obtained.
At this time, the process of acquiring the history cycle time in step 200 is similar to the process of refreshing the history cycle time in step S400, whereby the simulation program complexity can be simplified.
Of course, in some embodiments, the historical cycle times may not be refreshed. Alternatively, the "preset time" in the process of acquiring the history period time in step 200 and the process of refreshing the history period time in step S400 may be different, and there is no limitation here.
It should be understood that, although the steps in the flowchart of fig. 1 are shown in order as indicated by the arrows, the steps are not necessarily performed in order as indicated by the arrows. The steps are not performed in a strict order unless explicitly stated herein, and may be performed in other orders. Moreover, at least a portion of the steps in fig. 1 may include multiple steps or multiple stages, which are not necessarily performed at the same time, but may be performed at different times, and the order of performing the steps or stages is not necessarily sequential, but may be performed alternately or in alternation with other steps or at least a portion of the steps or stages in other steps.
In an embodiment, referring to fig. 7, a static simulation system for a semiconductor process cycle is further provided, including: a first obtaining module 100, a second obtaining module 200, and a predicting module 300, wherein:
the first acquisition module 100 is used to establish a standard cycle time for a target process step;
the second obtaining module 200 is configured to obtain a historical cycle time of the target process step;
the estimation module 300 is configured to obtain an estimated cycle time of the target process step within a first preset time according to the historical cycle time, the standard cycle time, and the time variable, where a start segment of the estimated cycle time at the preset time is the same as the historical cycle time, and an end segment of the estimated cycle time at the preset time is the same as the standard cycle time.
In one embodiment, referring to fig. 8, the estimation module 300 includes an obtaining unit 310 and an estimation unit 320.
The function unit 310 is configured to obtain a gradual change function related to a time variable, where when the time variable takes values sequentially within a first preset time, a value of the gradual change function gradually changes from 1 to 0 or gradually changes from 0 to 1.
The estimation unit 320 is configured to obtain an estimated cycle time of the target process step within a first preset time according to the historical cycle time, the standard cycle time, and the gradual change function.
In one embodiment, the second obtaining module 200 is further configured to refresh the historical cycle time. The estimation module 300 is further configured to update the estimated cycle time according to the refreshed historical cycle time.
In one embodiment, the second obtaining module 200 refreshes the historical cycle time according to a preset frequency.
In one embodiment, the second obtaining module 200 is configured to obtain the running time of each lot that has undergone the target process step within a second preset time before the refresh time, and refresh the historical cycle time according to the running time of each lot that has undergone the target process step within the second preset time before the refresh time.
In one embodiment, the second obtaining module 200 is configured to obtain the running time of each batch that has undergone the target process step within a second preset time before the simulation time, and obtain the historical period time according to the running time of each batch that has undergone the target process step within the second preset time before the simulation time.
For the specific definition of the static simulation system of the semiconductor process period, reference may be made to the above definition of the static simulation method of the semiconductor process period, and details are not described herein again. The modules in the static simulation system of the semiconductor process cycle can be wholly or partially realized by software, hardware and a combination thereof. The modules can be embedded in a hardware form or independent from a processor in the computer device, and can also be stored in a memory in the computer device in a software form, so that the processor can call and execute operations corresponding to the modules. It should be noted that, the division of the modules in the embodiments of the present disclosure is illustrative, and is only one division of logic functions, and there may be another division in actual implementation.
In one embodiment, a computer device is provided, comprising a memory and a processor, the memory having a computer program stored therein, the processor implementing the following steps when executing the computer program:
step S100, establishing standard cycle time of a target process step;
step S200, acquiring historical cycle time of a target process step;
step S300, acquiring the estimated cycle time of the target process step within the first preset time according to the historical cycle time, the standard cycle time and the time variable, wherein the estimated cycle time is the same as the historical cycle time at the starting moment of the first preset time, and the estimated cycle time is the same as the standard cycle time at the ending moment of the first preset time.
In one embodiment, the processor, when executing the computer program, further performs the steps of:
acquiring a gradual change function related to a time variable, wherein when the time variable is sequentially valued within a first preset time, the value of the gradual change function is gradually changed from 1 to 0 or from 0 to 1; and acquiring the estimated cycle time of the target process step within the first preset time according to the historical cycle time, the standard cycle time and the gradual change function.
In one embodiment, the processor, when executing the computer program, further performs the steps of:
refreshing the historical cycle time; and updating the estimated cycle time according to the refreshed historical cycle time.
In one embodiment, the processor, when executing the computer program, further performs the steps of:
and refreshing the historical cycle time according to the preset frequency.
In one embodiment, the processor, when executing the computer program, further performs the steps of:
acquiring the running time of each batch which has undergone the target process step within a second preset time before the refreshing time; and refreshing the historical cycle time according to the running time of each batch which has undergone the target process step within a second preset time before the refreshing time.
In one embodiment, the processor, when executing the computer program, further performs the steps of:
acquiring the running time of each batch which has undergone the target process step within a second preset time before the simulation time;
and acquiring the historical cycle time according to the running time of each batch which has undergone the target process step within a second preset time before the simulation time.
In one embodiment, a computer-readable storage medium is provided, having stored thereon a computer program which, when executed by a processor, performs the steps of:
step S100, establishing standard cycle time of a target process step;
step S200, acquiring historical cycle time of a target process step;
step S300, according to the historical period time, the standard period time and the time variable, acquiring the estimated period time of the target process step within the first preset time, wherein the estimated period time is the same as the historical period time at the starting moment of the first preset time, and the estimated period time is the same as the standard period time at the ending moment of the first preset time.
In one embodiment, the computer program when executed by the processor further performs the steps of:
acquiring a gradual change function related to a time variable, wherein when the time variable is sequentially valued within a first preset time, the value of the gradual change function is gradually changed from 1 to 0 or from 0 to 1; and acquiring the estimated cycle time of the target process step within the first preset time according to the historical cycle time, the standard cycle time and the gradual change function.
In one embodiment, the computer program when executed by the processor further performs the steps of:
refreshing the historical cycle time; and updating the estimated cycle time according to the refreshed historical cycle time.
In one embodiment, the computer program when executed by the processor further performs the steps of:
and refreshing the historical cycle time according to the preset frequency.
In one embodiment, the computer program when executed by the processor further performs the steps of:
acquiring the running time of each batch which has undergone the target process step within a second preset time before the refreshing time; and refreshing the historical cycle time according to the running time of each batch which has undergone the target process step within a second preset time before the refreshing time.
In one embodiment, the computer program when executed by the processor further performs the steps of:
acquiring the running time of each batch which has undergone the target process step within a second preset time before the simulation time;
and acquiring historical cycle time according to the running time of each batch which has gone through the target process step within a second preset time before the simulation time.
It will be understood by those skilled in the art that all or part of the processes of the methods of the embodiments described above can be implemented by hardware instructions of a computer program, which can be stored in a non-volatile computer-readable storage medium, and when executed, can include the processes of the embodiments of the methods described above. Any reference to memory, storage, database or other medium used in embodiments provided by the present disclosure may include at least one of non-volatile and volatile memory. Non-volatile Memory may include Read-Only Memory (ROM), magnetic tape, floppy disk, flash Memory, optical Memory, or the like. Volatile Memory can include Random Access Memory (RAM) or external cache Memory. By way of illustration and not limitation, RAM can take many forms, such as Static Random Access Memory (SRAM) or Dynamic Random Access Memory (DRAM), for example.
In the description herein, references to the description of "one embodiment," "some embodiments," etc., mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the disclosure. In this specification, a schematic description of the above terminology may not necessarily refer to the same embodiment or example.
The technical features of the above embodiments can be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the above embodiments are not described, but should be considered as the scope of the present specification as long as there is no contradiction between the combinations of the technical features.
The above-mentioned embodiments only express several embodiments of the present disclosure, and the description thereof is more specific and detailed, but not construed as limiting the scope of the invention. It should be noted that, for those skilled in the art, various changes and modifications can be made without departing from the concept of the present disclosure, and these changes and modifications are all within the scope of the present disclosure. Therefore, the protection scope of the present disclosure should be subject to the appended claims.

Claims (15)

1. A static simulation method of a semiconductor process cycle is characterized by comprising the following steps:
acquiring standard cycle time of a target process step;
acquiring historical cycle time of a target process step;
and acquiring the estimated cycle time of the target process step within a first preset time according to the historical cycle time, the standard cycle time and a time variable, wherein the estimated cycle time is the same as the historical cycle time at the starting time of the first preset time, and the estimated cycle time is the same as the standard cycle time at the ending time of the first preset time.
2. The static simulation method of claim 1, wherein the obtaining an estimated cycle time of the target process step within a first preset time according to the historical cycle time, the standard cycle time and a time variable comprises:
acquiring a gradual change function related to a time variable, wherein when the time variable is sequentially valued within the first preset time, the value of the gradual change function is gradually changed from 1 to 0 or gradually changed from 0 to 1;
and acquiring the estimated cycle time of the target process step within a first preset time according to the historical cycle time, the standard cycle time and the gradual change function.
3. The static simulation method of claim 1 or 2, wherein the step of obtaining the target process after the estimated cycle time within the first predetermined time further comprises:
refreshing the historical cycle time;
and updating the estimated cycle time according to the refreshed historical cycle time.
4. The static simulation method of claim 3, wherein the historical cycle time is refreshed according to a preset frequency.
5. The static simulation method of claim 4, wherein the preset frequency is refreshed once per hour.
6. The static simulation method of claim 3, wherein the refreshing the historical cycle time comprises:
acquiring the running time of each batch which has undergone the target process step within a second preset time before the refreshing time;
and refreshing the historical cycle time according to the running time of each batch which has gone through the target process step within a second preset time before the refreshing time.
7. The static simulation method of claim 1 or 6, wherein the obtaining the historical cycle time of the target process step comprises:
acquiring the running time of each batch which has undergone the target process step within a second preset time before the simulation time;
and acquiring the historical cycle time according to the running time of each batch which has undergone the target process step within a second preset time before the simulation time.
8. The static simulation method of claim 2, wherein the value of the ramp function is smoothly ramped between 0 and 1 when the time variables take values sequentially within the first preset time.
9. The static simulation method of claim 2, wherein the operation expression for obtaining the estimated cycle time of the target process step within the first preset time according to the historical cycle time, the standard cycle time and the gradual change function is as follows:
CT 1 ＝L*y 1 (x)+S*(1-y 1 (x))，
wherein, CT 1 For the estimated cycle time, L is the historical cycle time, S is the standard cycle time, y 1 Is a gradual change function, x is a time variable, and y is a time variable when x is sequentially valued within the first preset time 1 The value of (c) is gradually changed from 1 to 0.
10. The static simulation method of claim 9, wherein the first predetermined time is 24 hours.
11. The static simulation method of claim 10, wherein the operation expression of the gradual change function is:
y 1 (x)＝(cos((3.14159265/24)*x)+1)/2。
12. the static simulation method of claim 2, wherein the operation expression for obtaining the estimated cycle time of the target process step within the first preset time according to the historical cycle time, the standard cycle time and the gradual change function is as follows:
CT 1 ＝L*(1-y 2 (x))+S*y 2 (x)，
wherein, CT 1 For the estimated cycle time, L is the historical cycle time, S is the standard cycle time, y 2 Is a gradual change function, x is a time variable, and y is a time variable when x is sequentially valued within the first preset time 2 The value of (c) is gradually changed from 0 to 1.
13. A system for static simulation of a semiconductor process cycle, comprising:
the first acquisition module is used for establishing standard cycle time of a target process step;
the second acquisition module is used for acquiring the historical cycle time of the target process step;
and the estimation module is used for acquiring the estimation cycle time of the target process step within first preset time according to the historical cycle time, the standard cycle time and the time variable, wherein the estimation cycle time is the same as the historical cycle time in the starting section of the preset time, and the estimation cycle time is the same as the standard cycle time in the ending section of the preset time.
14. A computer device comprising a memory and a processor, the memory storing a computer program, characterized in that the processor, when executing the computer program, implements the steps of the method of any of claims 1 to 12.
15. A computer-readable storage medium, on which a computer program is stored, which, when being executed by a processor, carries out the steps of the method of any one of claims 1 to 12.
CN202210467484.5A 2022-04-29 2022-04-29 Static simulation method, system and computer equipment for semiconductor process cycle Pending CN115062568A (en)

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