CN117471504B - GNSS baseband chip verification method, electronic equipment and medium - Google Patents
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Abstract
The invention relates to a GNSS baseband chip verification method, electronic equipment and a medium, which comprise the steps of S1, acquiring a baseband parameter configuration file, initializing i=1 and executing S2; s2, configuring the operation parameters of the algorithm model C in the ith time block; step S3, inputting intermediate frequency data of the ith time block into a C algorithm model, obtaining corresponding time nodes, register configuration information corresponding to each time node and output information; step S4, judging whether i is equal to M, if so, setting i=1, executing S5, otherwise, setting i=i+1, and returning to S2; s5, configuring an RTL logic model, processing intermediate frequency data, and obtaining corresponding output information; s6, consistency comparison is carried out; and S7, judging whether i is equal to M, if so, outputting a result, otherwise, setting i=i+1, and returning to S5. The invention improves the accuracy and the reliability of GNSS baseband chip verification.
Description
Technical Field
The present invention relates to the field of chip technologies, and in particular, to a GNSS baseband chip verification method, an electronic device, and a medium.
Background
A global satellite navigation system (Global Navigation SATELLITE SYSTEM, abbreviated as GNSS) baseband chip refers to a chip for implementing the acquisition and tracking process of received satellite signals. The conventional chip verification process cannot well design various satellite signal scenes to verify the GNSS baseband chip, so that the problems of function deficiency, substandard performance index and the like occur after the corresponding register transmission level (REGISTER TRANSFER LEVEL, RTL for short) logic codes of the GNSS baseband chip are converted into the chip, the accuracy and the reliability of GNSS baseband chip verification are low, and the verification period of the GNSS baseband chip is prolonged. Therefore, how to provide a verification method suitable for the GNSS baseband chip, improve the accuracy and reliability of the GNSS baseband chip verification, shorten the verification period of the GNSS baseband chip, and become a technical problem to be solved.
Disclosure of Invention
The invention aims to provide a GNSS baseband chip verification method, electronic equipment and medium, which improve the accuracy and reliability of GNSS baseband chip verification and shorten the verification period of the GNSS baseband chip.
According to a first aspect of the present invention, there is provided a GNSS baseband chip verification method, including:
Step S1, acquiring a baseband parameter configuration file, wherein the baseband parameter configuration file is configured with operation parameters corresponding to continuous M time blocks, M is the total number of the corresponding time blocks in the baseband parameter configuration file, the large length of each time block is T, i=1 is initialized, and step S2 is executed;
S2, configuring operation parameters corresponding to an ith time block of a C algorithm model based on the baseband parameter configuration file, wherein the C algorithm model is a model of a GNSS baseband chip function realized based on a C language;
Step S3, inputting intermediate frequency data corresponding to the ith time block into a C algorithm model, wherein the C algorithm model operates and processes the intermediate frequency data corresponding to the ith time block based on the operation parameters corresponding to the ith time block, and obtains a time node corresponding to the ith time block, register configuration information corresponding to each time node and output information;
step S4, judging whether i is equal to M, if so, setting i=1, executing step S5, otherwise, setting i=i+1, and returning to executing step S2;
S5, configuring an RTL logic model based on a time node corresponding to an ith time block and register configuration information corresponding to each time node, enabling the RTL logic model to process intermediate frequency data corresponding to the ith time block, and obtaining output information corresponding to the ith time block, wherein the RTL logic model is a model of a GNSS baseband chip function realized based on an RTL language;
s6, carrying out consistency comparison on the output information corresponding to the C algorithm model corresponding to the ith time block and the output information corresponding to the RTL logic model to obtain a consistency comparison result corresponding to the ith time block;
and S7, judging whether i is equal to M, if so, outputting consistency comparison results corresponding to the M time blocks, otherwise, setting i=i+1, and returning to the step S5.
According to a second aspect of the present invention, there is provided an electronic device comprising: at least one processor; and a memory communicatively coupled to the at least one processor; wherein the memory stores instructions executable by the at least one processor, the instructions being arranged to perform the method according to the first aspect of the invention.
According to a third aspect of the present invention there is provided a computer readable storage medium storing computer executable instructions for performing the method of the first aspect of the present invention.
Compared with the prior art, the invention has obvious advantages and beneficial effects. By means of the technical scheme, the GNSS baseband chip verification method, the electronic equipment and the medium provided by the invention can achieve quite technical progress and practicality, have wide industrial utilization value, and have at least the following beneficial effects:
The invention provides a verification method suitable for a GNSS baseband chip, which can realize complete consistency comparison of functions of two models under the condition that a C algorithm model and an RTL logic model are input by the same intermediate frequency, can effectively verify the functional problem of the RTL in advance, reduces the problems of functional deficiency, performance index failure meeting the requirements and the like after the RTL logic is converted into the chip, improves the accuracy and reliability of GNSS baseband chip verification, shortens the verification period of the GNSS baseband chip, and becomes a technical problem to be solved urgently.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for the description of the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a flowchart of a method for verifying a GNSS baseband chip according to an embodiment of the present invention.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to fall within the scope of the invention.
The embodiment of the invention provides a GNSS baseband chip verification method, which comprises the following steps as shown in fig. 1:
Step S1, a baseband parameter configuration file is obtained, wherein operation parameters corresponding to continuous M time blocks (blocks) are configured in the baseband parameter configuration file, M is the total number of the corresponding time blocks in the baseband parameter configuration file, each time Block is T in large length, i=1 is initialized, and step S2 is executed.
It should be noted that, the baseband parameter configuration file may set the operation parameters corresponding to the continuous M time blocks to the same operation parameters, or may set different operation parameters according to specific application requirements, and specifically set according to a workflow required to be set according to the specific application requirements. But typically each operating parameter will run continuously over multiple time blocks and will not switch frequently.
And step S2, configuring operation parameters corresponding to the ith time block of a C algorithm model based on the baseband parameter configuration file, wherein the C algorithm model is a model of a GNSS baseband chip function realized based on a C language.
Wherein the operation parameters comprise acquisition configuration parameters, tracking configuration parameters, global control parameters and the like. The existing mode of the GNSS baseband chip function realized based on the C language falls into the protection scope of the invention, and is not described herein.
And S3, inputting intermediate frequency data corresponding to the ith time block into a C algorithm model, wherein the C algorithm model operates and processes the intermediate frequency data corresponding to the ith time block based on the operation parameters corresponding to the ith time block, and obtains a time node corresponding to the ith time block and register configuration information corresponding to each time node and output information.
It should be noted that, the present invention firstly configures the C algorithm model, runs the C algorithm model, and obtains the time node corresponding to the ith time block and the register configuration information corresponding to each time node during the process of running the C algorithm model, so as to prepare for the running of the RTL logic model. In addition, output information corresponding to the C algorithm model is required to be obtained, so that preparation is made for consistency comparison with the RTL logic model.
As an embodiment, the register configuration information includes capture register configuration information, trace register configuration information, global control register configuration information, and the like.
As one embodiment, the output information includes processing state information including acquisition state information, current acquisition satellite identification information, tracking state information, current tracking satellite identification information, and the like, and a sequence of processing results.
Step S4, judging whether i is equal to M, if so, setting i=1, executing step S5, otherwise, setting i=i+1, and returning to executing step S2.
It should be noted that, after the execution of the M time blocks in the baseband parameter configuration file is completed, the RTL logic model is operated based on the acquired time node corresponding to each time block and the register configuration information corresponding to each time node.
And S5, configuring an RTL logic model based on a time node corresponding to the ith time block and register configuration information corresponding to each time node, enabling the RTL logic model to process intermediate frequency data corresponding to the ith time block, and obtaining output information corresponding to the ith time block, wherein the RTL logic model is a model of a GNSS baseband chip function realized based on an RTL language.
It should be noted that, as an embodiment, the time node corresponding to the i-th time block obtained in step S3 and the register configuration information corresponding to each time node, and the output information may be stored in a file c.dat, and in step S5, the file c.dat is imported, and the baseband information in the RTL logic model is configured according to Verilog grammar rules based on the imported file c.dat.
And S6, carrying out consistency comparison on the output information corresponding to the C algorithm model corresponding to the ith time block and the output information corresponding to the RTL logic model to obtain a consistency comparison result corresponding to the ith time block.
It should be noted that, in the stage of running the RTL logic model, when each time block is completed during running, output information corresponding to the C algorithm model is compared.
And S7, judging whether i is equal to M, if so, outputting consistency comparison results corresponding to the M time blocks, otherwise, setting i=i+1, and returning to the step S5.
It should be noted that if the comparison results of the M time blocks are all consistent, the C algorithm model and the RTL logic model are determined to be consistent, and verification is passed, otherwise, the C algorithm model and the RTL logic model are determined to be inconsistent, and detailed information of inconsistent comparison can be specifically output, so that a reference is provided for subsequent GNSS baseband chip verification.
As an embodiment, T is greater than or equal to B max/V, wherein B max is the maximum reported data amount of the RTL logic model, and V is the data transmission rate of the RTL logic model, so that the RTL logic model can be ensured to normally operate under any configuration. Preferably, t=b max/V.
As an embodiment, each time block corresponds to a plurality of intermediate frequency data arranged in time sequence, and is related to a sampling rate, and is assumed to be X, and the step S3 includes:
Step S31, dividing the X pieces of intermediate frequency data corresponding to the ith time block into N groups of input sequences { L 1 i,L2 i,…,Ln i,…LN i }, wherein L n i is the nth group of input sequences corresponding to the ith time block, and the value range of N is 1 to N. x=t/W, W is the intermediate frequency data sampling rate, and the input time node corresponding to the first intermediate frequency data in L n i is T n i. When N < N is 1-1, L n i is the sequence formed by [ (N-1) Y+1] to N Y medium frequency data corresponding to the ith time block, Wherein/>Representing a rounding down. When n=n, L n i is the sequence of [ (N-1) ×y+1] to the xth intermediate frequency data of the ith time block pair.
Step S32, starting from time t n i, sequentially inputting intermediate frequency data corresponding to L n i into the C algorithm model, and recording register configuration information corresponding to time t n i and time t n i.
And S32, when the ith time block is finished, acquiring output information corresponding to the ith time block.
It should be noted that, in the operation of each time block, a plurality of processing results may be generated, or a plurality of processing states may be corresponding to each other, and buffering may be performed sequentially according to time, when the operation of the time block is finished, all the processing results are sequentially output, and all the processing state information is also sequentially output.
As an embodiment, the step S5 includes:
step S51 is performed by setting n=1, and step S52 is performed.
And step S52, at the time t n i, configuring the RTL logic model according to the register configuration information corresponding to the time t n i.
It can be understood that the invention configures the RTL logic model based on the configuration information of each time node of the C algorithm model, thereby realizing the verification of the RTL logic model.
Step S53, the intermediate frequency data in L n i are sequentially input into an RTL logic model from the time t n i, and the RTL logic model is enabled to process the intermediate frequency data in L n i.
Step S54, determining whether N is equal to N, if yes, obtaining output information corresponding to the ith time block when the ith time block ends, otherwise, setting n=n+1, and returning to execute step S52.
By the processing of step S53 to step S54, it is possible to keep the input of the RTL logical model and the C algorithm model consistent.
As an embodiment, the step S6 includes:
step S61, comparing the processing state information corresponding to the C algorithm model corresponding to the ith time block with the processing state information corresponding to the RTL logic model, if the processing state information is consistent with the processing state information, directly executing step S62, otherwise, generating state inconsistent information, wherein the state inconsistent information comprises the state information with inconsistent comparison, and then executing step S62.
Step S62, comparing the processing result sequence corresponding to the C algorithm model corresponding to the ith time block with the processing result sequence corresponding to the RTL logic model, if the processing result sequences are consistent in comparison and the state information is consistent in comparison, executing step S63, otherwise, executing step S64.
When comparing the processing result sequences, each item in the processing result sequences is compared respectively, and if only one inconsistent sequence item exists, the processing result sequences are determined to be inconsistent in comparison.
And step S63, determining that the C algorithm model corresponding to the ith time block is consistent with the RTL logic model, and executing step S7.
And S64, determining that the C algorithm model corresponding to the ith time block is inconsistent with the RTL logic model, and if the sequence comparison of the processing results is inconsistent, generating sequence comparison inconsistent information, wherein the sequence comparison inconsistent information comprises sequence items which are inconsistent in sequence.
It should be noted that, only when the processing state information corresponding to the ith time block and the processing result sequence are completely consistent, it can be determined that the C algorithm model corresponding to the ith time block and the RTL logic model are consistent, and if there is a place of inconsistency, it is determined that the C algorithm model corresponding to the ith time block and the RTL logic model are inconsistent. The embodiment of the invention can not only judge whether the C algorithm model corresponding to the ith time block is consistent with the RTL logic model, but also can clearly determine the specific information which is not necessarily required under the condition of inconsistent.
In step S7, it is to be noted that only when the consistency comparison results corresponding to the M time blocks are all consistent, it is finally determined that the C algorithm model and the RTL logic model are consistent. Otherwise, the inconsistent information corresponding to all the time blocks with inconsistent conditions can be accurately presented.
The embodiment of the invention provides a verification method suitable for a GNSS baseband chip, which can realize complete consistency comparison of functions of two models under the condition that a C algorithm model and an RTL logic model are input by the same intermediate frequency, can effectively verify the functional problem of the RTL in advance, reduces the problems of functional deficiency, performance index failure meeting the requirements and the like after the RTL logic is converted into the chip, improves the accuracy and reliability of GNSS baseband chip verification, shortens the verification period of the GNSS baseband chip, and becomes a technical problem to be solved urgently.
It should be noted that some exemplary embodiments are described as a process or a method depicted as a flowchart. Although a flowchart depicts steps as a sequential process, many of the steps may be implemented in parallel, concurrently, or with other steps. Furthermore, the order of the steps may be rearranged. The process may be terminated when its operations are completed, but may have additional steps not included in the figures. The processes may correspond to methods, functions, procedures, subroutines, and the like.
The embodiment of the invention also provides electronic equipment, which comprises: at least one processor; and a memory communicatively coupled to the at least one processor; wherein the memory stores instructions executable by the at least one processor, the instructions being configured to perform the methods of embodiments of the present invention.
The embodiment of the invention also provides a computer readable storage medium, which stores computer executable instructions for executing the method according to the embodiment of the invention.
The present invention is not limited to the above-mentioned embodiments, but is intended to be limited to the following embodiments, and any modifications, equivalents and modifications can be made to the above-mentioned embodiments without departing from the scope of the invention.
Claims (10)
1. A method for verifying a GNSS baseband chip, comprising:
Step S1, acquiring a baseband parameter configuration file, wherein the baseband parameter configuration file is configured with operation parameters corresponding to continuous M time blocks, M is the total number of the corresponding time blocks in the baseband parameter configuration file, the large length of each time block is T, i=1 is initialized, and step S2 is executed;
S2, configuring operation parameters corresponding to an ith time block of a C algorithm model based on the baseband parameter configuration file, wherein the C algorithm model is a model of a GNSS baseband chip function realized based on a C language;
Step S3, inputting intermediate frequency data corresponding to the ith time block into a C algorithm model, wherein the C algorithm model operates and processes the intermediate frequency data corresponding to the ith time block based on the operation parameters corresponding to the ith time block, and obtains a time node corresponding to the ith time block, register configuration information corresponding to each time node and output information;
step S4, judging whether i is equal to M, if so, setting i=1, executing step S5, otherwise, setting i=i+1, and returning to executing step S2;
S5, configuring an RTL logic model based on a time node corresponding to an ith time block and register configuration information corresponding to each time node, enabling the RTL logic model to process intermediate frequency data corresponding to the ith time block, and obtaining output information corresponding to the ith time block, wherein the RTL logic model is a model of a GNSS baseband chip function realized based on an RTL language;
s6, carrying out consistency comparison on the output information corresponding to the C algorithm model corresponding to the ith time block and the output information corresponding to the RTL logic model to obtain a consistency comparison result corresponding to the ith time block;
and S7, judging whether i is equal to M, if so, outputting consistency comparison results corresponding to the M time blocks, otherwise, setting i=i+1, and returning to the step S5.
2. The method of claim 1, wherein the step of determining the position of the substrate comprises,
The operating parameters include acquisition configuration parameters, tracking configuration parameters, and global control parameters.
3. The method of claim 1, wherein the step of determining the position of the substrate comprises,
T is greater than or equal to B max/V, wherein B max is the maximum reported data amount of the RTL logic model, and V is the data transmission rate of the RTL logic model.
4. The method of claim 1, wherein the step of determining the position of the substrate comprises,
The step S3 includes:
Step S31, dividing the X intermediate frequency data corresponding to the ith time block into N groups of input sequences { L 1 i,L2 i,…,Ln i,…LN i }, wherein L n i is the nth group of input sequences corresponding to the ith time block, and the value range of N is 1 to N;
x=t/W, W is the intermediate frequency data sampling rate, and the input time node corresponding to the first intermediate frequency data in L n i is T n i;
When N < N is 1-1, L n i is the sequence formed by [ (N-1) Y+1] to N Y medium frequency data corresponding to the ith time block,
When n=n, L n i is the sequence of [ (N-1) ×y+1] to the xth intermediate frequency data of the ith time block pair;
Step S32, starting from the time t n i, sequentially inputting intermediate frequency data corresponding to L n i into a C algorithm model, and recording register configuration information corresponding to the time t n i and the time t n i;
and S32, when the ith time block is finished, acquiring output information corresponding to the ith time block.
5. The method of claim 4, wherein the step of determining the position of the first electrode is performed,
The register configuration information includes capture register configuration information, trace register configuration information, and global control register configuration information.
6. The method of claim 4, wherein the step of determining the position of the first electrode is performed,
The step S5 includes:
Step S51, setting n=1, and executing step S52;
Step S52, at the time t n i, configuring an RTL logic model according to the register configuration information corresponding to the time t n i;
Step S53, sequentially inputting intermediate frequency data in L n i into an RTL logic model from the time t n i, and enabling the RTL logic model to process the intermediate frequency data in L n i;
step S54, determining whether N is equal to N, if yes, obtaining output information corresponding to the ith time block when the ith time block ends, otherwise, setting n=n+1, and returning to execute step S52.
7. The method of claim 1, wherein the step of determining the position of the substrate comprises,
The output information includes processing state information including acquisition state information, current acquisition satellite identification information, tracking state information, and current tracking satellite identification information, and a sequence of processing results.
8. The method of claim 7, wherein the step of determining the position of the probe is performed,
The step S6 includes:
Step S61, comparing the processing state information corresponding to the C algorithm model corresponding to the ith time block with the processing state information corresponding to the RTL logic model, if the processing state information is consistent with the processing state information, directly executing the step S62, otherwise, generating state inconsistent information, wherein the state inconsistent information comprises the state information with inconsistent comparison, and then executing the step S62;
Step S62, comparing the processing result sequence corresponding to the C algorithm model corresponding to the ith time block with the processing result sequence corresponding to the RTL logic model, if the processing result sequences are consistent in comparison and the state information is consistent in comparison, executing step S63, otherwise, executing step S64;
step S63, determining that a C algorithm model corresponding to the ith time block is consistent with the RTL logic model, and executing step S7;
and S64, determining that the C algorithm model corresponding to the ith time block is inconsistent with the RTL logic model, and if the sequence comparison of the processing results is inconsistent, generating sequence comparison inconsistent information, wherein the sequence comparison inconsistent information comprises sequence items which are inconsistent in sequence.
9. An electronic device, comprising:
At least one processor;
and a memory communicatively coupled to the at least one processor;
wherein the memory stores instructions executable by the at least one processor, the instructions being arranged to perform the method of any of the preceding claims 1-8.
10. A computer readable storage medium, characterized in that computer executable instructions are stored for performing the method of any of the preceding claims 1-8.
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