CN115051786A - Balance-point-free three-dimensional power system chaotic circuit - Google Patents
Balance-point-free three-dimensional power system chaotic circuit Download PDFInfo
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- CN115051786A CN115051786A CN202210639532.4A CN202210639532A CN115051786A CN 115051786 A CN115051786 A CN 115051786A CN 202210639532 A CN202210639532 A CN 202210639532A CN 115051786 A CN115051786 A CN 115051786A
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- H—ELECTRICITY
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- H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
- H04L9/001—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols using chaotic signals
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- H—ELECTRICITY
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- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L2209/00—Additional information or applications relating to cryptographic mechanisms or cryptographic arrangements for secret or secure communication H04L9/00
- H04L2209/12—Details relating to cryptographic hardware or logic circuitry
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Abstract
The invention provides a balance point-free three-dimensional power system chaotic circuit, which comprises a mathematical model and a simulation realization circuit of a three-dimensional power system, wherein the simulation realization circuit comprises a first channel circuit, a second channel circuit and a third channel circuit, and the output of a reverse phase integrator U1 in the first channel is connected with the first input end and the second input end of a multiplier A2 of the second channel and one end of a resistor R3; the output of the inverse integrator U2 in the second channel is fed back to one of its inputs and the output of the inverse integrator U2 in the second channel is connected to one of the terminals of the resistor R1 in the first channel and to the first and second inputs of the multiplier a4 in the third channel. The attractor phase diagram of the parameters required by the output signals of the three channels can be directly displayed on the oscilloscope, and the method has the advantage of convenient observation; the resistors, the capacitors, the operational amplifiers and the multipliers required by the first channel, the second channel and the third channel belong to common elements, and are easily purchased in the market, so the method is easy to realize.
Description
Technical Field
The invention relates to the technical field of chaotic signal generators and secret communication, in particular to a balance point-free three-dimensional power system chaotic circuit.
Background
Chaos is a ubiquitous mode of physical phenomena, but due to its special properties and complex dynamic behaviors, it has not attracted sufficient attention until nonlinear science is rapidly developed. The chaotic time sequence has the characteristics of high complexity, non-periodicity, inherent randomness, continuous broadband spectrum and the like, so that the chaotic time sequence has wide application in the fields of information security, secret communication and the like. The chaotic system is extremely sensitive to initial conditions, and for two identical chaotic systems, if the chaotic systems are in slightly different initial states, the chaotic systems can quickly change into completely different states. Most classic chaotic circuits can generate single-scroll, double-scroll or double-wing attractors, the structures are similar, but the essential requirements of the chaotic system are random, so that the generation of a new attractor phase diagram structure is a necessary condition for the construction of a new power system, and therefore, the three-dimensional power system chaotic circuit without balance points is provided.
Disclosure of Invention
In view of the above, embodiments of the present invention are intended to provide a balance-point-free three-dimensional power system chaotic circuit, so as to solve or alleviate the technical problems in the prior art, and to provide at least one useful choice.
The technical scheme of the embodiment of the invention is realized as follows: a balance point-free three-dimensional power system chaotic circuit comprises a mathematical model and a simulation realization circuit of a three-dimensional power system:
the mathematical model is constructed according to the following equation:
wherein x, y and z are system state variables, and a, b, c and d are system parameters;
the analog implementation circuit comprises a first channel circuit, a second channel circuit and a third channel circuit, wherein the output of an inverting integrator U1 in the first channel is connected with the first input end and the second input end of a multiplier A2 of the second channel and one end of a resistor R3;
the output of the inverse integrator U2 in the second channel is fed back to one of its inputs, and the output of the inverse integrator U2 in the second channel is connected to one end of the resistor R1 in the first channel and to the first and second inputs of the multiplier a4 in the third channel;
the output of the inverse integrator U3 in the third channel is connected to the first input of the multiplier a1 in the second channel.
Further preferred is: the circuit of the first channel comprises an inverting integrator U1, wherein 2 pins of the inverting integrator U1 are respectively connected with one ends of a capacitor C1, a resistor R1 and a resistor R2;
the other end of the resistor R2 is connected with a positive input voltage V1;
the 3 pin of the inverting integrator U1 is connected with the other end of the capacitor C1;
the 4 pins of the inverting integrator U1 are connected with a positive voltage VCC;
the 5 pin of the inverting integrator U1 is connected with a negative voltage VEE;
the output of the inverting integrator U2 of the first channel is signal-x.
Further preferred is: the second channel comprises a multiplier A1, a multiplier A2 and a multiplier A3, the multiplier A1 is connected with one end of a resistor R5, the other end of the resistor R5 is connected with a pin 2 of an inverse integrator U2, the pin 2 of the inverse integrator U2 is connected with one end of a capacitor C2, the other end of the capacitor C2 is connected with a pin 3 of the inverse integrator U2, and the pin 2 of the inverse integrator U2 is connected with one end of the resistor R6.
Further preferred is: the output end of the multiplier A2 is connected to one input end of the multiplier A3, the output end of the multiplier A3 is connected to the other end of the resistor R6, and the other input end of the multiplier A3 is connected to the 3 pin of the inverter U4.
Further preferred is: a pin 3 of the inverter U4 is connected with one end of a resistor R4, the other end of the resistor R4 is connected with a pin 2 of the inverter U3, and a pin 2 of the inverter U4 is connected with one end of a resistor R3; the 4 pins of the inverter U3 and the 4 pins of the inverting integrator U2 are connected with a positive voltage VCC; the pin 5 of the inverter U4 and the pin 5 of the inverting integrator U2 are connected to a negative voltage VEE; the output of the second channel inverting integrator U2 is signal-y.
Further preferred is: the circuit of the third channel comprises a multiplier A4, wherein the multiplier A4 is connected with a pin 2 of an inverter U5 through a resistor R7, the pin 2 of the inverter U5 is connected with one end of a resistor R8, and the other end of a resistor R8 is connected with a pin 3 of the inverter U5.
Further preferred is: a pin 3 of the inverter U5 is connected with a pin 2 of the inverting integrator U3 through a resistor R9, a pin 2 of the inverting integrator U3 is connected with one end of a resistor R10 and one end of a capacitor C3, and the other end of the capacitor C3 is connected with a pin 3 of the inverting integrator U3; the other end of the resistor R10 is connected with a positive input voltage V2; .
Further preferred is: the pin 4 of the inverter U5 and the pin 4 of the inverting integrator U3 are connected with a positive voltage VCC; pin 5 of the inverter U5 and pin 5 of the inverting integrator U3 are connected to a negative voltage VEE; the output signal of the third channel inverter inverting integrator U3 is-z.
Further preferred is: the inverting integrator U1, the inverting integrator U2, the inverting integrator U3, the inverter U4 and the inverter U5 adopt an operational amplifier 3288 RT.
Further preferred is: the multiplier a1, the multiplier a2 and the multiplier A3 adopt a multiplier AD 633.
Due to the adoption of the technical scheme, the embodiment of the invention has the following advantages:
the attractor phase diagram of the parameters required by the output signals of the three channels can be directly displayed on the oscilloscope, and the method has the advantage of convenient observation;
the resistors, the capacitors, the operational amplifiers and the multipliers required by the first channel, the second channel and the third channel belong to common elements, are easy to purchase in the market and have low price, so the method is easy to realize;
the graphic display of the numerical solution of the differential equation corresponding to the circuits of the first channel, the second channel and the third channel is basically consistent with the real attractor phase diagram, so the method has the advantage of higher reliability.
For the purposes of this description, no limitation is intended in any way. In addition to the illustrative aspects, embodiments, and features described above, further aspects, embodiments, and features of the present invention will be readily apparent by reference to the drawings and following detailed description.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings needed to be used in the embodiments or technical descriptions will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present application, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
FIG. 1 is a circuit diagram of the present invention;
FIG. 2 is a first diagram illustrating the numerical simulation result of the present invention;
FIG. 3 is a diagram illustrating a numerical simulation result according to the present invention;
fig. 4 is a third diagram illustrating the numerical simulation result of the present invention.
Detailed Description
In the following, only certain exemplary embodiments are briefly described. As those skilled in the art will recognize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention. Accordingly, the drawings and description are to be regarded as illustrative in nature, and not as restrictive.
Embodiments of the present invention will be described in detail below with reference to the accompanying drawings.
As shown in fig. 1 to 4, an embodiment of the present invention provides a three-dimensional power system simulation implementation circuit without a balance point, including a first channel circuit, a second channel circuit, and a third channel circuit, where an output of an inverse integrator U1 in the first channel is connected to a first input terminal and a second input terminal of a multiplier a2 in the second channel and one end of a resistor R3; the output of the inverse integrator U2 in the second channel is fed back to one of its inputs, and the output of the inverse integrator U2 in the second channel is connected to one end of the resistor R1 in the first channel and to the first and second inputs of the multiplier a4 in the third channel; the output of the inverse integrator U3 in the third channel is connected to a first input of the multiplier a1 in the second channel.
The circuit of the first channel comprises an inverting integrator U1, wherein 2 pins of the inverting integrator U1 are respectively connected with one ends of a capacitor C1, a resistor R1 and a resistor R2; the other end of the resistor R2 is connected with a positive input voltage V1; the 3 pin of the inverting integrator U1 is connected with the other end of the capacitor C1; the 4 pins of the inverting integrator U1 are connected with a positive voltage VCC; the 5 pin of the inverting integrator U1 is connected with a negative voltage VEE; the output of the inverting integrator U2 of the first channel is signal-x;
the second channel comprises a multiplier A1, a multiplier A2 and a multiplier A3, the multiplier A1 is connected with one end of a resistor R5, the other end of the resistor R5 is connected with a pin 2 of an inverse integrator U2, the pin 2 of the inverse integrator U2 is connected with one end of a capacitor C2, the other end of the capacitor C2 is connected with a pin 3 of the inverse integrator U2, and the pin 2 of the inverse integrator U2 is connected with one end of the resistor R6; the output end of the multiplier A2 is connected with one input end of a multiplier A3, the output end of the multiplier A3 is connected with the other end of a resistor R6, the other input end of the multiplier A3 is connected with a pin 3 of an inverter U4, a pin 3 of the inverter U4 is connected with one end of a resistor R4, the other end of the resistor R4 is connected with a pin 2 of an inverter U3, and a pin 2 of the inverter U4 is connected with one end of a resistor R3; the 4 pins of the inverter U3 and the 4 pins of the inverting integrator U2 are connected with a positive voltage VCC; pin 5 of the inverter U4 and pin 5 of the inverting integrator U2 are connected to a negative voltage VEE; the output of the second channel inverting integrator U2 is signal-y;
the circuit of the third channel comprises a multiplier A4, wherein the multiplier A4 is connected with a pin 2 of an inverter U5 through a resistor R7, the pin 2 of the inverter U5 is connected with one end of a resistor R8, and the other end of the resistor R8 is connected with a pin 3 of the inverter U5; a pin 3 of the inverter U5 is connected with a pin 2 of the inverting integrator U3 through a resistor R9, a pin 2 of the inverting integrator U3 is connected with one end of a resistor R10 and one end of a capacitor C3, and the other end of the capacitor C3 is connected with a pin 3 of the inverting integrator U3; the other end of the resistor R10 is connected with a positive input voltage V2; the 4 pins of the inverter U5 and the 4 pins of the inverting integrator U3 are connected with a positive voltage VCC; the pin 5 of the inverter U5 and the pin 5 of the inverting integrator U3 are connected to a negative voltage VEE; the output signal of the third channel inverter inverting integrator U3 is-z.
In a preferred embodiment, the first channel resistance R1 ═ R2 ═ 10k Ω, and C1 ═ 1 μ F; the second channel resistance R3 ═ R4 ═ 10k Ω, R5 ═ R6 ═ 100k Ω, and C2 ═ 1 μ F; the third channel resistance R7 ═ R8 ═ 10k Ω, R9 ═ R10 ═ 100k Ω, and C3 ═ 1 μ F.
The inverting integrator U1, the inverting integrator U2, the inverting integrator U3, the inverter U4 and the inverter U5 adopt an operational amplifier 3288 RT.
The multiplier a1, the multiplier a2 and the multiplier A3 adopt a multiplier AD 633.
The working principle is as follows: the first path implements-x with inverting integrator U1; the second pass implements yz using multiplier a 1; x is realized by an inverter; xxx is implemented using multiplier a2 and multiplier A3; the third channel implements yy using multiplier a 4; -yy is implemented with inverter U5; -z is implemented with an inverting integrator U3.
A three-dimensional power system without balance points comprises the following dynamic equations:
where x, y, z are system state variables, a, b, c, d are system parameters, and a is 10, b is 10, c is 1, and d is 3.
The self-excited oscillation circuit equation corresponding to the built analog circuit is as follows:
the x, y, z involved are state variables, all realized in the circuit outputs of the first, second and third channels. The numerical simulation results are shown in fig. 2, 3, and 4. The consistency of the circuit simulation result proves the physical realizability of the power system, and has important significance on circuit control and utilization.
The above description is only for the specific embodiment of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art can easily conceive various changes or substitutions within the technical scope of the present invention, and these should be covered by the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the appended claims.
Claims (10)
1. A three-dimensional power system chaotic circuit without balance points comprises a mathematical model and a simulation realization circuit of a three-dimensional power system, and is characterized in that:
the mathematical model is constructed according to the following equation:
wherein x, y and z are system state variables, and a, b, c and d are system parameters;
the analog implementation circuit comprises a first channel circuit, a second channel circuit and a third channel circuit, wherein the output of an inverting integrator U1 in the first channel is connected with the first input end and the second input end of a multiplier A2 of the second channel and one end of a resistor R3;
the output of the inverse integrator U2 in the second channel is fed back to one of its inputs, and the output of the inverse integrator U2 in the second channel is connected to one end of the resistor R1 in the first channel and to the first and second inputs of the multiplier a4 in the third channel;
the output of the inverse integrator U3 in the third channel is connected to a first input of the multiplier a1 in the second channel.
2. The balance-point-free three-dimensional power system chaotic circuit according to claim 1, characterized in that: the circuit of the first channel comprises an inverting integrator U1, wherein 2 pins of the inverting integrator U1 are respectively connected with one ends of a capacitor C1, a resistor R1 and a resistor R2;
the other end of the resistor R2 is connected with a positive input voltage V1;
a pin 3 of the inverting integrator U1 is connected with the other end of the capacitor C1;
the 4 pins of the inverting integrator U1 are connected with a positive voltage VCC;
the 5 pin of the inverting integrator U1 is connected with a negative voltage VEE;
the output of the inverting integrator U2 of the first channel is signal-x.
3. The balance-point-free three-dimensional power system chaotic circuit according to claim 1, characterized in that: the second channel comprises a multiplier A1, a multiplier A2 and a multiplier A3, the multiplier A1 is connected with one end of a resistor R5, the other end of the resistor R5 is connected with a pin 2 of an inverse integrator U2, the pin 2 of the inverse integrator U2 is connected with one end of a capacitor C2, the other end of the capacitor C2 is connected with a pin 3 of the inverse integrator U2, and the pin 2 of the inverse integrator U2 is connected with one end of the resistor R6.
4. The balance-point-free three-dimensional power system chaotic circuit according to claim 3, characterized in that: the output end of the multiplier A2 is connected to one input end of the multiplier A3, the output end of the multiplier A3 is connected to the other end of the resistor R6, and the other input end of the multiplier A3 is connected to the 3 pin of the inverter U4.
5. The balance-point-free three-dimensional power system chaotic circuit according to claim 4, characterized in that: a pin 3 of the inverter U4 is connected with one end of a resistor R4, the other end of the resistor R4 is connected with a pin 2 of the inverter U3, and a pin 2 of the inverter U4 is connected with one end of a resistor R3; the 4 pins of the inverter U3 and the 4 pins of the inverting integrator U2 are connected with a positive voltage VCC; the pin 5 of the inverter U4 and the pin 5 of the inverting integrator U2 are connected to a negative voltage VEE; the output of the second channel inverting integrator U2 is signal-y.
6. The balance-point-free three-dimensional power system chaotic circuit according to claim 1, characterized in that: the circuit of the third channel comprises a multiplier A4, wherein the multiplier A4 is connected with a pin 2 of an inverter U5 through a resistor R7, the pin 2 of the inverter U5 is connected with one end of a resistor R8, and the other end of the resistor R8 is connected with a pin 3 of the inverter U5.
7. The balance-point-free three-dimensional power system chaotic circuit according to claim 6, characterized in that: a pin 3 of the inverter U5 is connected with a pin 2 of the inverse integrator U3 through a resistor R9, a pin 2 of the inverse integrator U3 is connected with one end of a resistor R10 and one end of a capacitor C3, and the other end of the capacitor C3 is connected with a pin 3 of the inverse integrator U3; the other end of the resistor R10 is connected with a positive input voltage V2; .
8. The balance-point-free three-dimensional power system chaotic circuit according to claim 6, characterized in that: the pin 4 of the inverter U5 and the pin 4 of the inverting integrator U3 are connected with a positive voltage VCC; pin 5 of the inverter U5 and pin 5 of the inverting integrator U3 are connected to a negative voltage VEE; the output signal of the third channel inverter inverting integrator U3 is-z.
9. The three-dimensional power system chaotic circuit without the balance point as in claim 1, wherein: the inverting integrator U1, the inverting integrator U2, the inverting integrator U3, the inverter U4 and the inverter U5 adopt an operational amplifier 3288 RT.
10. The three-dimensional power system chaotic circuit without the balance point as in claim 1, wherein: the multiplier a1, the multiplier a2 and the multiplier A3 adopt a multiplier AD 633.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210639532.4A CN115051786A (en) | 2022-06-07 | 2022-06-07 | Balance-point-free three-dimensional power system chaotic circuit |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202210639532.4A CN115051786A (en) | 2022-06-07 | 2022-06-07 | Balance-point-free three-dimensional power system chaotic circuit |
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| CN115051786A true CN115051786A (en) | 2022-09-13 |
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| CN202210639532.4A Withdrawn CN115051786A (en) | 2022-06-07 | 2022-06-07 | Balance-point-free three-dimensional power system chaotic circuit |
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