CN111294197A - Double-vortex memory resistance hyperchaotic signal source circuit - Google Patents

Double-vortex memory resistance hyperchaotic signal source circuit Download PDF

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CN111294197A
CN111294197A CN202010199862.7A CN202010199862A CN111294197A CN 111294197 A CN111294197 A CN 111294197A CN 202010199862 A CN202010199862 A CN 202010199862A CN 111294197 A CN111294197 A CN 111294197A
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赖强
万志强
裴惠琴
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East China Jiaotong University
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    • H04L9/001—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols using chaotic signals
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    • H04—ELECTRIC COMMUNICATION TECHNIQUE
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Abstract

A double-vortex memristor hyperchaotic signal source circuit comprises a first channel, a second channel and a third channel; the three channels consist of an integral summation circuit, an addition circuit, an integral circuit or an inverter circuit; the third channel contains a memristor module M and a sign function module S; after the same ports in the three channels are connected in sequence, the realized signal source circuit can output the hyperchaotic signal. The circuit system of the invention has simple structure and is convenient for theoretical analysis and circuit simulation. As a chaotic signal source generating circuit, the hyperchaotic signal generated by the invention is complex, can enhance the safety when used for secret communication and image encryption, and has great engineering application value.

Description

Double-vortex memory resistance hyperchaotic signal source circuit
Technical Field
The invention relates to a double-vortex memristor hyperchaotic signal source circuit, and belongs to the technical field of memristor chaotic circuits.
Background
In 2000, the research of three-order Jerk system by Sprott has attracted the wide attention of domestic and foreign chaos researchers. The essential condition that an autonomous system can generate chaos is that at least three state variables and a nonlinear term are contained, the Jerk system not only meets the essential condition, but also is a third-order autonomous chaotic system with very simple mathematical form, and the general mathematical form is that
Figure BDA0002418981580000011
Wherein
Figure BDA0002418981580000012
Is the first derivative of position, representing velocity,
Figure BDA0002418981580000013
is the second derivative of position, representing acceleration, the third derivative
Figure BDA0002418981580000014
Referred to as Jerk. In 2006, Sprott et al, in turn, proposed a class of higher-order Jerk systems based on the third-order Jerk system, which is generally mathematically formed as: dnx/dτn＝J(x,dx/dτ,d2x/dτ2,...,dn-1x/dτn-1) The high-order Jerk system has the characteristics of simple equation form, convenient circuit realization and capability of generating single-scroll or double-scroll chaotic attractors.
The high-order Jerk system is widely applied to secure communication based on the characteristic of convenient circuit realization. In the process that the chaotic signal is used for secret communication and image encryption, the more complicated the chaotic attractor is, the higher the application safety of the corresponding chaotic signal is, so that how to generate the more complicated chaotic attractor to improve the safety of the chaotic signal in practical application becomes a research hotspot. The general method is that a memristor is added into a chaotic system by utilizing the nonlinear characteristic of the memristor, so that a corresponding memristor chaotic circuit can generate a more complex chaotic signal.
The memristor is a fourth basic circuit component except for a resistor, a capacitor and an inductor, and is a nonlinear circuit component with a memory function. The theoretical concept of memristors was proposed earlier, but the technological constraints made physical memristors to shape later. Due to the high manufacturing cost of the physical memristor, the memristor cannot be used commercially in a short time, and research on the memristor is mainly focused on research institutes and colleges at present. At present, in engineering application, a memristor simulator is mainly formed by combining an operational amplifier, a resistor, a capacitor, an analog multiplier and the like to replace a physical memristor, the simulator can generate nonlinear characteristics similar to those of the memristor, and important reference values are provided for research on the memristor and modeling simulation of related application circuits.
Disclosure of Invention
The invention aims to provide a double-vortex memristor hyper-chaotic signal source circuit in order to solve the problem of enhancing the safety of chaotic signals when the chaotic signals are used for secret communication and image encryption.
The technical scheme of the invention is that the double-vortex memristor hyperchaotic signal source circuit comprises a first channel, a second channel and a third channel; the three channels consist of an integral summation circuit, an addition circuit, an integral circuit or an inverter circuit; the third channel contains a memristor module M and a sign function module S; after the same ports in the three channels are connected in sequence, the realized signal source circuit can output the hyperchaotic signal.
When the chaotic attractor value generated by the signal source circuit is simulated, obvious double scrolls are formed in the projections of an x-y phase plane, an x-z phase plane and an x-w phase plane.
The first channel is composed of an integral summation circuit and an inversion circuit; the first channel has only one input and one output, the input being the output of the third channel.
Said first channel having an input end "-vw", the input end is connected with a resistor R in series3Rear-access operational amplifier U3Of the inverting input terminal of the operational amplifier U3Across a capacitor C between the inverting input and the output3At this time, the operational amplifier U3Output terminal "vz"; operational amplifier U3The output end of the operational amplifier is connected with a 100k omega resistor in series and then is connected with an operational amplifier Uf3Of the inverting input terminal of the operational amplifier Uf3Is connected across a 100k omega resistor between the inverting input and the output, and the operational amplifier U is connected to the outputf3Output "-vz"; operational amplifier U3And operational amplifier Uf3The non-inverting input of (a) is terminated by "ground".
The second channel is composed of an integral summation circuit and an inversion circuit; the second channel has only one input and one output, the inputs being the outputs of the first channel.
Said second channel having an input end "-vz", the input end is connected with a resistor R in series2Rear-access operational amplifier U2Of the inverting input terminal of the operational amplifier U2Across a capacitor C between the inverting input and the output2At this time, the operational amplifier U2Output terminal "vy"; operational amplifier U2The output end of the operational amplifier is connected with a 100k omega resistor in series and then is connected with an operational amplifier Uf2Of the inverting input terminal of the operational amplifier Uf2Is connected across a 100k omega resistor between the inverting input and the output, and the operational amplifier U is connected to the outputf2Output "-vy"; operational amplifier U2 and operational amplifier Uf2The non-inverting input of (a) is terminated by "ground".
The third channel consists of an addition circuit, an integration circuit and an inverting circuit; the third channel also comprises a memristor module M and a sign function module S; there are six inputs and one output for the third channel; the six inputs include the output of the first channel, the output of the second channel and the output of the third channel, and the inputs also include the output of the operational amplifier in the memristor module M and the corresponding inverted output.
The third channel has six inputs, wherein the input "-vyOperational amplifier U connected behind series memristor module M4The inverting input terminal of (1); input terminal "vxConnecting the sign function module S in series and then connecting the resistor R in series8Rear-access operational amplifier U4The inverting input terminal of (1); input terminal "-vx' series resistance R4Rear-access operational amplifier U4The inverting input terminal of (1); input terminal "-vy' series resistance R5Rear-access operational amplifier U4The inverting input terminal of (1); input terminal "-vz' series resistance R6Rear-access operational amplifier U4The inverting input terminal of (1); input terminal "-vw' series resistance R7Rear-access operational amplifier U4Of the inverting input terminal of the operational amplifier U4Across resistor R between the inverting input terminal and the output terminal9Operational amplifier U4Is connected in series with the output terminal ofResistance R10Rear-access operational amplifier U5Of the inverting input terminal of the operational amplifier U5Across a capacitor C between the inverting input and the output4At this time, the operational amplifier U5Output "vw"; operational amplifier U5The output end is connected in series with a 100k omega resistor connected into an operational amplifier Uf4Of the inverting input terminal of the operational amplifier Uf4Is connected across a 100k omega resistor between the inverting input and the output, and the operational amplifier U is connected to the outputf4Output "-vw"; operational amplifier U4 and operational amplifier U5And operational amplifier Uf4The non-inverting input of (a) is terminated by "ground".
Said sign function module S having an input terminal "vx", the input is connected directly to the operational amplifier UaOf the inverting input terminal of the operational amplifier UaThe output end of the operational amplifier is connected with a resistor of 13.5k omega in series to be connected into an operational amplifier UbOf the inverting input terminal of the operational amplifier UbIs connected across a resistor of 1k omega between the inverting input terminal and the output terminal, and the operational amplifier UbOutput "sgn (v)x) "; operational amplifier UaAnd operational amplifier UbThe non-inverting input of (a) is terminated by "ground".
The circuit system has the advantages of simple structure and convenience for theoretical analysis and circuit simulation. As a chaotic signal source generating circuit, the hyperchaotic signal generated by the invention is complex, can enhance the safety when used for secret communication and image encryption, and has great engineering application value.
Drawings
FIG. 1 is a circuit of a double-vortex memristor hyper-chaotic signal source;
FIG. 1(a) is a first channel circuit;
FIG. 1(b) shows a second channel circuit;
FIG. 1(c) shows a third channel circuit;
FIG. 1(d) is a memristor module M circuit;
FIG. 1(e) is a sign function module S circuit;
FIG. 2 is a phase-track diagram of a chaotic attractor on 6 phase planes, obtained by numerical simulation of a double-vortex memristor hyperchaotic signal source circuit under initial conditions (0.1,0.1,0.1, 0.1);
FIG. 2(a) is a phase diagram in the x-y plane;
FIG. 2(b) phase trace plot in the x-z plane;
FIG. 2(c) phase rail diagram in the x-w plane;
FIG. 2(d) phase trace plot in the y-z plane;
FIG. 2(e) phase trace plot on the y-w plane;
FIG. 2(f) is in the z-w plane;
FIG. 3 is a phase-track diagram of a chaotic attractor on 6 phase planes, obtained by experimental measurement of a double-vortex memristor hyperchaotic signal source circuit;
FIG. 3(a) at vx-vyPhase rail diagram on the plane;
FIG. 3(b) at vx-vzPhase rail diagram on the plane;
FIG. 3(c) at vx-vwPhase rail diagram on the plane;
FIG. 3(d) at vy-vzPhase rail diagram on the plane;
FIG. 3(e) at vy-vwPhase rail diagram on the plane;
FIG. 3(f) at vz-vwPhase rail diagram on the plane;
FIG. 4 is an output time domain graph obtained by experimental measurement of a double-vortex memristor hyper-chaotic signal source circuit;
FIG. 4(a) output signal vxTime domain diagram of (1): t-vx；
FIG. 4(b) output signal vyTime domain diagram of (1): t-vy；
FIG. 4(c) output signal vzTime domain diagram of (1): t-vz；
FIG. 4(d) output signal vwTime domain diagram of (1): t-vw。
Detailed Description
A specific embodiment of the present invention is shown in fig. 1.
The mathematical model corresponding to the signal source circuit of the invention is as follows:
Figure BDA0002418981580000051
the mathematical model is a fourth order Jerk system where x, y, z, w are state variables, a, b, c, d are system control parameters, sgn (x) is a sign function, the sign function is a function that reflects the sign of the variables, sgn (x) has a value of 1 when x > 0 and a value of-1 when x < 0.
The formula (1) also comprises a magnetic control memristor model:
Figure BDA0002418981580000061
the memristor of the embodiment is a triple magnetic control memristor model, wherein w (x) is a memory inductor, and w (x) is m + nx2The memristor model control parameter is m is 2, and n is 0.02.
Generally, when a memristor model is added into a chaotic system, a new state variable (internal state variable of the memristor) is introduced, so that the rising order of the chaotic system is caused. The mathematical model corresponding to the embodiment utilizes a special form of a Jerk system to well solve the problem that the system is upgraded due to the introduction of a new state variable after the memristor is added into the chaotic system.
The specific method is that the internal state variable of the memristor is set as the existing state variable x of the Jerk system, and the Jerk system is in a special form
Figure BDA0002418981580000062
Just as the memristor internal equation of state.
The mathematical model design of the embodiment is equivalent to the order reduction treatment of the system, and the circuit corresponding to the reduced system is simpler and is convenient to realize.
In the formula (1), when the system control parameter is selected to be a ═ 5, b ═ 2, c ═ 5, and d ═ 5, chaotic attractors appear in the simulation of the system value under the initial condition (0.1,0.1,0.1,0.1), and double scrolls are evident in the projection of the x-y phase plane, the x-z phase plane, and the x-w phase plane.
Through Matlab numerical calculation, the Lyapunov indexes of the system are respectively as follows: lambda [ alpha ]1＝0.10565，λ2＝0.10564，λ3＝-1.3137，λ4At-3.8976, there are two positive Lyapunov indices λ1And λ2The system is proved to be capable of generating hyperchaos.
The nonlinear dynamical system described in the formula (1) can be realized by adopting an operational amplifier and an analog multiplier as well as a resistor and a capacitor.
The UA741CD is selected as the operational amplifier, and the output upper and lower limits of the operational amplifier are +/-13.5V under normal working voltage. In order to make the amplitude of each signal of the experimental circuit in a proper range and make the experimental circuit obtain a proper output signal, variable ratio compression transformation is carried out on the formula (1):
Figure BDA0002418981580000071
wherein v isx,vy,vz,vwThe voltage state variables respectively represent the voltage state variables of the capacitors in the integrating circuit and the integrating and summing circuit in fig. 1, and correspond to the system state variables x, y, z and w one to one, and RC is an integration time constant. Then equation (1) transforms to:
Figure BDA0002418981580000072
first channel input end "-v in FIG. 1(a)w' series resistance R3Rear-access operational amplifier U3Of the inverting input terminal of the operational amplifier U3Across a capacitor C between the inverting input and the output3At this time, the operational amplifier U3Output terminal "vz". The circuit expression of the first channel is:
Figure BDA0002418981580000073
second channel input end "-v in FIG. 1(b)z' series resistance R2Rear-access operational amplifier U2Of the inverting input terminal of the operational amplifier U2Across a capacitor C between the inverting input and the output2At this time, the operational amplifier U2Output terminal "vy". The circuit expression of the second channel is:
Figure BDA0002418981580000074
in the third channel in FIG. 1(c), input "-vyOperational amplifier U connected behind series memristor module M4The inverting input terminal of (1); input terminal "vxConnecting the sign function module S in series and then connecting the resistor R in series8Rear-access operational amplifier U4The inverting input terminal of (1); input terminal "-vx' series resistance R4Rear-access operational amplifier U4The inverting input terminal of (1); input terminal "-vy' series resistance R5Rear-access operational amplifier U4The inverting input terminal of (1); input terminal "-vz' series resistance R6Rear-access operational amplifier U4The inverting input terminal of (1); input terminal "-vw' series resistance R7Rear-access operational amplifier U4Of the inverting input terminal of the operational amplifier U4Across resistor R between the inverting input terminal and the output terminal9Operational amplifier U4Output end of (3) is connected with a resistor R in series10Rear-access operational amplifier U5Of the inverting input terminal of the operational amplifier U5Across a capacitor C between the inverting input and the output4At this time, the operational amplifier U5Output "vw". The circuit expression of the third channel is:
Figure BDA0002418981580000081
memristor Module M input "-v of FIG. 1(e)y' series resistance R1Rear-access operational amplifier U1Of the inverting input terminal of the operational amplifier U1Across a capacitor C between the inverting input and the output1At this time, the operational amplifier U1Output "vx", operational amplifier U1Output of (2) is connected toInto an analog multiplier A1Two input terminals of A1Is connected to the multiplier A2Input terminal of A2Is connected to the other input terminal "-vy”，A2The output end of the resistor is connected with a resistor R in seriesaAfter with "-vy' concatenation RbAnd then connected. The output of the point a in the memristor module is W (v)x)vy". Multiplier A1And multiplier A2The output gain of (2) is 0.1/V. The circuit expression of the memristor module M is as follows:
Figure BDA0002418981580000082
sign function block S input terminal "v" in the third channel of FIG. 1(d)x' direct access operational amplifier UaOf the inverting input terminal of the operational amplifier UaThe output end of the operational amplifier is connected with a resistor of 13.5k omega in series to be connected into an operational amplifier UbOf the inverting input terminal of the operational amplifier UbIs connected across a resistor of 1k omega between the inverting input terminal and the output terminal, and the operational amplifier UbOutput "sgn (v)x)”。
The circuit oscillation equation for the circuit shown in fig. 1 is:
Figure BDA0002418981580000091
let the integration time constant RC be 0.0005, compare the circuit oscillation equation (9) with the transformed system state equation (4). There are:
Figure BDA0002418981580000092
Figure BDA0002418981580000093
the parameters of each element in the circuit are selected as follows: c1＝C2＝C3＝C4＝10nF,R1＝R2＝R3＝R10＝50kΩ,R9＝50kΩ,R4＝R6＝R7＝10kΩ,R5＝Rb＝25kΩ,Ra＝10MΩ。
Under the circuit parameters, the circuit shown in fig. 1 is built in Multisim simulation software, the same ports of the experimental circuit are connected with each other, the chaotic attractor shown in fig. 3 can be collected on an oscilloscope, and the experimental result is consistent with the numerical simulation result shown in fig. 2. FIG. 4 is an output time domain diagram obtained by experimental measurement of a double-vortex memristor hyper-chaotic signal source circuit.
The above examples are merely illustrative for clearly illustrating the present invention and are not intended to limit the embodiments of the present invention. Other variations and modifications will be apparent to persons skilled in the art in light of the above description. And are neither required nor exhaustive of all embodiments.

Claims (10)

1. A double-vortex memristor hyperchaotic signal source circuit is characterized in that the signal source circuit comprises a first channel, a second channel and a third channel; the three channels consist of an integral summation circuit, an addition circuit, an integral circuit or an inverter circuit; the third channel contains a memristor module M and a sign function module S; after the same ports in the three channels are connected in sequence, the realized signal source circuit can output the hyperchaotic signal.
2. The double-scroll memristor hyperchaotic signal source circuit according to claim 1, wherein when the chaotic attractor value generated by the signal source circuit is simulated, there are obvious double scrolls in the projection of an x-y phase plane, an x-z phase plane and an x-w phase plane.
3. The dual-eddy memristor hyper-chaotic signal source circuit according to claim 1, wherein the first channel is composed of an integral summation circuit and an inverting circuit; the first channel has only one input and one output, the input being the output of the third channel.
4. The dual-eddy memristor hyper-chaotic signal source circuit according to claim 1, wherein the second channel consists of an integral summation circuit and an inversion circuit; the second channel has only one input and one output, the inputs being the outputs of the first channel.
5. The dual-eddy memristor hyper-chaotic signal source circuit according to claim 1, wherein the third channel is composed of an addition circuit, an integration circuit and an inverter circuit; the third channel also comprises a memristor module M and a sign function module S; there are six inputs and one output for the third channel; the six inputs include the output of the first channel, the output of the second channel and the output of the third channel, and the inputs also include the output of the operational amplifier in the memristor module M and the corresponding inverted output.
6. The circuit of claim 3, wherein the first channel has an input terminal "-v,"w", the input end is connected with a resistor R in series3Rear-access operational amplifier U3Of the inverting input terminal of the operational amplifier U3Across a capacitor C between the inverting input and the output3At this time, the operational amplifier U3Output terminal "vz"; operational amplifier U3The output end of the operational amplifier is connected with a 100k omega resistor in series and then is connected with an operational amplifier Uf3Of the inverting input terminal of the operational amplifier Uf3Is connected across a 100k omega resistor between the inverting input and the output, and the operational amplifier U is connected to the outputf3Output "-vz"; operational amplifier U3And operational amplifier Uf3The non-inverting input of (a) is terminated by "ground".
7. The circuit of claim 4, wherein the second channel has an input terminal "-v,"z", the input end is connected with a resistor R in series2Rear-access operational amplifier U2Of the inverting input terminal of the operational amplifier U2And an inverting input terminal ofCapacitor C connected across output ends2At this time, the operational amplifier U2Output terminal "vy"; operational amplifier U2The output end of the operational amplifier is connected with a 100k omega resistor in series and then is connected with an operational amplifier Uf2Of the inverting input terminal of the operational amplifier Uf2Is connected across a 100k omega resistor between the inverting input and the output, and the operational amplifier U is connected to the outputf2Output "-vy"; operational amplifier U2And operational amplifier Uf2The non-inverting input of (a) is terminated by "ground".
8. The circuit of claim 5, wherein the third channel has six inputs, wherein "-v" is the inputyOperational amplifier U connected behind series memristor module M4The inverting input terminal of (1); input terminal "vxConnecting the sign function module S in series and then connecting the resistor R in series8Rear-access operational amplifier U4The inverting input terminal of (1); input terminal "-vx' series resistance R4Rear-access operational amplifier U4The inverting input terminal of (1); input terminal "-vy' series resistance R5Rear-access operational amplifier U4The inverting input terminal of (1); input terminal "-vz' series resistance R6Rear-access operational amplifier U4The inverting input terminal of (1); input terminal "-vw' series resistance R7Rear-access operational amplifier U4Of the inverting input terminal of the operational amplifier U4Across resistor R between the inverting input terminal and the output terminal9Operational amplifier U4Output end of (3) is connected with a resistor R in series10Rear-access operational amplifier U5Of the inverting input terminal of the operational amplifier U5Across a capacitor C between the inverting input and the output4At this time, the operational amplifier U5Output "vw"; operational amplifier U5The output end is connected in series with a 100k omega resistor connected into an operational amplifier Uf4Of the inverting input terminal of the operational amplifier Uf4Is connected across a 100k omega resistor between the inverting input and the output, and the operational amplifier U is connected to the outputf4Output "-vw"; operational amplifier U4 and operational amplifier U5And operational amplifier Uf4The non-inverting input of (a) is terminated by "ground".
9. The circuit of claim 8, wherein the sign function module S has an input terminal "vx", the input is connected directly to the operational amplifier UaOf the inverting input terminal of the operational amplifier UaThe output end of the operational amplifier is connected with a resistor of 13.5k omega in series to be connected into an operational amplifier UbOf the inverting input terminal of the operational amplifier UbIs connected across a resistor of 1k omega between the inverting input terminal and the output terminal, and the operational amplifier UbOutput "sgn (v)x) "; operational amplifier UaAnd operational amplifier UbThe non-inverting input of (a) is terminated by "ground".
10. The dual-vortex memristor hyper-chaotic signal source circuit according to claim 1, wherein a mathematical model of the signal source circuit is as follows:
Figure FDA0002418981570000031
the circuit expression of the first channel is as follows:
Figure FDA0002418981570000032
the circuit expression of the second channel is as follows:
Figure FDA0002418981570000033
the circuit expression of the third channel is as follows:
Figure FDA0002418981570000034
the circuit expression of the memristor module M is as follows:
Figure FDA0002418981570000035
the parameters in the formula are defined as follows: v. ofx,vy,vz,vwRespectively representing the voltage state variables of capacitors in an integrating circuit and an integrating and summing circuit in a signal source circuit, and corresponding to the system state variables x, y, z and w one by one; RC is an integration time constant; sgn (x) is a sign function; r1For memristor module M input end "-v in third channely"series resistance; r2For the second channel input end "-vz"series resistance; r3For the input end "-v of the first channelw"series resistance; r4For the third channel input end "-vx"series resistance; r5For the third channel input end "-vy"series resistance; r6For the third channel input end "-vz"series resistance; r7For the third channel input end "-vw"series resistance; r8Is the series resistance of the third channel sign function module S; r9An operational amplifier U as a third channel4A resistor is connected between the inverting input end and the output end in a bridging way; r10For a third channel operational amplifier U4The output end of the resistor is connected in series with a resistor; raCircuit multiplier A for memristor module M2The output end of the resistor is connected in series with a resistor; rbFor memristor module M circuit and input end' -vy"series resistance; c1Operational amplifier U for memristor module M circuit1A capacitor is connected between the inverting input end and the output end in a bridging way; c2For the second channel 1 operational amplifier U2A capacitor is connected between the inverting input end and the output end in a bridging way; c3For a first channel operational amplifier U3A capacitor is connected between the inverting input end and the output end in a bridging way; c4For a third channel operational amplifier U5Across a capacitor between the inverting input and the output.
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