CN115048296B - Method for verifying validity of memory barrier instruction and related product - Google Patents
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Abstract
The invention relates to a method and a related product for verifying the validity of a memory barrier instruction, wherein the method comprises the following steps: obtaining verification instructions, wherein the verification instructions comprise one or more instruction subsets generated based on configuration information of various program structures in a verification code set, and each instruction subset comprises memory barrier instructions; running the verification instruction by using a CPU to generate an execution result of the verification instruction; comparing the execution result of the verification instruction by the CPU with a standard result corresponding to the verification instruction; and determining that the memory barrier instruction in the CPU is invalid in response to the fact that the execution result of the CPU on the verification instruction is different from the standard result corresponding to the verification instruction. The method solves the problems of poor system safety and incapability of ensuring the instruction operation correctness caused by abnormal function of the existing CPU memory barrier instruction.
Description
Technical Field
The present invention relates generally to the field of computer technology. More particularly, the present invention relates to a method, apparatus, and computer readable storage medium for verifying memory barrier instruction validity.
Background
In recent years, the directions of science and technology in China are continuously developed, but the core arithmetic unit, the dispatcher, the operating system, the core algorithm and the chip design principle are still in the fumbling and learning stage.
In the design concept of the core processor, the first generation design of 'instruction sequence execution' in China and developed countries in the world is shifted into the second generation design stage of 'instruction out-of-order emission and out-of-order execution', and a large number of peak core processor design frameworks based on 'instruction out-of-order emission and out-of-order execution' are generated, such as Arm v8 series, intel Xeon and the like. The out-of-order execution of the instructions enables the performance of the core processor to be significantly improved in a self-optimizing manner.
When receiving 1-4 instructions, the conventional instruction sequential execution CPU sequentially executes the following steps: firstly, the address "Beijing" is moved to "Guangzhou", secondly, the address "Tianjin" is moved to "Shanghai", secondly, the address "Beijing" is moved to "Tianjin", and finally, the address "Shanghai" is moved to "Guangzhou". As shown in table 1 below:
Table 1:
| Sequence number | Instructions for | Execution order |
| 1 | Beijing- > Guangzhou | 1 |
| 2 | Tianjin- > Shanghai | 2 |
| 3 | Beijing- > Tianjin | 3 |
| 4 | Shanghai- > Guangzhou | 4 |
The implementation mode has the advantages that: the CPU can perform each task precisely, but the drawbacks thereof are also apparent. There is redundancy in time and space on the instruction paths and associated nodes. It can be obviously seen that the CPU can complete all tasks once without addressing from Beijing to Guangzhou twice, so that the design of 'instruction out-of-order emission and out-of-order execution' is added in the subsequent CPU design. All instructions are first issued out of order to the instruction level queue of the CPU for queuing, and then ordering, screening, and optimization (e.g., some instructions do not execute). And then, after the redundant instructions which do not influence the running result of the program are sequenced and optimized, performing 'out-of-order' optimization execution to achieve the result of optimizing the performance. The actual execution order of the optimized instructions is shown in table 2:
Table 2:
| Sequence number | Instructions for | Optimizing results | Actual execution order |
| 1 | Beijing- > Guangzhou | Optimizing drop | Not to perform |
| 2 | Tianjin- > Shanghai | The ordering is unchanged | 2 |
| 3 | Beijing- > Tianjin | Ordering 1 | 1 |
| 4 | Shanghai- > Guangzhou | Sequencing 3 | 3 |
The execution order of the instructions in table 2 is as follows: firstly, the address "Beijing" is moved to "Tianjin", secondly, the address "Tianjin" is moved to "Shanghai", and finally, the address "Shanghai" is moved to "Guangzhou". Since the instructions of "Beijing- > Guangzhou" actually achieve the effect, the optimization is not performed. The mode ensures that the original order input instructions are transmitted to the operation unit of the CPU in disorder due to optimization and are not executed according to the original order, namely 'out-of-order transmission and out-of-order execution', thereby greatly accelerating the operation speed and efficiency of the CPU and being the main stream design principle of the contemporary CPU. However, the method has a certain vulnerability in safety, the original sequence of instruction execution is destroyed, the source address and the target address of the instruction are easily prejudged, and certain information is acquired in a side channel analysis mode, so that information leakage is caused.
With the development of the technology of 'out-of-order execution' of a CPU, in order to ensure that the program strictly executes the sequence of original instructions in the operation process, the CPU adds a 'memory barrier' instruction barrier () in an instruction set, so that statements on two sides of the memory barrier prohibit execution optimization. The execution order after the memory barrier instruction is added is shown in table 3 below:
Table 3:
| Sequence number | Instructions for | Execution order |
| 1 | Beijing- > Guangzhou | Not to perform |
| 2 | Tianjin- > Shanghai | 2 |
| 3 | Beijing- > Tianjin | 1 |
| 4 | Shanghai- > Guangzhou | 3 |
| 5 | barrier() | 4 |
| 6 | Shanghai- > Guangzhou | 6 |
| 7 | Tianjin- > Shanghai | 5 |
The occurrence of the memory barrier instruction barrier () causes the instruction queue to be divided into a group preceding the memory barrier instruction (i.e., instructions with sequence numbers 1-4) and a group following the memory barrier instruction (i.e., instructions with sequence numbers 6-7). The actual execution sequence can show that the CPU performs out-of-order execution on the 1-4 instruction and the 6-7 instruction respectively at two sides of the memory barrier instruction, and does not perform out-of-order execution according to the 1-7 instruction. Without the addition of the "memory barrier" instruction barrier (), its theoretical out-of-order execution yields the following results in table 4:
table 4:
| Sequence number | Instructions for | Execution order |
| 1 | Beijing- > Guangzhou | Not to perform |
| 2 | Tianjin- > Shanghai | 2 |
| 3 | Beijing- > Tianjin | 1 |
| 4 | Shanghai- > Guangzhou | 3 |
| 5 | Shanghai- > Guangzhou | Not to perform |
| 6 | Tianjin- > Shanghai | Not to perform |
The memory barrier instruction is an important condition for preventing the out-of-order execution of the CPU, and the hardware implementation of the memory barrier instruction can be realized by an instruction level isolation register, a switch selection gate circuit and the like. In the design process of detail chips, for example: in the implementation of the instruction level isolation register, the switch gate circuit and the selection gate circuit, the functions of the devices are disabled due to the defects of the process and the design, and the disabled result is that the memory barrier instruction barrier () cannot normally operate, so that large-scale out-of-order instruction execution occurs, and the operation logic of the traditional chip is damaged. If the phenomenon is not found in time, serious problems such as poor system safety, incapability of ensuring the instruction operation accuracy and the like are brought about by abnormal function of the CPU memory barrier instruction.
Since the production and test of the CPU depend on the manufacturing level and test level of the CPU streaming manufacturer or CPU designer, the problem of the invalidation of the memory barrier instruction cannot be truly reflected in the operating system and the user layer, and thus the influence of the invalidation of the memory barrier instruction on the execution instruction of the CPU is not easily found. Moreover, memory barrier instructions are currently rarely introduced during normal programming, and therefore are not easily detected by programmers even if they fail. However, the correctness of the memory barrier instruction execution is related to the system security and the instruction execution correctness, and the value of the memory barrier instruction execution in the domestic autonomous CPU is not ignored.
Therefore, how to quickly and conveniently detect whether the CPU barrier instruction has a functional abnormality becomes a technical problem to be solved.
Disclosure of Invention
In order to solve one or more of the above technical problems, the present invention proposes to generate a verification instruction including a memory barrier through various program structures, and determine the validity of the memory barrier instruction in the CPU by using the execution result of the verification instruction executed by the CPU, thereby effectively improving the validity of instruction operation in the CPU, and reducing unauthorized use or authority improvement loopholes caused by improper use of the memory barrier instruction. To this end, the present invention provides solutions in various aspects as follows.
In a first aspect, the present invention provides a method for verifying validity of a memory barrier instruction, including: obtaining verification instructions, wherein the verification instructions comprise one or more instruction subsets generated based on configuration information of various program structures in a verification code set, and each instruction subset comprises memory barrier instructions; running the verification instruction by using a CPU to generate an execution result of the verification instruction; comparing the execution result of the verification instruction by the CPU with a standard result corresponding to the verification instruction; and determining that the memory barrier instruction in the CPU is invalid in response to the fact that the execution result of the verification instruction by the CPU is different from the standard result corresponding to the verification instruction.
In one embodiment, the program structure includes one or more of the following types: a sequence structure, a circulation structure, a judgment structure, a queue structure, a stack structure, a tree structure, a graph structure and a nested structure, wherein the graph structure comprises an undirected graph structure and a directed graph structure.
In one embodiment, the executing the validation instruction with the CPU to generate an execution result of the validation instruction includes: sequencing the corresponding instruction subsets according to the sequence from small to large of the complexity of the program structure; and respectively running the instruction subsets corresponding to each program structure by utilizing the CPU according to the sequencing so as to generate corresponding execution results.
In one embodiment, the subset of instructions further includes a probe, wherein the executing the validation instruction with the CPU to generate an execution result of the validation instruction further includes: and acquiring data flow information of the verification instruction when the verification instruction runs in the CPU by using the probe so as to monitor the processing process of the CPU.
In one embodiment, before inputting the verification instruction into the CPU, the method further comprises: disabling an optimization option of the compiler to avoid the compiler from optimizing the validation instruction; and inputting the verification instruction into a compiler to convert the verification instruction into a binary instruction recognizable by the CPU.
In one embodiment, the method further comprises: and performing pressurization detection on the CPU to judge the validity of the memory barrier instruction when the pressure is set.
In one embodiment, the performing the pressurization detection on the CPU to determine the validity of the memory barrier instruction at the set pressure includes: detecting the load pressure of the CPU to judge whether the load pressure is larger than a set pressure or not; and in response to the load pressure being below a set pressure, raising the load pressure of the CPU to raise the load pressure of the CPU to the set pressure.
In one embodiment, the acquiring verification instructions include: selecting code information of one or more program structures from a preset verification code set; and generating a subset of instructions based on the code information of each program structure to form a verification instruction for verifying the validity of the memory barrier.
In a second aspect, the present invention also provides an apparatus for verifying validity of a memory barrier instruction, comprising: a processor; and a memory storing computer instructions for verifying memory barrier instruction validity, which when executed by the processor, cause the electronic device to perform a method according to one or more embodiments of the first aspect.
In a third aspect, the invention also provides a computer readable storage medium having stored thereon computer readable instructions for verifying memory barrier instruction validity, which when executed by one or more processors, implement a method as described in one or more embodiments of the first aspect.
According to the technical scheme of the invention, corresponding verification instructions can be generated based on various program structures, and the verification instructions are operated by the CPU so as to verify the validity of the memory barrier instructions in the CPU according to the execution result, thereby effectively improving the system safety and the instruction operation correctness in the CPU. The method does not need to acquire program source codes, and can realize convenient and comprehensive detection of the effectiveness of the CPU memory barrier instruction at the user layer. Furthermore, in the scheme of the invention, the operation pressure of the CPU is increased in the verification process by adopting a pressurizing detection mode, so that the CPU is more comprehensively detected.
Drawings
The above, as well as additional purposes, features, and advantages of exemplary embodiments of the present invention will become readily apparent from the following detailed description when read in conjunction with the accompanying drawings. In the drawings, embodiments of the invention are illustrated by way of example and not by way of limitation, and like reference numerals refer to similar or corresponding parts and in which:
FIG. 1 is a schematic diagram schematically illustrating a scenario for verifying the validity of a memory barrier instruction according to an embodiment of the present invention;
FIG. 2 is a flow chart schematically illustrating a method for verifying the validity of a memory barrier instruction according to an embodiment of the present invention;
FIG. 3 is a flow chart schematically illustrating another method for verifying the validity of a memory barrier instruction according to an embodiment of the present invention;
FIG. 4 is a diagram schematically illustrating a memory barrier instruction in a tree program structure according to an embodiment of the present invention;
FIG. 5 is a diagram schematically illustrating a memory barrier instruction in an undirected graph program architecture according to one embodiment of the present invention;
FIG. 6 is a schematic diagram schematically illustrating a memory barrier instruction in a directed graph program structure according to an embodiment of the present invention;
Fig. 7 is a schematic diagram schematically illustrating an apparatus for verifying the validity of a memory barrier instruction according to an embodiment of the present invention.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are some, but not all embodiments of the present invention. All other embodiments, based on the embodiments of the invention, which a person skilled in the art would obtain without making any inventive effort, are within the scope of the invention.
It should be understood that the terms "first," "second," "third," and "fourth," etc. in the claims, specification and drawings of the present invention are used for distinguishing between different objects and not for describing a particular sequential order. The terms "comprises" and "comprising" when used in the specification and claims of the present invention are taken to specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
It is also to be understood that the terminology used in the description of the invention herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used in the specification and claims, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should be further understood that the term "and/or" as used in the present specification and claims refers to any and all possible combinations of one or more of the associated listed items, and includes such combinations.
As used in this specification and the claims, the term "if" may be interpreted as "when..once" or "in response to a determination" or "in response to detection" depending on the context. Similarly, the phrase "if a determination" or "if a [ described condition or event ] is detected" may be interpreted in the context of meaning "upon determination" or "in response to determination" or "upon detection of a [ described condition or event ]" or "in response to detection of a [ described condition or event ]".
Specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.
The memory barrier instruction class is different from other traditional instructions, the operation of the memory barrier instruction class does not relate to logic of changing the level of a processor pin, the test method cannot be directly embodied by directly measuring the high and low levels of the instruction, and the memory barrier instruction class is embodied only when the corresponding instruction level logic is changed, so that the memory barrier instruction class has certain concealment. In addition, at present, CPU manufacturers do not disclose internal detection mechanisms and detection methods due to the demands of commercial confidentiality and security, so that elaborate designs are needed to find out the design defects. According to the scheme provided by the invention, the scheme for detecting the effectiveness of the memory barrier instruction is provided, so that whether the memory barrier instruction in the CPU is executed correctly or not is judged on the basis of no knowledge of source codes, and the running safety and reliability of a computer system are effectively improved.
Fig. 1 is a schematic diagram of a scenario 100 schematically illustrating a scheme for verifying the validity of a memory barrier instruction according to an embodiment of the present invention. In the context of the present invention, it is desirable to form an overall framework of a computer when determining the validity of memory barrier instructions in a CPU. The whole frame can be divided into the following functional modules: "hardware support module", "kernel", "C language support module", "optimization compiler", "load pressure generator" and "memory barrier verification code library".
The hardware support module mainly comprises a main board, a CPU slot, a physical memory and an SSD hard disk. The hardware support module is used as general hardware, can support the verification work of the CPU, and has the function of the prior art, and is not repeated here. The Kernel refers to an operating system Kernel, and is mainly used for hardware support, scheduling, process management and memory management, and in the scheme, general Linux Kernel is mainly used. The C language support module is a function which is packed in C language and is embedded and assembled by CPU with memory barrier instructions, and because the C language is used as the basis of a verification program during the test of the scheme, a general C language support library is required to support the function. It will be appreciated that other programming languages may be employed as a basis for the verification program and accordingly may include a support module for the programming language thereof, as the embodiments of the invention are not limited in this respect. The optimization compiler needs to prohibit any optimization during compilation. All optimization options are closed when the program is compiled, and a debugging symbol instrumentation link can be added when a verification instruction is generated so as to realize the visualization of the running process. The memory barrier verification code library is a C language code library for verifying memory barrier instructions, and is mainly divided into programs for detecting 8-class program structures: sequential structure barrier detection, cyclic structure barrier detection, judging structure barrier detection, queue/stack structure barrier detection, tree structure barrier detection, directed graph structure barrier detection, undirected graph structure barrier detection, nested structure barrier detection.
The structure of memory barrier verification code library 101, compiler 102, and CPU103 are shown in fig. 1 for illustrative purposes only in the present invention. The memory barrier verification code library 101 includes a verification code set for verifying the validity of various memory barrier instructions, and the compiler 102 is an optimization compiler described above, and its optimization function needs to be disabled during the verification process.
As shown in fig. 1, by using the verification code set in the memory barrier verification code library 101, a subset of instructions may be generated according to configuration information of various program structures, and one or more subsets of instructions may constitute a verification instruction, so that the CPU103 may execute the verification instruction to implement a validity detection process.
After acquiring the verification instruction, the compiler 102 may convert the verification instruction into a machine instruction code that can be identified by the CPU, so that the CPU outputs an execution result after executing the machine instruction code.
The CPU103 outputs an execution result according to the execution process of the verification instruction, compares the execution result with a standard result corresponding to the verification instruction, and then determines whether the memory barrier instruction in the CPU is invalid according to the comparison result.
FIG. 2 is a flow chart schematically illustrating a method 200 for verifying memory barrier instruction validity according to an embodiment of the present invention.
As shown in fig. 2, at step S201, a verification instruction is acquired. The validation instructions may include one or more subsets of instructions generated based on configuration information of various program structures in the validation code set, each subset of instructions containing memory barrier instructions. In some embodiments, the program structure may include one or more of the following types: a sequence structure, a circulation structure, a judgment structure, a queue structure, a stack structure, a tree structure, a graph structure and a nested structure, wherein the graph structure comprises an undirected graph structure and a directed graph structure.
At step S202, the verification instruction is executed with the CPU to generate an execution result of the verification instruction. In some embodiments, when the CPU runs, the CPU may verify only the memory barrier instruction in one of the program structures according to the type of the verification instruction, or may verify the memory barrier instruction in multiple program structures respectively.
At step S203, the execution result of the verification instruction by the CPU is compared with the standard result corresponding to the verification instruction. In some embodiments, the comparison result may be obtained by counting the same number and different number of times the execution result is compared with the standard result in a period of time.
At step S204, in response to the execution result of the verification instruction by the CPU being different from the standard result corresponding to the verification instruction, it is determined that the memory barrier instruction in the CPU is invalid. In some embodiments, the memory barrier instruction in the CPU may be determined to be invalid when the execution result of the verification instruction by the CPU is different from the standard result corresponding to the verification instruction. The judgment can also be performed according to the same times and different times of the execution result and the standard result in a period of time. For example, if the same number of times is 99% over a period of time, then the memory barrier instruction may be considered to be executed effectively, otherwise it is determined that the memory barrier instruction in the CPU is invalid.
FIG. 3 is a flow chart schematically illustrating another method 300 for verifying the validity of a memory barrier instruction according to an embodiment of the present invention.
As shown in fig. 3, at step S301, code information of one or more program structures is selected from a preset set of verification codes. In some embodiments, the memory barrier verification code library includes code information of a plurality of program structures, and in the process of generating the verification instruction, the code information of one or more program mechanisms may be selected to generate the verification code corresponding to the memory barrier instruction in the corresponding program structure.
At step S302, a subset of instructions is generated based on the code information of each program structure to form a verification instruction for verifying the validity of the memory barrier. In some embodiments, the code information of each program structure in combination with the configuration information of the program structure may generate a subset of instructions of the corresponding program structure, which may form a verification instruction for verifying the validity of the memory barrier.
In actual operation, before the CPU executes the instruction code, the compiler will also optimize the instruction code, so that in order to accurately detect the validity of the memory barrier instruction in the CPU, the optimization function of the compiler needs to be disabled. Therefore, before the aforementioned validation instruction is input to the CPU, at step S303, the optimization option of the compiler is disabled to avoid the compiler optimizing the validation instruction.
Next, at step S304, a validation instruction is input to the compiler to convert the validation instruction into a binary instruction that the CPU can recognize.
Then, at step S305, the corresponding instruction subsets are sorted in order of complexity of the program structure from small to large, respectively. In some embodiments, the complexity of the program structure is from small to large, and the program structure may be divided into a sequential structure, a loop structure, a judgment structure, a queue structure, a stack structure, a tree structure, a graph structure and a nested structure, wherein the graph structure includes an undirected graph structure and a directed graph structure. Based on the above order, priorities at the time of verification of different program structures in the verification instruction can be set.
At step S306, the CPU is used to execute the instruction subsets corresponding to each program structure according to the ordering, respectively, to generate corresponding execution results. In some embodiments, if the running result of the instruction subset corresponding to one of the program structures does not match the standard result, it may be determined that the memory barrier instruction in the CPU cannot run normally. In order to realize comprehensive detection of the CPU, the instruction subset corresponding to each program structure is still verified.
Further, the instruction subset may further include a probe to detect data information during operation of the CPU. At step S307, the data flow information at the time of execution of the verification instruction in the CPU can be acquired by the probe so as to monitor the processing procedure of the CPU. In some embodiments, probes may be inserted into code through a program instrumentation process at compile time, thereby enabling memory monitoring, instruction tracking, error detection, etc. at program run time in the CPU.
Further, in step S308, the CPU performs a pressurization detection to determine the validity of the memory barrier command at the set pressure. In some embodiments, the load pressure generator may be utilized to increase the pressure of the CPU operations. Because the CPU operates in multiple modes, and the load thereof is in a high load operation mode, the operation logic may be optimized in a higher manner, resulting in rearrangement of instruction level, or neglecting the validity of the memory barrier instruction, it is necessary to manually adjust the load of the CPU during operation to determine whether the CPU can normally operate the memory barrier instruction under different load pressures.
In some embodiments, when the CPU is pressurized to determine the validity of the memory barrier command at the set pressure, the load pressure of the CPU is first detected to determine whether the load pressure of the CPU is greater than the set pressure. When the load pressure is lower than the set pressure, the load pressure of the CPU is raised to raise the load pressure of the CPU to the set pressure. The CPU can normally operate the memory barrier instruction under high pressure through the pressurization detection process, so that the CPU is detected more comprehensively, and the safety of a computer system is ensured.
The methods described in one or more embodiments of the present invention will be described in connection with the validity detection of memory barrier instructions in various program structures in a CPU, respectively. Specifically, the verification instruction may include sequential structure barrier detection, loop structure barrier detection, judgment structure barrier detection, queue structure barrier detection, stack structure barrier detection, tree structure barrier detection, undirected graph structure barrier detection, directed graph structure barrier detection, and nested structure barrier detection according to an execution order of the instruction subset.
The first is sequential structure barrier detection, which refers to inserting a memory barrier instruction into the sequentially executed program logic to observe the effect of the execution of the memory barrier instruction. The sequential program structure in Table 5 below, for example, includes sequential logic statements 1-10.
Table 5:
It can be seen that a memory barrier instruction 1 is provided between sequential logic statement 4 and sequential logic statement 5, and a memory barrier instruction 2 is provided between sequential logic statement 7 and sequential logic statement 8. Based on this, the logical correctness of the three sets of sequential program structures of sequential logic statements 1-4, 5-7, and 8-10 will be observed primarily in the execution results.
The second type is loop structure barrier detection, which refers to inserting a memory barrier instruction into the program logic of the loop structure to observe the execution effect of the memory barrier instruction. Two examples of the cyclic structure are shown in the following 6.
Table 6:
It can be seen that, in the loop structure example 1, the memory barrier instruction 1 is provided between the sequential logic statement 2 and the sequential logic statement 3 other than the do-while statement, and the memory barrier instruction 3 is provided between the sequential logic statement 10 and the sequential logic statement 11. In the loop logic statement, a memory barrier instruction 2 is provided between the logic statement 6 and the logic statement 7. Based on this, in addition to observing the logical correctness of the program structure in the sequential logical statement, the logical correctness of the program structure in the loop logical statement is also observed in the execution result.
The third is to determine the structure barrier detection, which refers to inserting a memory barrier instruction into the program logic of the determination structure to observe the execution effect of the memory barrier instruction. Two examples of the determination structure are shown in table 7 below.
Table 7:
It can be seen that, in the judgment structure example 1, the memory barrier instruction 1 is provided between the sequential logic statement 2 and the sequential logic statement 3 other than the if-else statement, and the memory barrier instruction 4 is provided between the sequential logic statement 14 and the sequential logic statement 15. In the judgment logic statement, a memory barrier instruction 2 is arranged between the logic statement 6 and the logic statement 7, and a memory barrier instruction 3 is arranged between the logic statement 12 and the logic statement 13. Based on this, in addition to the logical correctness of the program structure in the sequential logical statement, the logical correctness of the program structure in the judgment logical statement is observed in the execution result.
The fourth is queue/stack structure barrier detection, which refers to inserting a memory barrier instruction into the program logic of the queue/stack structure to observe the execution effect of the memory barrier instruction. The placement of memory barrier instructions in the queue structure and stack structure are shown below, respectively.
Queue structure:
……
pending enqueue queue statement 7
| Queue statement 6 |
| Queue statement 5 |
| Memory barrier instruction 2 |
| Queue statement 4 |
| Queue statement 3 |
| Memory barrier instruction 1 |
| Queue statement 2 |
| Queue statement 1 |
It can be seen that a memory barrier instruction 1 is arranged between the queue statement 2 and the queue statement 3 in the queue structure, and a memory barrier instruction 2 is arranged between the queue statement 4 and the queue statement 5 in the queue structure. Based on this, the logical correctness of three sets of queue statements 1-2, 3-4, and 5-6 are required to be observed in the execution result.
Stack structure:
Push statement and pop statement
Trestle top
Trestle bottom
It can be seen that a memory barrier instruction 1 is arranged between a queue statement 2 and a queue statement 3 in the stack structure, a memory barrier instruction 2 is arranged between a queue statement 4 and a queue statement 5 in the queue structure, and a memory barrier instruction 3 is arranged between a queue statement 7 and a queue statement 8 in the queue structure. Based on this, the logical correctness of three sets of queue statements 1-2, 3-4, 5-7, and 8-9 are required to be observed in the execution result.
The fifth is tree-structure barrier detection, which refers to inserting a memory barrier instruction into the program logic of the tree structure, and observing the execution effect of the memory barrier instruction. Fig. 4 is a schematic diagram schematically illustrating a memory barrier instruction in a tree program structure according to an embodiment of the invention.
The sixth is the barrier detection of the graphics structure, which refers to inserting a memory barrier instruction into the program logic of the graphics structure to observe the execution effect of the memory barrier instruction. The graphical structure may include an undirected graph structure and a directed graph structure. FIG. 5 is a diagram schematically illustrating a memory barrier instruction in an undirected graph program architecture according to one embodiment of the present invention. As shown in fig. 5, a memory barrier instruction may be inserted between program logic to effect verification of the validity of the memory barrier instruction therein. FIG. 6 is a schematic diagram schematically illustrating a memory barrier instruction in a directed graph program structure according to an embodiment of the present invention. As shown in fig. 6, a memory barrier instruction is provided between each program logic in the directed graph program structure to verify the validity of the memory barrier instruction therein. Further, a nested structure barrier detection may be further included, which is to integrate the mixed use of the above 2 or more program logics, and randomly add a memory barrier instruction in the multi-layer nest to verify the correctness of the logic.
Fig. 7 is a schematic diagram schematically illustrating an apparatus 700 for verifying memory barrier instruction validity according to an embodiment of the present invention. The device 700 for verifying the validity of a memory barrier instruction may include the device 701 and its peripheral devices and external networks according to an embodiment of the present invention. As previously described, the apparatus 701 performs operations of acquiring a verification instruction, inputting the verification instruction into the CPU, comparing an execution result with a standard result, and the like, to implement the solution of the present invention described in connection with fig. 2 or fig. 3.
As shown in fig. 7, the device 701 may include a CPU7011, which may be a general-purpose CPU, a special-purpose CPU, or other execution unit for information processing and program execution. Further, the device 701 may further include a mass memory 7012 and a read only memory ROM 7013, wherein the mass memory 7012 may be configured to store various kinds of data and various programs required for a multimedia network, and the ROM 7013 may be configured to store a power-on self-test for the device 701, initialization of various functional modules in the system, a driver for basic input/output of the system, and data required to boot an operating system.
Further, the device 701 also includes other hardware platforms or components, such as a TPU (Tensor Processing Unit ) 7014, GPU (Graphic Processing Unit, graphics processor) 7015, FPGAs (Field Programmable GATE ARRAY, field programmable gate arrays) 7016 and MLU (Memory Logic Unit), memory logic unit) 7017 as shown. It will be appreciated that while various hardware platforms or components are shown in device 701, this is by way of example only and not limitation, and that one of skill in the art may add or remove corresponding hardware as desired. For example, device 701 may include only a CPU as a well-known hardware platform and another hardware platform as a test hardware platform of the present invention.
The device 701 of the present invention further comprises a communication interface 7018 whereby it may be connected to a local area network/wireless local area network (LAN/WLAN) 705 via the communication interface 7018 and further to a local server 706 or to the Internet ("Internet") 707 via the LAN/WLAN. Alternatively or additionally, the device 701 of the present invention may also be directly connected to the internet or cellular network via the communication interface 7018 based on wireless communication technology, such as third generation ("3G"), fourth generation ("4G"), or 5 th generation ("5G") wireless communication technology. In some application scenarios, the device 701 of the present invention may also access the server 708 and possibly the database 709 of the external network as needed.
Peripheral devices of the device 701 may include a display device 702, an input device 703, and a data transmission interface 704. In one embodiment, the display device 702 may include, for example, one or more speakers and/or one or more visual displays. The input device 703 may include, for example, a keyboard, mouse, microphone, gesture-capturing camera, or other input buttons or controls configured to receive input of data or user instructions. The data transfer interface 704 may include, for example, a serial interface, a parallel interface, or a universal serial bus interface ("USB"), a small computer system interface ("SCSI"), serial ATA, fireWire ("FireWire"), PCI Express, and high definition multimedia interface ("HDMI"), etc., configured for data transfer and interaction with other devices or systems.
The above-described CPU 7011, mass memory 7012, read only memory ROM 7013, TPU 7014, GPU 7015, FPGA 7016, MLU 7017, and communication interface 7018 of the device 701 of the present invention can be connected to each other through a bus 7019, and data interaction with peripheral devices can be achieved through the bus. In one embodiment, the cpu 7011 may control other hardware components in the device 701 and its peripherals through the bus 7019.
In operation, the processor CPU 7011 of the apparatus 701 of the present invention may retrieve media data packets via the input device 703 or the data transfer interface 704 and retrieve computer program instructions or code stored in the memory 7012 to verify the validity of the memory barrier instructions.
From the above description of the modular design of the present invention, it can be seen that the system of the present invention can be flexibly arranged according to the application scenario or requirement and is not limited to the architecture shown in the drawings. Further, it should also be appreciated that any module, unit, component, server, computer, or device that performs the operations of the examples of the invention may include or otherwise access a computer-readable medium, such as a storage medium, a computer storage medium, or a data storage device (removable) and/or non-removable) such as, for example, a magnetic disk, optical disk, or magnetic tape. Computer storage media may include volatile and nonvolatile, removable and non-removable media implemented in any method or technology for storage of information such as computer readable instructions, data structures, program modules or other data. Based on this, the present invention also discloses a computer-readable storage medium having stored thereon computer-readable instructions for a method of verifying memory barrier instruction validity, which when executed by one or more processors, implement the method and operations described above in connection with the accompanying drawings.
While various embodiments of the present invention have been shown and described herein, it will be obvious to those skilled in the art that such embodiments are provided by way of example only. Numerous modifications, changes, and substitutions will occur to those skilled in the art without departing from the spirit and scope of the invention. It should be understood that various alternatives to the embodiments of the invention described herein may be employed in practicing the invention. The appended claims are intended to define the scope of the invention and to cover such modular compositions, equivalents, or alternatives falling within the scope of the claims.
Claims (6)
1. A method for verifying the validity of a memory barrier instruction, comprising:
obtaining verification instructions, wherein the verification instructions comprise one or more instruction subsets generated based on configuration information of various program structures in a verification code set, and each instruction subset comprises memory barrier instructions;
running the verification instruction by using a CPU to generate an execution result of the verification instruction;
comparing the execution result of the verification instruction by the CPU with a standard result corresponding to the verification instruction; and
Determining that a memory barrier instruction in the CPU is invalid in response to the fact that an execution result of the CPU on the verification instruction is different from a standard result corresponding to the verification instruction;
wherein the executing the verification instruction with the CPU to generate an execution result of the verification instruction includes:
sequencing the corresponding instruction subsets according to the sequence from small to large of the complexity of the program structure; and
Respectively running a corresponding instruction subset of each program structure by utilizing the CPU according to the sequencing to generate a corresponding execution result;
The subset of instructions further includes a probe, wherein the executing the validation instruction with the CPU to generate an execution result of the validation instruction further includes:
acquiring data flow information of the verification instruction when the verification instruction runs in the CPU by using the probe so as to monitor the processing process of the CPU;
Wherein before inputting the verification instruction into the CPU, further comprises:
Disabling an optimization option of the compiler to avoid the compiler from optimizing the validation instruction; and
Inputting the verification instruction into a compiler to convert the verification instruction into a binary instruction which can be identified by a CPU;
the acquisition verification instruction comprises the following steps:
selecting code information of one or more program structures from a preset verification code set; and
A subset of instructions is generated based on the code information for each program structure to form a validation instruction for validating the memory barrier.
2. The method of claim 1, wherein the program structure comprises one or more of the following types:
a sequence structure, a circulation structure, a judgment structure, a queue structure, a stack structure, a tree structure, a graph structure and a nested structure, wherein the graph structure comprises an undirected graph structure and a directed graph structure.
3. The method according to claim 1, wherein the method further comprises:
and performing pressurization detection on the CPU to judge the validity of the memory barrier instruction when the pressure is set.
4. The method of claim 3, wherein the performing a pressurization test on the CPU to determine the validity of the memory barrier instruction at a set pressure comprises:
detecting the load pressure of the CPU to judge whether the load pressure is larger than a set pressure or not; and
And in response to the load pressure being lower than a set pressure, raising the load pressure of the CPU to raise the load pressure of the CPU to the set pressure.
5. An apparatus for verifying the validity of a memory barrier instruction, comprising:
A processor; and
A memory storing computer instructions for verifying memory barrier instruction validity, which when executed by the processor cause the apparatus to perform the method of any one of claims 1-4.
6. A computer readable storage medium having stored thereon computer readable instructions for verifying memory barrier instruction validity, which when executed by one or more processors, implement the method of any of claims 1-4.
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