CN114518884A

CN114518884A - Method and device for repairing weak memory order problem

Info

Publication number: CN114518884A
Application number: CN202011303988.0A
Authority: CN
Inventors: 余狄; 吕研冬; 张汝涛
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2020-11-19
Filing date: 2020-11-19
Publication date: 2022-05-20
Also published as: EP4231138A1; US20230289187A1; WO2022105492A1

Abstract

The application discloses a method and a device for repairing a weak memory order problem, and relates to the technical field of computers. The method comprises the following steps: determining a read-write instruction set in a code to be repaired; classifying the instructions in the read-write instruction set to determine a target instruction; inserting a memory barrier instruction between a previous read-write instruction of the target instruction and the target instruction; the read-write instruction set comprises read instructions and/or write instructions in the codes to be repaired, and the instructions in the read-write instruction set are used for accessing the memory.

Description

Method and device for repairing weak memory order problem

Technical Field

The present application relates to the field of computer technologies, and in particular, to a method and an apparatus for repairing a weak memory problem.

Background

When a multithread program developed based on a non-weak memory model runs in a computer device adopting a weak memory model (weak memory model), because instruction semantics supported by hardware under different memory models are different, threads running in parallel in the program may be out of order when executing read-write instructions for memory access, and the problem of weak memory order occurs.

For example, a multithread program developed based on a strong memory model (strong memory model) may have a problem of weak memory order when a read/write instruction for access is executed by a thread running in parallel in the program when the program runs in a computer device adopting a weak memory model. In this way, the function to be implemented by the program may be logically incorrect, resulting in inaccurate output results after the program is run.

Therefore, how to repair the weak memory order of the multi-thread program is a technical problem to be solved urgently.

Disclosure of Invention

The application provides a method and a device for repairing a weak memory problem, wherein the method can automatically repair the weak memory problem in a multi-thread program in a compiling stage of the program.

In order to achieve the above purpose, the present application provides the following technical solutions:

in a first aspect, the present application provides a method for repairing a weak memory order problem, the method comprising: and determining a read-write instruction set in the code to be repaired. And classifying the instructions in the read-write instruction set to determine a target instruction. And inserting a memory barrier instruction between a read-write instruction which is before the target instruction and the target instruction. The read-write instruction set comprises read instructions and/or write instructions in the codes to be repaired, and the instructions in the read-write instruction set are used for accessing the memory.

By the method, the target instruction can be determined by classifying the instruction to be repaired. Then, a memory barrier instruction is inserted before the target instruction, so that the target instruction can be executed according to the sequence required by the program, and the problem of automatically repairing the weak memory sequence of the multi-thread program is solved. The method provided by the embodiment of the application can automatically repair the weak memory order problem of the multi-thread program, and greatly improves the efficiency of repairing the weak memory order problem of the program.

In a possible design manner, the "classifying the instructions in the read-write instruction set to determine the target instruction" specifically includes: determining a first type of instruction in the read-write instruction set; according to the first class of instructions, a target instruction is determined. Wherein the instructions in the first class of instructions are weak memory order security instructions. The target instruction is an instruction in the read-write instruction set other than the first type of instruction.

In another possible design, the "determining a target instruction according to a first type of instruction" specifically includes: determining a target instruction set based on the first class of instructions; a target instruction is determined in the set of target instructions based on an optimization policy. The target instruction set comprises all instructions except the first type of instruction in the read-write instruction set. The optimization strategy is used for indicating the type of the read-write instruction which needs to repair the weak memory order problem.

In another possible design, the optimization strategy includes at least one of the following strategies: the method comprises the steps that a first strategy is used for determining read-write instructions belonging to a white list in a target instruction set as target instructions; or, determining the read-write instruction except the read-write instruction in the blacklist in the target instruction set as the target instruction. And determining the read-write instruction with the context dependency relationship in the target instruction set as the target instruction only as the dependent read-write instruction by the second strategy. And determining the read-write instructions in the target instruction set except the read-write instructions related to the special register as the target instructions according to the third strategy. And determining the read-write instructions in the target instruction set except the read-write instructions related to the input and output parameters as the target instructions according to the fourth strategy.

In another possible design, the first type of instruction includes: at least one of an instruction for reading and writing non-shared variables between threads or a read and write instruction with order-preserving semantics.

Through the several possible designs, the first type of safe instruction without weak memory order problem can be accurately identified, and the target instruction is determined by excluding the first type of instruction. By the method, the read-write instructions which do not need to be repaired in the codes to be repaired can be quickly eliminated, so that the insertion of unnecessary memory barrier instructions can be reduced to the maximum extent, and the running performance of the repaired multithread program is improved.

In addition, through the optimization strategy, the insertion of unnecessary memory barrier instructions can be further reduced, so that the running performance of the repaired multithreading program is further improved.

In another possible design manner, the "classifying the instructions in the read-write instruction set to determine the target instruction" specifically includes: and classifying the instructions in the read-write instruction set based on the optimization strategy to determine a target instruction. The optimization strategy is used for indicating the type of the read-write instruction needing to repair the weak memory order problem.

Through the possible implementation mode, the read-write instruction which needs to be inserted into the memory barrier instruction can be determined in the read-write instruction set through the optimization strategy, so that the insertion of unnecessary memory barrier instructions can be reduced, and the running performance of the repaired multithread program is improved.

In another possible design, the method further includes: and acquiring a fifth strategy configured by the user. This fifth strategy is added to the optimization strategy described above.

Here, the fifth policy may be a user-custom configured policy. Therefore, through the possible design, the method and the device allow the codes to be repaired through the strategy configured by the user in a user-defined mode, and therefore the flexibility of application of the method and the device is improved.

In another possible design, before the "determining the target instruction," the method further includes: and receiving indication information, wherein the indication information is used for indicating a user to select the optimization strategy from the optimization strategies to be selected.

Here, the candidate optimization strategy may be an optimization strategy preset by the repair apparatus. Therefore, through the possible design mode, a user can freely select the optimization strategy for repairing the code to be repaired from the optimization strategies to be selected, and the application flexibility of the method is improved.

Through the possible implementation mode, the user can customize the configuration optimization strategy, so that the flexible application of the method is realized.

In another possible design, the "determining a read-write instruction set" specifically includes: and identifying the instruction in the target function to determine the read-write instruction set. The target function is any one of the above codes to be repaired.

Through the possible design, the method can identify and repair the weak memory order problem in the code to be repaired by taking the function as a unit, so that the method can be applied to repairing the weak memory order problem of the large-scale multi-thread program, and the practicability of the method is further improved.

In another possible design, the code to be repaired is an intermediate language obtained by compiling the source code of the multi-threaded program by a compiler.

In another possible design, the code to be repaired is assembly code obtained by compiling source code of a multi-thread program by a compiler.

Through the two possible designs, the method for repairing the weak memory order problem can be synchronously executed with the source code compiling of the multi-thread program, so that the weak memory order problem of the multi-thread program is automatically repaired, and the efficiency of repairing the weak memory order problem of the multi-thread program is improved.

In a second aspect, the present application provides an apparatus for repairing weak memory order problems.

In one possible design, the apparatus is configured to perform any one of the methods provided in the first aspect above. The present application may divide the functional modules of the apparatus according to any one of the methods provided by the first aspect. For example, the functional blocks may be divided for the respective functions, or two or more functions may be integrated into one processing block. Illustratively, the present application may divide the apparatus into a determination unit, an insertion unit, and the like according to functions. The above description of possible technical solutions and beneficial effects executed by each divided functional module may refer to the technical solutions provided by the first aspect or the corresponding possible designs thereof, and will not be described herein again.

In another possible design, the apparatus for repairing weak memory order problem includes: the memory is coupled to the one or more processors. The memory is for storing computer instructions which the processor is adapted to invoke in order to perform any of the methods as provided by the first aspect and any of its possible designs.

In a third aspect, the present application provides a computer-readable storage medium, such as a computer non-transitory readable storage medium. A computer program (or instructions) stored thereon, which, when run on an apparatus for repairing weak memory ordering problems, causes the apparatus for repairing weak memory ordering problems to perform any of the methods provided by any of the possible implementations of the first or second aspect described above.

In a fourth aspect, the present application provides a computer program product which, when run on an apparatus for repairing weak memory ordering problems, causes any of the methods provided by any of the possible implementations of the first aspect to be performed.

In a fifth aspect, the present application provides a chip system, comprising: and the processor is used for calling and running the computer program stored in the memory from the memory and executing any one of the methods provided by the implementation mode in the first aspect.

It is understood that any one of the apparatuses, computer storage media, computer program products, or chip systems provided above can be applied to the corresponding methods provided above, and therefore, the beneficial effects achieved by the apparatuses, the computer storage media, the computer program products, or the chip systems can refer to the beneficial effects in the corresponding methods, and are not described herein again.

In the present application, the names of the above-mentioned apparatuses for repairing weak memory order problems do not limit the devices or functional modules themselves, and in actual implementation, the devices or functional modules may appear by other names. Insofar as the functions of the respective devices or functional modules are similar to those of the present application, they fall within the scope of the claims of the present application and their equivalents.

These and other aspects of the present application will be more readily apparent from the following description.

Drawings

FIG. 1 is a diagram illustrating a prior art process for compiling program source code into machine executable program code;

fig. 2 is a schematic hardware structure diagram of a computing device according to an embodiment of the present disclosure;

fig. 3 is a schematic flowchart of a method for repairing a weak memory problem according to an embodiment of the present disclosure;

fig. 4a is a schematic diagram illustrating that a repair apparatus according to an embodiment of the present application obtains an optimization policy selected by a user from optimization policies to be selected based on a graphical interaction interface;

FIG. 4b is a flowchart illustrating another method for repairing weak memory order problem according to an embodiment of the present disclosure;

fig. 5 is a schematic structural diagram of a repair apparatus according to an embodiment of the present disclosure;

fig. 6 is a schematic structural diagram of a chip system according to an embodiment of the present disclosure;

fig. 7 is a schematic structural diagram of a computer program product provided in an embodiment of the present application.

Detailed Description

For a clearer understanding of the embodiments of the present application, some terms or techniques referred to in the embodiments of the present application are described below:

1) compiler, compiler and program

Compilers are commonly used to translate "one language" into "another language". For example, program source code developed by a developer in a high-level computer language (e.g., C language, C + + language, etc.) is translated into machine language code (e.g., binary code) that a machine can recognize and run, as required.

In general, a compiler may integrate assembly functions. In this way, the compiler can compile the program source code processed by the preprocessor into the assembly code. The assembly code is assembly language code. The assembly code is then compiled into object code by an assembly function. The object code is a language code that can be recognized by the machine, and is a binary code, for example. In this way, the object code combines the machine language programs independently assembled in the object code via a linker (linker) to obtain a machine executable program code.

Optionally, in order to improve the compiling effect, the compiler compiles the program source code processed by the preprocessor into an intermediate language before compiling the program source code into an assembly code. The intermediate language is generated by analyzing the preprocessed program source code by the compiler, and is used for optimizing the compiler to compile and obtain the target code.

By way of example, referring to FIG. 1, FIG. 1 illustrates a process diagram for compiling program source code into machine executable program code.

As shown in fig. 1, a program source code is processed by a preprocessor 11 and then input to a compiler 12. The sub-compiler 121 of the compiler 12 may compile the preprocessed program source code into assembly code and output it. Next, the assembler 122 assembles and compiles the assembly code output by the sub-compiler 121 to obtain the object code. The object code is a code that can be recognized by the machine. Finally, the object code is processed by the linker 13, and then the executable program which can be run by the machine can be obtained.

After the sub-compiler 121 parses the preprocessed program source code, an intermediate language may be generated. The sub-compiler 121 may further compile the intermediate language to obtain the assembly code shown in fig. 1.

2) Multithread program

An instance of a program that is running is often referred to as a process. A process may include at least one thread, which refers to a single sequential control flow in the process. Typically, multiple threads may be concurrent in a process, and may be run in parallel by multiple processing cores in a computer device to perform different tasks. Of course, there may be only one thread in one process, and this is not limited.

Thus, a multi-threaded program refers to a program that includes multiple threads in one process of the program during execution.

3) Other terms

In the embodiments of the present application, words such as "exemplary" or "for example" are used to mean serving as an example, instance, or illustration. Any embodiment or design described herein as "exemplary" or "e.g.," is not necessarily to be construed as preferred or advantageous over other embodiments or designs. Rather, use of the word "exemplary" or "such as" is intended to present concepts related in a concrete fashion.

In the embodiments of the present application, the terms "first", "second" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present application, "a plurality" means two or more unless otherwise specified.

The term "at least one" in this application means one or more, and the term "plurality" in this application means two or more, for example, the plurality of second messages means two or more second messages. The terms "system" and "network" are often used interchangeably herein.

It should also be understood that the term "and/or" as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items. The term "and/or" is an associative relationship that describes an associated object, meaning that three relationships may exist, e.g., A and/or B, may mean: a exists alone, A and B exist simultaneously, and B exists alone. In addition, the character "/" in the present application generally indicates that the former and latter related objects are in an "or" relationship.

It should also be understood that, in the embodiments of the present application, the sequence numbers of the respective processes do not mean the execution sequence, and the execution sequence of the respective processes should be determined by the functions and the inherent logic thereof, and should not constitute any limitation to the implementation process of the embodiments of the present application.

It should be understood that determining B from a does not mean determining B from a alone, but may also be determined from a and/or other information.

It will be further understood that the terms "comprises," "comprising," "includes," and/or "including," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

It should be appreciated that reference throughout this specification to "one embodiment," "an embodiment," "one possible implementation" means that a particular feature, structure, or characteristic described in connection with the embodiment or implementation is included in at least one embodiment of the present application. Thus, the appearances of the phrases "in one embodiment" or "in an embodiment" or "one possible implementation" in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

It should be understood that threads running in parallel in a multi-thread program are control flows independent of each other, but there may be a logical relationship between instructions used to access a memory (for simplicity of description, the embodiments of the present application will simply refer to "accessing a memory" as "accessing a memory") in different threads. Here, the instruction for accessing generally includes a read instruction and/or a write instruction.

As an example, in a multi-threaded program developed based on a non-weak memory model, a write instruction 1 for access in the first thread is used to write (store) the value 0 in register 1 to memory. And a read instruction 2 for accessing in the second thread is used for reading (load) the value 0 from the memory to the register 2. Therefore, there is a logical sequential relationship between the write command 1 and the read command 2, that is, after the write command 1 writes the value 0 of the register 1 into the memory, the read command 2 can read the value 0 in the memory into the register.

When a first thread and a second thread of the multi-threaded program are run in parallel by two processing cores of a computer device employing a weak memory model, if a write instruction 1 is executed before a read instruction or a write instruction in the first thread before the write instruction 1, this may cause the write instruction 1 to be executed later than the read instruction 2 in the second thread. When the write instruction 1 is executed later than the read instruction 2 in the second thread, the read instruction 2 in the second thread is executed, and the memory is empty, i.e. the value 0 in the register 1 has not been written into the memory. In this way, a logical error occurs in the tasks executed by the first thread and the second thread, which may cause program crash or result in inaccurate output result. This situation, known as write instruction 1 in the first thread, creates a weak memory order problem.

Generally, when a thread of a program is running, situations in which weak memory ordering may occur include: read (loadload), write (store), read and write (loadstore), and write and read (store). I.e. the execution order of the two read instructions is reversed, the execution order of the two write instructions is reversed, the execution order of the read and write instructions is reversed, and the execution order of the write and read instructions is reversed. Here, the reversal of the instruction execution order means that the instruction execution order is opposite to the execution order required by the program itself.

For the weak memory order problem, a memory barrier instruction may be inserted before the access instruction to ensure that the two access instructions can be executed according to the sequence required by the program.

For example, in program 1 developed based on the non-weak memory model, the normal execution order of instruction 1 for memory access and instruction 2 for memory access is "instruction 1 → instruction 2". When program 1 is running in a computer device that employs a weak memory model, a weak memory problem may arise between instruction 1 and instruction 2. At this time, a memory barrier instruction may be inserted between instruction 1 and instruction 2, so that it is ensured that instruction 1 and instruction 2 may be executed in the order of "instruction 1 → instruction 2" when program 1 is run in a computer device using a weak memory model.

However, in conventional approaches, the determination of the location in a program where a memory barrier instruction needs to be inserted is typically determined empirically by a developer. When the scale of the procedure is large, the efficiency of the process is extremely low.

Based on this, embodiments of the present application provide a method for repairing a weak memory order problem, which is applied to an apparatus for repairing a weak memory order problem (for convenience of description, an "apparatus for repairing a weak memory order problem" is referred to as a "repairing apparatus" hereinafter in embodiments of the present application). The method identifies the code to be repaired to determine a read-write instruction set in the code to be repaired, wherein the read-write instruction set comprises read-write instructions for access and storage. Then, the repairing device classifies the read-write instructions in the read-write instruction set based on the determined read-write instruction set so as to determine a target instruction needing to be inserted into the memory barrier. And finally, inserting a memory barrier instruction before the target instruction, thereby realizing the automatic repair of the weak memory order problem of the code to be repaired and greatly improving the efficiency of repairing the weak memory order problem of the code to be repaired.

The code to be repaired may be an intermediate language obtained by compiling a multi-thread program source code by a compiler, or an assembly code obtained by compiling by a compiler, which is not specifically limited in this embodiment of the application.

The multithread program source code may be a program source code developed in a high-level computer language such as C, C + + or Fortran, and the embodiment of the present application is not particularly limited thereto.

The embodiment of the present application further provides a repair apparatus, where the repair apparatus may be applied to any computing device with computing processing capability, where the computing device may be a general-purpose computer or a server, and this is not specifically limited in this embodiment of the present application.

Referring to fig. 2, fig. 2 shows a hardware structure diagram of a computing device 20 according to an embodiment of the present application. The above-mentioned apparatus for repairing the memory access problem can be applied to the computing device 20. As shown in fig. 2, computing device 20 includes a processor 21, a memory 22, a communication interface 23, an input-output interface 24, and a bus 25. The processor 21, the memory 22, the communication interface 23, and the input/output interface 24 may be connected by a bus 25.

The processor 21 is a control center of the computing device 20, and may be a Central Processing Unit (CPU), other general-purpose processors, or the like. Wherein a general purpose processor may be a microprocessor or any conventional processor or the like.

As one example, processor 21 may include one or more CPUs, such as CPU 0 and CPU 1 shown in fig. 2. Wherein, CPU 0 and CPU 1 can run two threads of the multithread program in parallel.

The memory 22 may be, but is not limited to, a read-only memory (ROM) or other type of static storage device that may store static information and instructions, a Random Access Memory (RAM) or other type of dynamic storage device that may store information and instructions, an electrically erasable programmable read-only memory (EEPROM), a magnetic disk storage medium or other magnetic storage device, or any other medium that can be used to carry or store desired program code in the form of instructions or data structures and that can be accessed by a computer.

In one possible implementation, the memory 22 may exist independently of the processor 21. Memory 22 may be coupled to processor 21 via bus 25 for storing data, instructions, or program code. The method for repairing the access disorder problem provided by the embodiment of the present application can be implemented when the processor 21 calls and executes the instructions or program codes stored in the memory 22.

In another possible implementation, the memory 22 may also be integrated with the processor 21.

A communication interface 23, configured to connect the computing device 20 and other devices (such as network nodes in a public cloud, etc.) through a communication network, where the communication network may be an ethernet, a Radio Access Network (RAN), a Wireless Local Area Network (WLAN), etc. The communication interface 23 may include a receiving unit for receiving data, and a transmitting unit for transmitting data.

An input/output interface 24 for enabling human-computer interaction with the computing device 20. The input/output interface 24 may be a mouse, a keyboard, a touch screen, etc., but is not limited thereto.

As an example, a user may submit a blacklist or whitelist, etc. to a computing device based on an input-output interface.

The bus 25 may be an Industry Standard Architecture (ISA) bus, a Peripheral Component Interconnect (PCI) bus, an Extended ISA (enhanced Industry Standard Architecture) bus, or the like. The bus may be divided into an address bus, a data bus, a control bus, etc. For ease of illustration, only one thick line is shown in FIG. 2, but it is not intended that there be only one bus or one type of bus.

It should be noted that the configuration shown in FIG. 2 does not constitute a limitation of the computing device 20, and that the computing device 20 may include more or less components than those shown, or some components in combination, or a different arrangement of components than those shown in FIG. 2.

The following describes a method for repairing a weak memory problem according to an embodiment of the present application with reference to the accompanying drawings.

Referring to fig. 3, fig. 3 is a flowchart illustrating a method for repairing a weak memory order problem according to an embodiment of the present application. The method may be applied to a prosthetic device as shown in fig. 2. The method may comprise the steps of:

s101, the repairing device determines a read-write instruction set.

Specifically, the repair device may determine the read-write instruction set in the code to be repaired, where the read-write instruction set includes a read instruction and/or a write instruction in the code to be repaired, and an instruction in the read-write instruction set is used for accessing and storing.

For example, a read command "ldr x1, [ x0 ]" indicates reading a value from the memory address pointed to by general register x0 and writing the value to general register x 1. As another example, a write instruction "str x1, [ x0 ]", indicates that the value in general register x1 is to be written to the memory address pointed to by general register x 0.

For simplicity, in the following description, the "read instruction and/or write instruction" is simply referred to as "read-write instruction" in the embodiments of the present application.

The code to be repaired may be an intermediate language obtained by compiling a source code of the multi-thread program by a compiler. Alternatively, the code to be repaired may also be assembly code obtained by compiling a source code of a multi-threaded program by a compiler, which is not specifically limited in this embodiment of the present application. Here, the description of the compiler and the intermediate language may refer to the above description, and is not repeated here.

Optionally, the code to be repaired may also be a module to be repaired in the source code of the multi-thread program, and the intermediate language is obtained by compiling the code by the compiler. Alternatively, the code to be repaired may also be a module to be repaired in a source code of the multi-thread program, and the compiler compiles the obtained assembly code, which is not specifically limited in this embodiment of the present application.

The module to be repaired may be one of a plurality of modules obtained by dividing a source code of the multithread program by a developer. Or, the module to be repaired may be one of a plurality of modules obtained by dividing the source code of the multi-threaded program by the preprocessor or the compiler. The embodiments of the present application do not limit this.

The source code of the multi-thread program may be divided according to the functions or purposes that the code can realize, but is not limited thereto.

The source code of the multithread program is divided into a plurality of modules, wherein the plurality of modules comprise a safety module and a non-safety module. The security module refers to a read-write instruction obtained by compiling a source code in the module, and the problem of weak memory order cannot be caused. The non-secure module refers to a problem that a read-write instruction obtained by compiling a source code in the module can generate a weak memory order. Therefore, the non-secure module is the module to be repaired.

Optionally, the security module may determine that it does not generate the weak memory order problem through a large number of running tests, which is not particularly limited.

Specifically, the repairing device may determine the read-write instruction in the code to be repaired by identifying an instruction in the code to be repaired, so as to obtain a read-write instruction set corresponding to the code to be repaired.

In a possible implementation manner, the repairing apparatus may identify the instruction in the target function by taking a function in the code to be repaired as a unit, so as to determine the read-write instruction in the target function, thereby obtaining a read-write instruction set corresponding to the target function. The target function is any one of the codes to be repaired. It should be understood that the code to be repaired is composed of at least one function.

Specifically, the repairing device may traverse each instruction in the objective function, and identify each instruction in the objective function to determine the read-write instruction in the objective function, so as to obtain the read-write instruction set corresponding to the objective function.

Therefore, after the repairing device identifies the instruction in each function in the code to be repaired, the read-write instruction set corresponding to each function can be determined. The set of the read-write instruction set corresponding to each function includes all the read-write instructions in the code to be repaired.

It can be seen that, when the read-write instruction set is determined in this way, each function in the code to be repaired may correspond to one read-write instruction set, that is, the functions in the code to be repaired correspond to the determined read-write instruction sets one to one. Or, the code to be repaired may also correspond to a read-write instruction set, in this case, the read-write instruction set may be obtained by aggregating, by the repair device, the read-write instruction sets determined based on each function, which is not specifically limited in this embodiment of the present application.

In another possible implementation manner, the repair device may traverse the instruction in the code to be repaired, and identify the instruction in the code to be repaired to determine the read-write instruction in the code to be repaired, so as to obtain the read-write instruction set corresponding to the code to be repaired.

It can be seen that when the read-write instruction set is determined in this way, the code to be repaired corresponds to one read-write instruction set.

S102, the repairing device determines a first type of instruction based on the read-write instruction set.

The repair apparatus may determine the first type of instruction in the read-write instruction set based on the determined read-write instruction set. Here, the instructions in the first class of instructions do not cause weak memory order problems, i.e., the first class of instructions are weak memory order safe instructions.

The instruction in the first type of instruction may be an instruction that does not cause a weak memory order problem, or may be an instruction that does not cause a weak memory order problem in a preset context, which is not limited herein.

Optionally, the first type of instruction may include at least one of an instruction for reading and writing an unshared variable between threads, or a read and write instruction with order-preserving semantics.

Among them, the inter-thread non-shared variable is a variable dedicated within one thread (for example, the first thread), and the variable is not called by the threads except the first thread. Thus, weak memory problems are not typically generated for instructions that read and write such variables.

For example, the instruction for reading and writing the non-shared variable between threads may include at least one of an instruction for reading and writing a local variable or a read local instruction.

For the read-write instruction with order-preserving semantics, the semantics of the read-write instruction enable the read-write instruction to be executed without the problem of weak memory order.

S103, the repairing device determines a target instruction set according to the first type of instructions and determines target instructions in the target instruction set.

The instructions in the target instruction set are all the instructions except the first type of instructions in the read-write instruction set. Thus, the repairing device can determine the target instruction set in the read-write instruction set according to the determined first type of instruction.

Further, the repair apparatus may determine the target instruction in the target instruction set.

In one possible implementation, the repair device may determine all instructions in the target instruction set as target instructions. That is, the repair means repairs all of the instructions in the target instruction set.

In another possible implementation, the repair apparatus may determine the target instruction in the target instruction set based on at least one of the following optimization strategies. The optimization strategy is used for indicating the read-write instruction type needing to repair the weak memory order problem.

The repair device may preset the optimization policy, and the repair device may also obtain the optimization policy configured by the user when the repair of the code to be repaired is started, which is not limited to this.

The optimization strategy may include, among other things, a first strategy-a fourth strategy described below. It is understood that the first policy-the fourth policy are only exemplary, and the embodiments of the present application are not limited thereto.

In one case, when the optimization policy is an optimization policy pre-configured by a user, the user may submit the optimization policy to the repair apparatus through an input/output interface of the computing device and by using any one of a graphical interactive interface, a command line insertion or a configuration file setting mode. In response, the repair device may obtain an optimization policy configured by a user, and determine a target instruction based on the obtained optimization policy when repairing the code to be repaired.

For example, the user submits the optimization policy to the repair apparatus through an input/output interface of the computing device by setting a configuration file. In general, a user may place a pre-configured optimization policy file in a root directory of a repair device and modify a suffix format of the file, thereby implementing a configuration file for setting an optimization policy in the repair device. In this way, when the repairing apparatus executes the method provided by the embodiment of the present application, the target instruction may be determined in the target instruction set according to the optimization policy indicated by the configuration file, and the target instruction may be repaired.

Of course, the optimization policy may further include a fifth policy configured by the user in a customized manner based on the user's own needs, which is not limited in this embodiment of the application.

In this case, the repair apparatus may acquire a fifth policy custom-configured by the user in advance, and add the fifth policy to the optimization policy described above. In this way, the repair apparatus can determine the target instruction based on the optimization policy including the fifth policy when repairing the code to be repaired. Here, the process of the repairing apparatus obtaining the user-defined configured fifth policy in advance may refer to the description above of the repairing apparatus obtaining the optimization policy configured in advance by the user, and is not described herein again.

In another case, the above-mentioned optimization strategy is preset in the prosthetic device. In this way, the repair device may determine the target instruction in the process of repairing the code to be repaired according to the preset optimization strategy, and certainly, the repair pre-installation may also use the preset optimization strategy as the candidate optimization strategy, so that the repair device may receive the indication information input by the user when the repair of the code to be repaired is started, and determine the target instruction based on the optimization strategy indicated by the indication information. Here, the indication information is used to indicate an optimization policy selected by the user from the optimization policies to be selected.

It should be understood that the preset optimization policy in the repair apparatus may include a fifth policy of the user-defined configuration that is obtained by the repair apparatus in advance, and of course, the repair apparatus may also obtain the fifth policy of the user-defined configuration when repairing the code to be repaired, which is not limited in this respect. The following description will take the fifth policy of obtaining the user-defined configuration when the repair apparatus repairs the code to be repaired as an example.

Illustratively, referring to fig. 4a, fig. 4a shows a schematic diagram of the repairing apparatus acquiring, based on the graphical interactive interface, the optimization strategy selected by the user from the optimization strategies to be selected. As shown in fig. 4a (a), the repairing apparatus may display options through a dialog 411 on a display interface 41 (e.g., a display) of the computing device when starting to prepare to repair the code to be repaired or when starting to compile the source code of the multi-threaded program: the method comprises the steps of selecting options such as a first strategy, a second strategy, a third strategy, a fourth strategy, a user-defined optimization strategy and the like so as to realize the optimization strategy which is required to be used when a user is inquired to repair the code to be repaired. Wherein the first policy, the second policy, the third policy, and the fourth policy are optimization policies preset by the repair apparatus. The user-defined optimization strategy is an optimization strategy needing immediate submission by a user.

As shown in fig. 4a (a), when the user selects the options "first policy" and "second policy" by controlling the mouse (or keyboard), the indication information indicating the "first policy" and the "second policy" is sent to the repair apparatus, so that the repair apparatus can determine the optimization policies selected by the user as the "first policy" and the "second policy" based on the indication information. In this way, the repair device can determine the target instruction in the target instruction set based on the optimization strategy selected by the user and repair the target instruction.

As shown in fig. 4a (b), when the user selects the option "custom optimization policy" by controlling the mouse (or keyboard), the user may upload the policy configured by the user in advance in the dialog box 412 shown in fig. 4a (c) by controlling the mouse (or keyboard). For example, the user may first find the storage directory "Aa/bb/cc/" of the custom-configured policy by clicking the "browse" icon by operating a mouse (or keyboard). Then, the user can upload the user-defined configured policy by clicking an "upload" icon by operating a mouse (or a keyboard). In response, the prosthetic device receives the custom configured policy uploaded by the user. In this way, the repair device can determine the target instruction in the target instruction set based on the custom configured policy and repair it.

Therefore, the method provided by the embodiment of the application is more flexible in application by allowing the user to customize the configuration strategy and allowing the user to freely select the optimization strategy from the optimization strategies to be selected.

It should be understood that the repairing device obtains the optimization strategy configured by the user before the technical solution described in the embodiment of the present application is executed. In this way, the repair device can repair the read-write instruction of the type indicated by the optimization strategy through the configured optimization strategy in the process of executing the method provided by the embodiment of the application.

The following exemplary first strategy-fourth strategy is described:

the first strategy is as follows: the repair apparatus may determine the read/write instruction belonging to the white list in the target instruction set as the target instruction, or the repair apparatus may determine the read/write instruction except the read/write instruction in the black list in the target instruction set as the target instruction.

The white list and the black list may be a black list and a white list of functions in the code to be repaired, or may be a black list and a white list of different functional modules in the code to be repaired, which is not limited herein.

In the following, the white list and the black list are the black list and the white list of the function in the code to be repaired, for example.

The blacklist of functions generally includes functions such as security functions and/or hotspot functions in the code to be repaired.

Here, the security function may be, in general, a function in which a weak memory problem does not occur after an executable program obtained by ordinary compilation is executed, or the security function may be a function that does not include a shared variable in a source code, and the like, which is not limited thereto. Since the security function does not usually cause weak memory problem, the repair device does not need to repair the security function for the weak memory problem.

Hot spot functions are typically functions that are frequently called by programs. For example, if the number of times that the function a is called by the program is greater than or equal to the preset threshold, the function a is a hotspot function. Since the repair of the weak memory problem for an instruction is accomplished by inserting a memory barrier instruction before the instruction. Therefore, for the hot function, since the hot function is frequently called, when a memory barrier instruction is inserted into the hot function, the running performance of the program may be reduced. Therefore, the repairing device does not repair the hot spot function with the weak memory order problem.

Of course, the hot function in the function blacklist may also be the hot function determined in advance by the above-mentioned method for determining the security function, which does not have the weak memory order problem.

The function white list generally includes functions of the code to be repaired, except for the hot spot function and/or the security function. For this type of function, the repair device can repair it for weak memory ordering problems.

It should be understood that the repair apparatus may preset the function blacklist and/or the function whitelist, and the repair apparatus may also obtain the function blacklist and/or the function whitelist configured by the user in advance, which is not limited in this respect.

When the function blacklist and/or the function whitelist are configured by the user in advance, the user can submit the function blacklist and/or the function whitelist configured in advance to the repair device through any one of the input and output interfaces of the computing device, the graphical interactive interface, the command line insertion or the configuration file setting mode and the like. In response, the repair device may obtain the function blacklist and/or the function whitelist configured by the user. Here, the process of acquiring the function blacklist and/or the function whitelist configured by the user by the repair device may refer to the description of the process of acquiring the user-defined optimization policy by the repair device, and is not described in detail again.

The second strategy is as follows: the repair apparatus may determine, as the target instruction, only the dependent read/write instruction from among the read/write instructions having the context dependency in the target instruction set.

Optionally, the repairing apparatus may analyze the instruction in the target instruction set, and determine the read-write instruction only as a dependency according to the context dependency of the read-write instruction in the target instruction set. Here, the read/write instruction that is merely dependent means an instruction that is independent of other read/write instructions in the target instruction set.

By way of example, if the target instruction set includes the following instructions:

instruction 1: ldr x0, [ s1 ];

instruction 2: str x0, [ s2 ];

here, instruction 1 "ldr x0, [ s1 ]" indicates a read from the memory address indicated by register s1 to register x 0. Instruction 2 "str x0, [ s2 ]" indicates that the value in register x0 is written to the memory address indicated by register s 2. It can be seen that when instruction 1 is not executed, i.e. the value in register x0 is not read from the memory address indicated by register s1, then instruction 2 cannot be executed to write the value in register x0 to the memory address indicated by register s 2. That is, instruction 1 and instruction 2 are instructions having a dependency relationship, and instruction 1 is a dependency of instruction 2. I.e., the execution of instruction 2, depends on the execution of instruction 1. In this case, when the execution of instruction 1 is not dependent on other read/write instructions in the target instruction set, the repair apparatus may determine that instruction 1 is a read/write instruction that is only dependent.

For read and write instructions that have context dependencies and depend on execution of other instructions, weak memory ordering problems typically do not occur for such instructions. Therefore, the repair facility may not generally repair such instructions.

The third strategy is as follows: the repair apparatus may determine a read-write instruction other than the read-write instruction relating to the special register in the target instruction set as the target instruction.

Where a special purpose register is typically a register used only for a particular instruction or occasion. For example, the special purpose register may be a floating point register. Here, the floating point register is a register for storing a floating point number.

For example, if the special-purpose register is a floating-point register, the repair apparatus may determine whether the register is a floating-point register by identifying the name of the register in the read/write instruction. When the register in the read-write instruction is a floating-point register, the repair apparatus may determine that the read-write instruction is a read-write instruction for operating the floating-point register.

Since the special registers are not typically used to read and write global control variables, read and write instructions that operate on special registers do not typically create the problem of weak memory ordering. Therefore, the repair apparatus may not usually repair a read/write instruction that operates on a special register.

The fourth strategy is as follows: the repair apparatus may determine, as the target instruction, a read-write instruction other than the read-write instruction related to the input-output parameter in the target instruction set.

The input and output parameters comprise parameters needing to be input when the function is called and return values of the function.

Illustratively, when general register x0 is a register used to store the return value of a function, if the instructions in the target instruction set are as follows:

B malloc；

str x11,[x0]；

wherein, "B" represents an instruction whose instruction class phase is a call function, and "malloc" is a function name for applying for memory. The instruction "B malloc" indicates that the function malloc is called. When the function "malloc" is executed, the memory address returned by "malloc" will be written to general register x 0. At this point, the instruction "Str x11, [ x0 ]" is used to indicate that the value in register "x 11" is written to the memory address indicated by general register x0, which is the memory address returned for "malloc". In this case, the instruction "str x11, [ x0 ]" is a read/write instruction relating to the input/output parameter.

Generally, in a scenario like this, as for the read/write instruction related to the input/output parameter, the weak memory order problem does not occur, so the repair apparatus may not repair it.

It should be noted that, when the repair apparatus determines the target instruction based on the fourth policy, the target instruction may also be determined based on a context logic relationship of instructions in the target instruction set, which is not described in detail herein.

It should be noted that, when the optimization policy adopted by the repair apparatus is any combination policy of the first policy to the fourth policy, the repair apparatus may preset priorities of a plurality of policies in the combination policy. Thus, when the same read-write instruction produces opposite results based on two different policies, the repair device can process the read-write instruction through the policy with the higher priority based on the priority. Wherein the priority is used to indicate the priority level of the policy, and the policy with high priority level is used in preference to the policy with low optimization level.

Illustratively, when the combination policy is the second policy and the third policy, if the instruction 1 is an instruction that is only a dependency, the repairing apparatus should repair the instruction 1 according to the instruction of the second policy. Meanwhile, if the instruction 1 is an instruction for reading and writing the floating-point register, the repairing device should not repair the instruction 1 according to the instruction of the third strategy. In this case, different ones of the combination strategies produce opposite results on the same instruction. At this time, if the priority of the second policy is higher than the third policy in the combination policies, the repair device determines instruction 1 as the target instruction based on the second policy and repairs it.

S104, the repairing device inserts a memory barrier instruction between the read-write instruction before the determined target instruction and the target instruction.

After the repair device determines the target instruction, a memory barrier instruction is inserted between the read-write instruction before the determined target instruction and the target instruction, so that the problem of weak memory order of the instructions in the code to be repaired is repaired.

The memory barrier instruction is used for indicating that the target instruction is executed after the read-write instruction before the memory barrier instruction is executed.

As an example, if the target instruction is instruction 1, the read-write instruction preceding the target instruction is instruction 2. Then the repair device inserts a memory barrier instruction between instruction 1 and instruction 2. The memory barrier instruction is used to indicate that instruction 1 is executed after instruction 2.

The embodiment of the application provides a method for repairing a weak memory order problem, which classifies instructions to be repaired in a multithreading program source code compiling process to determine a target instruction set. Then, a target instruction needing to be inserted into the memory barrier instruction is further determined in the target instruction set through an optimization strategy, so that the target instruction can be executed according to the sequence required by the program. By the method, the repair device can automatically repair the weak memory order problem of the multi-thread program.

Alternatively, referring to fig. 4b, in another method for repairing the weak memory order problem provided in the embodiment of the present application, the above-mentioned steps S102 to S103 may be replaced by the following step S202.

S202, the repairing device classifies the instructions in the read-write instruction set based on the optimization strategy so as to determine the target instructions.

The read/write instruction set is the read/write instruction set determined by the repair apparatus in S101.

The optimization strategy is used for indicating the read-write instruction type needing to repair the weak memory order problem. The description of the optimization strategy can refer to the description of the optimization strategy, which is not repeated herein.

Specifically, the repair device may divide the read-write instruction into the read-write instruction that needs to be inserted with the memory barrier instruction and the read-write instruction that does not need to be inserted with the memory barrier instruction according to the optimization policy in the read-write instruction set determined in step S101 based on the optimization policy. Then, the repair device determines the read-write instruction needing to be inserted into the memory barrier instruction as a target instruction.

Therefore, in the process of compiling the source code of the multi-thread program, the method for repairing the weak memory order problem provided by the embodiment of the application can directly classify the instructions to be repaired through the optimization strategy, so that the target instructions needing to be inserted into the memory barrier instructions are determined, and thus the target instructions can be guaranteed to be executed according to the sequence required by the program. By the method, the repair device can automatically repair the weak memory order problem of the multi-thread program.

In order to more easily understand the method provided by the embodiment of the present application, the method for repairing the weak memory problem provided by the embodiment of the present application is applied to a GNU Compiler Collection (GCC), and the weak memory problem of the multi-thread program is repaired as an example.

Among them, GCC supports compilation of program source codes developed in advanced computer languages such as C, C + + or Fortran. The working process of GCC compiler source code comprises the following steps: pre-processing, compiling, assembling and linking. The method for repairing the weak memory problem provided by the embodiment of the application can be applied to a compiling stage.

After the GCC compiles the preprocessed multithreaded program source code in the compiling stage, an intermediate language (e.g., Register Transformation Language (RTL) expression) of the compiler can be obtained. The GCC can then output the optimized intermediate language as assembly code through the final module.

In general, the final module exports the intermediate language as assembly code in units of functions. Specifically, the final module outputs the intermediate language as assembly code through the final _ start _ function, final and final _ end _ function interfaces.

The final _ start _ function interface is used for initializing the state of the function. For example, analyzing the number of instructions in the function in the intermediate language, and determining the number of insn statements, etc., are not described in detail.

A final interface for outputting the intermediate language as assembly code. The method for repairing the weak memory order problem provided by the embodiment of the present application (for example, the method for repairing the weak memory order problem shown in fig. 3 or fig. 4 b) can be performed at this stage. Specifically, the repair device may execute the method described in S101-S104 above through the final interface, and insert the memory barrier instruction before the target instruction. The final interface then calls the output _ asm _ insn function, outputting the insn statement as assembly code.

In the multiple assembly instructions included in an insn statement, each assembly instruction is generally 4 in length. Since the number of insn statements and the number of instructions are determined when initializing the function state. Therefore, the final interface has typically determined the length of an insn statement.

However, when the repair device repairs the read/write command through the final interface, a memory barrier command is inserted before the target command. Thus, a repair instruction changes the length of the insn statement. In this case, before the final interface is output as assembly code, the final _ start _ function interface needs to perform corresponding processing on the original process (e.g. get _ attr _ length) for obtaining the length of the insn statement, so as to obtain the length of the insn statement after the memory barrier instruction is inserted. For example, without limitation, the number of instructions in an insn statement may be reduced by function calls, the length of the insn statement may be controlled, and so on.

Finally, final _ end _ function is used to clean up the resources used to export the intermediate language as assembly code.

The GCC then proceeds to assemble and link the repaired assembly code, thereby outputting the executable program code. Here, the embodiment of the present application does not describe in detail the specific working process of the GCC. It should be understood that the executable program code that the GCC finally outputs is the program code that repairs the weak memory order.

In summary, the embodiment of the present application provides a method for repairing a weak memory order problem, in a process of compiling a multi-thread program source code, a target instruction set is determined by classifying instructions to be repaired. Then, a target instruction needing to be inserted with the memory barrier instruction is further determined in the target instruction set through an optimization strategy, so that the target instruction can be executed according to the sequence required by the program, and the problem of automatically repairing the weak memory sequence of the multi-thread program is solved. The method provided by the embodiment of the application is used for repairing the problem of the weak memory order of the multithread program, and the efficiency of repairing the problem of the weak memory order of the program is greatly improved.

In addition, in the embodiment of the application, the weak memory order problem in the code to be repaired is identified and repaired by taking the function as a unit, so that the method provided by the embodiment of the application can be applied to repairing the weak memory order problem of a large-scale multi-thread program, and further the practicability of the method provided by the embodiment of the application is improved.

The scheme provided by the embodiment of the application is mainly introduced from the perspective of a method. To implement the above functions, it includes hardware structures and/or software modules for performing the respective functions. Those of skill in the art would readily appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as hardware or combinations of hardware and computer software. Whether a function is performed as hardware or computer software drives hardware depends upon the particular application and design constraints imposed on the solution. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present application.

In the embodiment of the present application, functional modules of the repair apparatus may be divided according to the above method example, for example, each functional module may be divided corresponding to each function, or two or more functions may be integrated into one processing module. The integrated module can be realized in a hardware mode, and can also be realized in a software functional module mode. It should be noted that, in the embodiment of the present application, the division of the module is schematic, and is only one logic function division, and there may be another division manner in actual implementation.

As shown in fig. 5, fig. 5 is a schematic structural diagram illustrating a prosthetic device 50 according to an embodiment of the present disclosure. The repair device 50 may be used in a method for repairing weak memory ordering problems as described above, such as for example in the method shown in fig. 3. The repair device 50 may include, among other things, a determination unit 51 and an insertion unit 52.

A determining unit 51, configured to determine a read-write instruction set in the code to be repaired; and the system is used for classifying the instructions in the read-write instruction set so as to determine the target instructions. The read-write instruction set comprises read instructions and/or write instructions in the codes to be repaired, and the instructions in the read-write instruction set are used for accessing the memory. And an inserting unit 52, configured to insert a memory barrier instruction between a read/write instruction before the target instruction and the target instruction.

As an example, in connection with fig. 3, the determining unit 51 may be configured to perform S101-S103, and the inserting unit 52 may be configured to perform S104.

Optionally, the determining unit 51 is specifically configured to determine a first type of instruction in the read-write instruction set; and the system is used for determining a target instruction according to the first type of instruction. The target instruction is an instruction in the read-write instruction set except the first type of instruction.

As an example, in connection with fig. 3, the determination unit 51 may be adapted to perform S102-S103.

Optionally, the determining unit 51 is specifically configured to determine a target instruction set based on the first type of instruction; and the target instruction set is used for determining a target instruction based on an optimization strategy, wherein the target instruction set comprises all instructions except the first type of instructions in the read-write instruction set. The optimization strategy is used for indicating the type of the read-write instruction which needs to repair the weak memory order problem.

As an example, in connection with fig. 3, the determining unit 51 may be configured to perform S103.

Optionally, the determining unit 51 is specifically configured to: and classifying the instructions in the read-write instruction set based on an optimization strategy to determine a target instruction. The optimization strategy is used for indicating the type of the read-write instruction which needs to repair the weak memory order problem.

Optionally, the optimization strategy includes at least one of the following strategies: the method comprises the steps that a first strategy is used for determining read-write instructions belonging to a white list in a target instruction set as target instructions; or, determining the read-write instruction except the read-write instruction in the blacklist in the target instruction set as the target instruction. And determining the read-write instruction with the context dependency relationship in the target instruction set as the target instruction only as the dependent read-write instruction by the second strategy. And determining the read-write instructions except the read-write instructions related to the special register in the target instruction set as the target instructions according to a third strategy. And determining the read-write instructions in the target instruction set except the read-write instructions related to the input and output parameters as the target instructions according to the fourth strategy.

Optionally, the prosthetic device 50 further comprises: an obtaining unit 53, configured to obtain a fifth policy configured by the user. An adding unit 54, configured to add the fifth policy to the optimization policy.

Optionally, the prosthetic device 50 further comprises: a receiving unit 55, configured to receive indication information before the determining unit 51 determines the target instruction, where the indication information is used to instruct a user to select the above-mentioned optimization strategy from the optimization strategies to be selected.

Optionally, the first type of instruction includes at least one of an instruction for reading and writing an unshared variable between threads, or a read and write instruction with order-preserving semantics.

Optionally, the prosthetic device 50 further comprises: and the identifying unit 56 is used for identifying the instruction in the objective function so as to determine the read-write instruction set. Wherein, the target function is any one of the above codes to be repaired.

As an example, in connection with fig. 3, the identifying unit 56 may be configured to perform S101.

Optionally, the code to be repaired is an intermediate language obtained by compiling a source code of a multi-thread program by a compiler, or the code to be repaired is an assembly code obtained by compiling a source code of a multi-thread program by a compiler.

For the detailed description of the above alternative modes, reference may be made to the foregoing method embodiments, which are not described herein again. In addition, for any explanation and beneficial effects of the repair apparatus 50 provided above, reference may be made to the corresponding method embodiments, and details are not repeated.

As an example, in connection with fig. 2, the determining unit 51, the inserting unit 52, the adding unit 54, and the identifying unit 56 in the repair apparatus 50 may be implemented by the processor 21 in fig. 2 executing the program code in the memory 22 in fig. 2. The acquisition unit 53 and the reception unit 55 may be implemented by the input-output interface 24 or the communication interface 25 in fig. 2.

The embodiment of the present application further provides a chip system 60, as shown in fig. 6, where the chip system 60 includes at least one processor and at least one interface circuit. By way of example, when the system-on-chip 60 includes one processor and one interface circuit, then the one processor may be the processor 61 shown in solid line block in fig. 6 (or the processor 61 shown in dashed line block), and the one interface circuit may be the interface circuit 62 shown in solid line block in fig. 6 (or the interface circuit 62 shown in dashed line block). When the chip system 60 includes two processors and two interface circuits, then the two processors include a processor 61 shown in a solid line block and a processor 61 shown in a dashed line block in fig. 6, and the two interface circuits include an interface circuit 62 shown in a solid line block and an interface circuit 62 shown in a dashed line block in fig. 6. This is not limitative.

The processor 61 and the interface circuit 62 may be interconnected by wires. For example, the interface circuit 62 may be used to receive signals (e.g., obtain optimization strategies, etc.). As another example, the interface circuit 62 may be used to send signals to other devices, such as the processor 61. Illustratively, the interface circuit 62 may read instructions stored in the memory and send the instructions to the processor 61. The instructions, when executed by the processor 61, may cause the repair device to perform the various steps in the embodiments described above. Of course, the chip system 60 may also include other discrete devices, which is not specifically limited in this embodiment.

Another embodiment of the present application further provides a computer-readable storage medium, which stores instructions that, when executed on a repair apparatus, cause the repair apparatus to perform the steps performed by the repair apparatus in the method flow shown in the foregoing method embodiment.

In some embodiments, the disclosed methods may be implemented as computer program instructions encoded on a computer-readable storage medium in a machine-readable format or encoded on other non-transitory media or articles of manufacture.

Fig. 7 schematically illustrates a conceptual partial view of a computer program product comprising a computer program for executing a computer process on a computing device provided by an embodiment of the application.

In one embodiment, the computer program product is provided using a signal bearing medium 70. The signal bearing medium 70 may include one or more program instructions that, when executed by one or more processors, may provide the functions or portions of the functions described above with respect to fig. 3. Thus, for example, one or more features described with reference to S101-S104 in FIG. 3 may be undertaken by one or more instructions associated with the signal bearing medium 70. Further, the program instructions in FIG. 7 also describe example instructions.

In some examples, signal bearing medium 70 may comprise a computer readable medium 71 such as, but not limited to, a hard disk drive, a Compact Disc (CD), a Digital Video Disc (DVD), a digital tape, a memory, a read-only memory (ROM), a Random Access Memory (RAM), or the like.

In some embodiments, signal bearing medium 70 may comprise a computer recordable medium 72 such as, but not limited to, memory, read/write (R/W) CDs, R/W DVDs, and the like.

In some embodiments, signal bearing medium 70 may comprise a communication medium 73, such as, but not limited to, a digital and/or analog communication medium (e.g., a fiber optic cable, a waveguide, a wired communications link, a wireless communication link, etc.).

The signal bearing medium 70 may be communicated by a wireless form of communication medium 73, such as a wireless communication medium conforming to the IEEE 1902.11 standard or other transmission protocol. The one or more program instructions may be, for example, computer-executable instructions or logic-implementing instructions.

In some examples, a remediation device, such as described with respect to fig. 3, may be configured to provide various operations, functions, or actions in response to one or more program instructions via computer-readable medium 71, computer-recordable medium 72, and/or communication medium 73.

It should be understood that the arrangements described herein are for illustrative purposes only. Thus, those skilled in the art will appreciate that other arrangements and other elements (e.g., machines, interfaces, functions, orders, and groupings of functions, etc.) can be used instead, and that some elements may be omitted altogether depending upon the desired results. In addition, many of the described elements are functional entities that may be implemented as discrete or distributed components or in conjunction with other components, in any suitable combination and location.

In the above embodiments, the implementation may be wholly or partially realized by software, hardware, firmware, or any combination thereof. When implemented using a software program, may be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. The processes or functions according to the embodiments of the present application are generated in whole or in part when the instructions are executed on and by a computer. The computer may be a general purpose computer, a special purpose computer, a network of computers, or other programmable device. The computer instructions may be stored on a computer readable storage medium or transmitted from one computer readable storage medium to another computer readable storage medium, for example, the computer instructions may be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wire (e.g., coaxial cable, fiber optic, Digital Subscriber Line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.). Computer-readable storage media can be any available media that can be accessed by a computer or can comprise one or more data storage devices, such as servers, data centers, and the like, that can be integrated with the media. The usable medium may be a magnetic medium (e.g., floppy disk, hard disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium (e.g., Solid State Disk (SSD)), among others.

The above description is only for the specific embodiments of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present invention, and all the changes or substitutions should be covered within the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the appended claims.

Claims

1. A method of repairing weak memory order problems, the method comprising:

determining a read-write instruction set in a code to be repaired, wherein the read-write instruction set comprises a read instruction or a write instruction in the code to be repaired, and the instruction in the read-write instruction set is used for accessing a memory;

classifying the instructions in the read-write instruction set to determine a target instruction;

and inserting a memory barrier instruction between a read-write instruction before the target instruction and the target instruction.

2. The method of claim 1, wherein the classifying the instructions in the read-write instruction set to determine the target instruction specifically comprises:

determining a first class of instructions in the read-write instruction set, wherein the instructions in the first class of instructions are weak internal memory order safety instructions;

determining the target instruction according to the first type of instruction; the target instruction is an instruction in the read-write instruction set other than the first type of instruction.

3. The method according to claim 2, wherein the determining the target instruction according to the first class of instruction specifically comprises:

determining a target instruction set based on the first class of instructions; the target instruction set comprises all instructions except the first type of instructions in the read-write instruction set;

determining the target instruction in the target instruction set based on an optimization policy; the optimization strategy is used for indicating the type of the read-write instruction needing to repair the weak memory order problem.

4. The method of claim 1, wherein the classifying the instructions in the read-write instruction set to determine the target instruction specifically comprises:

classifying the instructions in the read-write instruction set based on an optimization strategy to determine the target instruction; the optimization strategy is used for indicating the type of the read-write instruction needing to repair the weak memory order problem.

5. The method according to claim 3 or 4, wherein the optimization strategy comprises at least one of the following strategies:

determining a read-write instruction belonging to a white list in the target instruction set as the target instruction by a first strategy; or, determining the read-write instruction except the read-write instruction in the blacklist in the target instruction set as the target instruction;

the second strategy is to determine the read-write instruction with the context dependency relationship in the target instruction set as the dependent read-write instruction;

determining read-write instructions in the target instruction set except the read-write instructions related to the special register as the target instructions according to a third strategy;

and determining the read-write instructions in the target instruction set except the read-write instructions related to the input and output parameters as the target instructions according to a fourth strategy.

6. The method of claim 5, further comprising:

acquiring a fifth strategy configured by the user;

adding the fifth policy to the optimization policy.

7. The method of any of claims 3-6, wherein prior to said determining the target instruction, the method further comprises:

and receiving indication information, wherein the indication information is used for indicating a user to select the optimization strategies from the optimization strategies to be selected.

8. The method of any of claims 2, 3, 5-7, wherein the first class of instructions comprises at least one of instructions to read and write non-shared variables between threads, or read and write instructions with order preserving semantics.

9. The method according to any one of claims 1 to 8, wherein the determining a read-write instruction set specifically includes:

identifying an instruction in a target function to determine the read-write instruction set; wherein the target function is any one of the codes to be repaired.

10. The method according to any one of claims 1 to 9,

the code to be repaired is an intermediate language obtained by compiling a source code of a multi-thread program by a compiler; alternatively, the first and second electrodes may be,

the code to be repaired is an assembly code obtained by compiling a source code of the multi-thread program by a compiler.

11. An apparatus for repairing weak memory order problems, the apparatus comprising:

the device comprises a determining unit, a judging unit and a processing unit, wherein the determining unit is used for determining a read-write instruction set in a code to be repaired, the read-write instruction set comprises a read instruction and/or a write instruction in the code to be repaired, and the instruction in the read-write instruction set is used for accessing a memory; the system comprises a reading instruction set, a reading instruction set and a reading instruction set, wherein the reading instruction set is used for reading and writing instructions;

and the inserting unit is used for inserting a memory barrier instruction between a previous read-write instruction of the target instruction and the target instruction.

12. The apparatus of claim 11,

the determining unit is specifically configured to determine a first type of instruction in the read-write instruction set, where an instruction in the first type of instruction is a weak internal memory order security instruction; and determining the target instruction according to the first type of instruction; the target instruction is an instruction in the read-write instruction set other than the first type of instruction.

13. The apparatus of claim 12,

the determining unit is specifically configured to determine a target instruction set based on the first class of instruction; the target instruction set comprises all instructions except the first type of instructions in the read-write instruction set; and, determining the target instruction in the set of target instructions based on an optimization policy; the optimization strategy is used for indicating the type of the read-write instruction needing to repair the weak memory order problem.

14. The apparatus according to claim 11, wherein the determining unit is specifically configured to:

15. The apparatus of claim 13 or 14, wherein the optimization strategy comprises at least one of the following strategies:

16. The apparatus of claim 15, further comprising:

the acquisition unit is used for acquiring a fifth strategy configured by the user;

an adding unit, configured to add the fifth policy to the optimization policy.

17. The apparatus according to any one of claims 13-16, further comprising:

and the receiving unit is used for receiving indication information before the determining unit determines the target instruction, wherein the indication information is used for indicating a user to select the optimization strategy from optimization strategies to be selected.

18. The apparatus of any one of claims 12, 13, 15-17, wherein the first type of instruction comprises at least one of an instruction to read and write non-shared variables between threads, or a read and write instruction with order preserving semantics.

19. The apparatus according to any one of claims 11-18, further comprising:

the identification unit is used for identifying the instruction in the target function so as to determine the read-write instruction set; wherein the target function is any one of the codes to be repaired.

20. The apparatus of any one of claims 11-19,

the code to be repaired is assembly code obtained by compiling a source code of the multi-thread program by a compiler.

21. An apparatus for repairing weak memory order problems, the apparatus comprising: a memory for storing computer instructions and one or more processors for invoking the computer instructions to perform the method of any of claims 1-10.

22. A computer-readable storage medium, having stored thereon a computer program which, when run on a computer, causes the computer to perform the method of any one of claims 1-10.