CN115037402A - Clock signal synchronization method and device - Google Patents
Clock signal synchronization method and device Download PDFInfo
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- CN115037402A CN115037402A CN202210458344.1A CN202210458344A CN115037402A CN 115037402 A CN115037402 A CN 115037402A CN 202210458344 A CN202210458344 A CN 202210458344A CN 115037402 A CN115037402 A CN 115037402A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
- H04J3/0635—Clock or time synchronisation in a network
- H04J3/0638—Clock or time synchronisation among nodes; Internode synchronisation
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
- H04J3/0635—Clock or time synchronisation in a network
- H04J3/0638—Clock or time synchronisation among nodes; Internode synchronisation
- H04J3/0641—Change of the master or reference, e.g. take-over or failure of the master
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- Synchronisation In Digital Transmission Systems (AREA)
Abstract
The application provides a clock signal synchronization method and equipment. In the method, frame type network equipment is connected with an upstream network equipment, calibrates a local clock signal based on a recovered upstream clock signal and outputs a multi-channel selector of a main control board and a standby control board; the multi-channel selectors of the main master control board and the standby master control board respectively output calibrated multi-channel drivers; the multi-channel drivers of the main and standby main control boards respectively output a first group and a second group of multi-channel clock signals to the phase-locked loop chips of the frame type service boards; the clock signal selector of each service board gates a first group of multi-path clock signals input to the phase-locked loop chip of each board; and the phase-locked loop chips of the service boards of the butted upstream equipment lock the recovered upstream clock signals, and the phase-locked loop chips of other service boards lock the first group of multipath clock signals and calibrate the local clock signals.
Description
Technical Field
The present disclosure relates to communications technologies, and in particular, to a clock signal synchronization method and apparatus.
Background
Synchronous Ethernet (Sync E) is a technology for recovering a clock by using an Ethernet link code stream, and recovers the clock of a transmitting end from a serial data code stream through an Ethernet physical layer chip (PHY), thereby realizing network clock Synchronization.
In the frame network device of the ethernet, the service board connected with the upstream device recovers the clock frequency of the clock synchronization board of the upstream device from the butted ethernet port, and the clock frequency needs to be synchronized to other service boards of the frame network device, so that the service board butted with the downstream device sends an ethernet message of the clock frequency after synchronization is to be met, clock synchronization information is continuously transmitted, and clock synchronization in the whole networking is ensured.
In order to avoid that each service board of the frame device interfaces with a large number of ethernet ports of the upstream device occupied by the upstream device with a clock frequency synchronized with the upstream device, the conventional frame network device adopts a manner shown in fig. 1, where an upstream clock signal clock 1 recovered by an ethernet Physical Layer (PHY) chip of the service board interfacing with the upstream device is input to an active main control board and a standby main control board, Phase Locked Loop (PLL) chips 30 and 40 of the active main control board and the standby main control board respectively output calibrated clocks a1-an and a1 '-an' to PLL chips 1-n of all service boards, and the PLL chips 1-n of each service board calibrate a system clock of its own board and output the system clock to PHY chips 1-n of its own board and a service module (not shown in the figure) of its own board; the PHY of the service board n interfacing with the downstream device encodes the calibrated clock information in an ethernet message, and transmits the ethernet message to the downstream device for clock synchronization. However, the frequency input range of the clock signal supported by the PLL chip of the main control board of the frame network device is limited, and thus the type selection of the PHY chip on the service board is limited.
Disclosure of Invention
The purpose of the present application is to provide a clock signal synchronization method and device, where a frame-type network device provides full frame synchronization by interfacing with a service board of an upstream device, and simplifies the type selection of a PHY chip by the service board.
In order to achieve the above object, the present application provides a clock signal synchronization method, in which a first service board interfacing an upstream network device recovers an upstream clock signal of the upstream network device, calibrates a local clock signal of the first service board based on the upstream clock signal, and outputs the calibrated local clock signal of the first service board to a first multi-channel selector of a main master control board and a second multi-channel selector of a standby master control board; the first multichannel selector of the main master control board outputs the calibrated local clock signal of the first service board to a first multichannel driver of the main master control board; the second multi-channel selector of the standby main control board outputs the calibrated local clock signal of the first service board to a second multi-channel driver of the standby main control board; the first multichannel driver and the second multichannel driver respectively output a first group of multichannel clock signals and a second group of multichannel clock signals to each service board phase-locked loop chip; the clock signal selectors of the first service board, the second service board butted with the downstream network equipment and other service boards gate a first group of multi-path clock signals input to the phase-locked loop chip of each service board; the phase-locked loop chip of the first service board locks the recovered upstream clock signal, and the phase-locked loop chips of the second service board and other service boards lock the first group of multipath clock signals and calibrate the local clock signals.
In order to achieve the above object, the present application further provides a clock signal synchronization device, which is applied as an ethernet inner frame network device, and includes a main control board, a standby control board, a first service board for interfacing with an upstream network device, a second service board for interfacing with a downstream network device, and one or more other service boards; the output end of the Ethernet physical layer chip of the first service board is connected to the phase-locked loop chip of the board, and the output end of the phase-locked loop chip of the first service board is connected to the first multi-channel selector of the main control board and the second multi-channel selector of the standby main control board; the output ends of the first multi-channel selector and the multi-channel selector are respectively connected with the multi-channel drivers of the main control board and the standby main control board; the output end of the multi-channel driver of the main control board is respectively connected to the first input end of the clock signal selector of each service board; the output end of the multi-channel driver of the standby main control board is respectively connected to the second input end of the clock signal selector of each service board; the method comprises the steps that an upstream clock signal of upstream network equipment recovered by an Ethernet physical layer chip of a first service board is input to a phase-locked loop chip of the first service board, the phase-locked loop chip of the first service board calibrates a local clock signal of the first service board based on the upstream clock signal, and outputs the calibrated local clock signal of the first service board to a first multi-channel selector and a second multi-channel selector; the first multi-channel selector outputs the calibrated local clock signal of the first service board to the first multi-channel driver; the second multi-channel selector outputs the calibrated local clock signal of the first service board to the second multi-channel driver; the first multichannel driver and the second multichannel driver respectively output a first group of multichannel clock signals and a second group of multichannel clock signals to each service board phase-locked loop chip; the clock signal selectors of the first service board, the second service board butted with the downstream network equipment and other service boards gate a first group of multipath clock signals input to the phase-locked loop chip of each service board; the phase-locked loop chip of the first service board locks the recovered upstream clock signal, and the phase-locked loop chips of the second service board and other service boards lock the first group of multipath clock signals and calibrate the local clock signals.
The method and the device have the advantages that the limitation of the frequency of the clock signal output by the PHY chip of the service board due to the PLL chip of the main control board on the PHY chip of the service board can be reduced, and the type selection of the PHY chip of the service board on the frame type network equipment is simplified.
Drawings
Fig. 1 is a schematic diagram of a conventional synchronous clock of a frame type network device in a synchronous ethernet network;
FIG. 2 is a schematic diagram of a method for synchronizing clocks of a frame network device in a synchronous Ethernet network according to the present application;
fig. 3 is a schematic diagram of a synchronous clock of a frame network device in a synchronous ethernet network according to the present application.
Detailed Description
A detailed description will be given of a number of examples shown in a number of figures. In the following detailed description, numerous specific details are set forth in order to provide a thorough understanding of the present application. Well-known methods, procedures, components and circuits have not been described in detail so as not to obscure the examples.
The term "including" as that term is used is meant to include, but is not limited to; the term "comprising" means including but not limited to; the terms "above," "within," and "below" include the instant numbers; the terms "greater than" and "less than" mean that the number is not included. The term "based on" means based on at least a portion thereof.
FIG. 2 is a schematic diagram of a method for synchronizing clocks of a frame network device in a synchronous Ethernet network according to the present application; the method comprises the following steps:
in step 206, the pll chips of the first service board lock the recovered upstream clock signals, and the pll chips of the second service board and the other service boards lock the first set of multiple clock signals and calibrate the local clock signals.
The method and the device have the advantages that the limitation of the frequency of the clock signal output by the PHY chip of the service board due to the PLL chip of the main control board on the PHY chip of the service board can be reduced, and the type selection of the PHY chip of the service board on the frame type network equipment is simplified.
FIG. 3 is a schematic diagram of a synchronous clock of a frame network device in a synchronous Ethernet network according to the present application; the network devices 1, 2, 3 are 3 network nodes of a synchronous ethernet network. The network device 1 is used as a clock source device to transmit clock information downwards, the frame-type network device 2 is an intermediate node in a synchronous ethernet, receives the clock information of the upstream network device 1, synchronizes system clocks of a PHY1 chip-PHYn chip and related service function blocks on each service board of the device, and transmits the clock information to the downstream network device 3. The frame type network device 2 is provided with n service boards, a main control board and a standby main control board. The network device 3 receives only clock information.
In the frame network device 2, the output terminal of the PHY1 chip of the service board 1 is connected to the PLL1 chip of the board, and the output terminal of the PLL1 chip is connected to the multichannel selector 1 of the active main control board and the multichannel selector 2 of the standby main control board. The outputs of the multi-channel selector 1 and the multi-channel selector 2 are connected to the multi-channel drivers 1 and 2, respectively.
The output end of the multi-channel driver 1 is respectively connected to the first input end of the clock signal selector of each service board 1-service board n; the output terminals of the multi-channel driver 2 are connected to the second input terminals of the clock signal selectors of the respective service boards, respectively.
The PHY10 chip of the network device 1 encodes the high-precision clock information of the device into an ethernet packet, and sends the ethernet packet containing the clock information to the network device 2 through the ethernet.
The ethernet port of the service board 1 in the frame network device 2 is connected to the network device 1 in the synchronous ethernet, and receives an ethernet packet P1 containing clock information.
The PHY1 chip of the service board 1 recovers the clock signal clock 1 with high-precision clock synchronization on the network device 1 according to the received ethernet packet P1, and inputs the clock signal clock 1 to the PLL1 chip of the service board 1. The PLL1 chip also receives a local clock signal from a local crystal oscillator chip (not shown) on the service board 1. Since the PLL1 of the main control board has been configured such that the priority of the pin receiving the clock signal clock 1 from the PHY1 is higher than that of the pin receiving the local clock signal, the frequency of the local clock signal is calibrated according to the frequency of the clock signal clock 1, and the high-precision clock signal u1 is output to the multi-channel selector 1 of the main control board and the multi-channel selector 2 of the standby control board.
The multichannel selectors 1 and 2 are independent N-to-1 logic devices controlled by the controllers 1 and 2, respectively, and the controllers 1 and 2 gate the multichannel selectors 1 and 2 to be connected to pins of the PLL1 chip, respectively.
Since only the service board 1 and the network device 1 have an ethernet port for interfacing, only the clock signal clock u1 output by the PLL1 chip on the service board 1 is synchronous with the high-precision clock of the network device 1, and the clock signal clocks u2, … un output by the PLL2-PLLn chips on the remaining service boards 2-n are local clock signals output based on the frequency of the local crystal oscillator chips of the respective boards, and are not synchronous with the network device 1, but the pins of the multi-channel selectors 1, 2 connected to the service boards 2-n are not gated, so that the signals are not synchronous in the frame network device through the main control board and the standby control board.
The multi-channel selector 1 on the main control board outputs a clock signal clock U1 to the multi-channel driver 1 on the main control board based on the input clock signal clock U1, and the multi-channel driver 1 outputs n-channel clocks a1 and a2 … an to the PLL1-PLLn chip on each service board. The multi-channel selector 2 on the standby main control board outputs a clock signal clock U1 to the multi-channel driver 2 on the main control board based on the input clock signal clock U1, and the multi-channel driver 2 outputs n-channel clocks a1 ' and a2 ' … an ' to the PLLs 1-PLLn chips on the respective service boards.
The signal selector 1 and the signal selector n on the service board 1 and the service board n respectively gate the channel driver 1 of the master control board to output n-way clocks a1 and a2 … an.
The PLL1 on the service board 1 locks the clock signal clock 1 output by the PHY1 chip, and does not lock the input clock a1, and the PLL2-PLLn chip on the service board 2-service board n receives and locks the high-precision clocks a2 and … an distributed by the main master control board and outputs the reference clock to the PHY2-PHYn chip on the service board for normal operation.
In this application, the clock signal u1 output by the PHY1 chip of the service board 1 of the network device 1 connected to the upstream is synchronized with the clock 1, and the clock 1 is synchronized with the high-precision clock on the network device 1, so that the reference clock of each service board PHY is synchronized with the high-precision clock of the network device 1, and clock synchronization of the network device 1 and the network device 2 is achieved.
The service board n of the network device 2 is connected to the ethernet port of the network device 3, and the PHYn chip on the service board n encodes the clock information synchronized with the clock of the network device 1 in the device into the ethernet packet P2, and sends the ethernet packet P2 containing the clock information to the network device 3. The network device 3 is not a frame network device, and the PHY chip 20 of the network device 3 decodes the received ethernet packet to obtain clock information without performing intra-frame clock signal synchronization shown in fig. 3, thereby implementing clock synchronization of the network device 1, the network device 2, and the network device 3.
In this application, when the primary master control board fails, the standby master control board is switched to a new primary master control board and notified to each service board 1-service board n through a control channel (not shown), and the signal selector 1-signal selector n selects the channel driver 2 of the new master control board to output n-way clocks a1 ' and a2 ' … an ', respectively.
In this application, the multi-channel selectors 1 and 2 may also be other independent programmable logic devices, such as CPLDs and FPGAs, and the controller gates the pins of these programmable logic devices connected to the clock signal clock u1 by controlling the control pins of these programmable logic devices.
The clock signal calibrated by the PLL chip of the service board synchronously utilized by the clock signal of each service board of the intra-frame network device shown in fig. 3 may reduce the frequency limitation of the clock signal output by the PHY chip of the service board due to the PLL chip of the main control board in the PHY chip of the service board, and simplify the type selection of the PHY chip of the service board on the frame network device.
In the existing clock synchronization scheme shown in fig. 1, the clock synchronization of the standby main control board depends on the calibrated clock signal of the main control board, and in the present application, the main control board and the standby main control board are synchronized in the frame network device based on the calibrated clock signal of the service board of the upstream network device, so that the dependence of the standby main control board on the calibrated signal of the main control board in the scheme shown in fig. 1 is avoided.
The above description is only exemplary of the present application and should not be taken as limiting the present application, as any modification, equivalent replacement, or improvement made within the spirit and principle of the present application should be included in the scope of protection of the present application.
Claims (8)
1. A clock signal synchronization method applied to a frame network device, characterized in that,
a first service board of an upstream network device is butted to recover an upstream clock signal of the upstream network device, a local clock signal of the first service board is calibrated based on the upstream clock signal, and the calibrated local clock signal of the first service board is output to a first multi-channel selector of an active main control board and a second multi-channel selector of a standby main control board;
the first multichannel selector of the main master control board outputs the calibrated local clock signal of the first service board to a first multichannel driver of the main master control board;
the second multi-channel selector of the standby master board outputs the calibrated local clock signal of the first service board to a second multi-channel driver of the standby master board;
the first multichannel driver and the second multichannel driver respectively output a first group of multichannel clock signals and a second group of multichannel clock signals to each service board phase-locked loop chip;
the clock signal selectors of the first service board, the second service board butted with the downstream network equipment and other service boards gate the first group of multipath clock signals input to the phase-locked loop chips of the service boards;
and the phase-locked loop chips of the first service board lock the recovered upstream clock signals, and the phase-locked loop chips of the second service board and other service boards lock the first group of multipath clock signals and calibrate local clock signals.
2. The method of claim 1, wherein recovering the upstream clock signal of the upstream network device by a first service board interfacing with an upstream network device means that an ethernet physical layer chip of the first service board recovers an encoded upstream clock signal from a first ethernet packet received from an ethernet port interfacing with the upstream device;
the first service board calibrating the local clock signal of the first service board based on the upstream clock signal comprises:
the Ethernet physical layer chip of the first service board outputs a recovered upstream clock signal to a phase-locked loop chip of the first service board;
the phase-locked loop chip of the first service board determines that the priority of the upstream clock signal is higher than that of a local clock signal of a crystal oscillator chip of the first service board; and calibrating the frequency of the local clock signal of the first service board according to the frequency of the upstream clock signal.
3. The method of claim 1, further comprising:
the phase-locked loop chips of the second service board and other service boards input the calibrated local clock signal as a reference clock signal to the Ethernet physical layer chips of the respective service boards;
the Ethernet physical layer chip of the second service board encodes the reference clock signal of the second service board to a second Ethernet message;
and the second service board sends the second Ethernet through an Ethernet port which is butted with the downstream equipment.
4. The method of claim 2, further comprising:
the standby main control board is switched to a new main control board to inform the first service board, the second service board and the other service boards;
and the clock signal selectors of the first service board, the second service board and the other service boards gate the second group of multi-path clock signals input to the phase-locked loop chip of each service board.
5. A clock signal synchronization device is applied to frame type network equipment in an Ethernet and is characterized in that the device comprises a main control board, a standby control board, a first service board for butting upstream network equipment, a second service board for butting downstream network equipment and more than one other service boards;
the output end of the Ethernet physical layer chip of the first service board is connected to the phase-locked loop chip of the first service board, and the output end of the phase-locked loop chip of the first service board is connected to the first multichannel selector of the main control board and the second multichannel selector of the standby main control board;
the output ends of the first multi-channel selector and the multi-channel selector are respectively connected with the multi-channel drivers of the main control board and the standby main control board;
the output end of the multi-channel driver of the main master control board is respectively connected to the first input end of the clock signal selector of each service board; the output end of the multi-channel driver of the standby main control board is respectively connected to the second input end of the clock signal selector of each service board;
an upstream clock signal of the upstream network device recovered by an ethernet physical layer chip of the first service board is input to a phase-locked loop chip of the first service board, and the phase-locked loop chip of the first service board calibrates a local clock signal of the first service board based on the upstream clock signal and outputs the calibrated local clock signal of the first service board to the first multichannel selector and the second multichannel selector;
the first multi-channel selector outputs the calibrated local clock signal of the first traffic board to the first multi-channel driver; the second multi-channel selector outputs the calibrated local clock signal of the first traffic board to the second multi-channel driver;
the first multichannel driver and the second multichannel driver respectively output a first group of multichannel clock signals and a second group of multichannel clock signals to each service board phase-locked loop chip;
the clock signal selectors of the first service board, the second service board butted with the downstream network equipment and other service boards gate the first group of multipath clock signals input to the phase-locked loop chips of the service boards;
and the phase-locked loop chips of the first service board lock the recovered upstream clock signals, and the phase-locked loop chips of the second service board and other service boards lock the first group of multipath clock signals and calibrate local clock signals.
6. The device according to claim 5, wherein the first service board recovering the upstream clock signal of the upstream network device means that the ethernet physical layer chip of the first service board recovers an encoded upstream clock signal from a first ethernet packet received from the ethernet port of the upstream device;
the first service board calibrating the local clock signal of the first service board based on the upstream clock signal comprises:
the Ethernet physical layer chip of the first service board outputs a recovered upstream clock signal to a phase-locked loop chip of the first service board;
the phase-locked loop chip of the first service board determines that the priority of the upstream clock signal is higher than the local clock signal of the crystal oscillator chip of the first service board; and calibrating the frequency of the local clock signal of the first service board according to the frequency of the upstream clock signal.
7. The apparatus of claim 5,
the phase-locked loop chips of the second service board and other service boards input the calibrated local clock signal as a reference clock signal to the Ethernet physical layer chips of the respective service boards;
the Ethernet physical layer chip of the second service board encodes the reference clock signal of the second service board to a second Ethernet message;
and the second service board sends the second Ethernet through an Ethernet port which is butted with the downstream equipment.
8. The apparatus of claim 6,
the standby main control board is switched to a new main control board to inform the first service board, the second service board and the other service boards;
and the clock signal selectors of the first service board, the second service board and the other service boards gate the second group of multi-path clock signals input to the phase-locked loop chip of each service board.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210458344.1A CN115037402A (en) | 2022-04-28 | 2022-04-28 | Clock signal synchronization method and device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210458344.1A CN115037402A (en) | 2022-04-28 | 2022-04-28 | Clock signal synchronization method and device |
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| Publication Number | Publication Date |
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| CN115037402A true CN115037402A (en) | 2022-09-09 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN202210458344.1A Pending CN115037402A (en) | 2022-04-28 | 2022-04-28 | Clock signal synchronization method and device |
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| CN (1) | CN115037402A (en) |
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- 2022-04-28 CN CN202210458344.1A patent/CN115037402A/en active Pending
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