CN115033263A - Electronic equipment and firmware updating method of clock chip - Google Patents
Electronic equipment and firmware updating method of clock chip Download PDFInfo
- Publication number
- CN115033263A CN115033263A CN202210765021.7A CN202210765021A CN115033263A CN 115033263 A CN115033263 A CN 115033263A CN 202210765021 A CN202210765021 A CN 202210765021A CN 115033263 A CN115033263 A CN 115033263A
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- clock chip
- programmable logic
- configuration information
- logic device
- storage module
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F8/00—Arrangements for software engineering
- G06F8/60—Software deployment
- G06F8/65—Updates
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/24—Resetting means
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/44—Arrangements for executing specific programs
- G06F9/445—Program loading or initiating
- G06F9/44505—Configuring for program initiating, e.g. using registry, configuration files
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Abstract
The application discloses firmware updating method of electronic equipment and clock chip, wherein electronic equipment includes treater, programmable logic device and clock chip, the treater with programmable logic device connects, programmable logic device with clock chip connects, programmable logic device is equipped with storage module, storage module storage has clock chip's configuration information, after the system was powered on, programmable logic device load in the storage module configuration information will the configuration information writes in clock chip, clock chip loads configuration information and based on configuration information generation output information. The firmware of the clock chip is convenient to update, material normalization is facilitated, and material management and control difficulty and production cost are reduced.
Description
Technical Field
The present disclosure relates to electronic devices, and particularly to a firmware updating method for an electronic device and a clock chip.
Background
When the hardware is designed, different platforms can be customized to design different clock topologies, and a chip manufacturer burns matched firmware according to design requirements and updates manufacturer material codes. In the existing method, a manufacturer updates firmware to a nonvolatile memory in a chip, the nonvolatile memory is not invalid when power is down, but the number of times of updating is extremely limited, burning is complex, burning is carried out when the nonvolatile memory is actually used, different firmware is required to be burned and new material codes are required to be added when the firmware is updated. For the chip user, even if the internal hardware design of the chip can support the change, a new material code is needed because the firmware is updated. And then be unfavorable for realizing the material normalization, increase the material management and control degree of difficulty and the difficult change of firmware, cause the waste of huge manpower, material resources, financial resources.
Disclosure of Invention
The application aims to provide the electronic equipment and the firmware updating method of the clock chip, so that the firmware of the clock chip can be updated conveniently, material normalization is facilitated, and material management and control difficulty and production cost are reduced.
In order to achieve the above object, the present application provides an electronic device, including a processor, a programmable logic device and a clock chip, where the processor is connected to the programmable logic device, the programmable logic device is connected to the clock chip, the programmable logic device is provided with a storage module, the storage module stores configuration information of the clock chip, after a system is powered on, the programmable logic device loads the configuration information in the storage module and writes the configuration information into the clock chip, and the clock chip loads the configuration information and generates output information based on the configuration information.
Optionally, the electronic device includes a central processing unit and a substrate management controller, the central processing unit is connected to the clock chip, and the processor is the substrate management controller or the central processing unit.
Optionally, the clock chip is provided with a register, and the configuration information is written into the register.
Optionally, a non-volatile memory is further disposed in the clock chip.
Optionally, an I2C interface or an SPI interface is provided between the processor and the programmable logic device and between the programmable logic device and the clock chip.
Optionally, the programmable logic device sends a reset signal to the clock chip to enable the clock chip to load the configuration information.
In order to achieve the above object, the present application further provides a firmware update method for a clock chip, where the method performs firmware update based on an electronic device, where the electronic device includes a programmable logic device, and a processor and a clock chip that are respectively connected to the programmable logic device, and the method includes:
storing the configuration information of the clock chip in a storage module of the programmable logic device;
when the system is powered on, the configuration information in the storage module is loaded through the programmable logic device and is written into the clock chip;
the clock chip loads the configuration information and generates output information based on the configuration information.
Optionally, before the clock chip loads the configuration information, the method further includes: the programmable logic device sends a reset signal to the clock chip;
and the clock chip loads the configuration information according to the reset signal.
Optionally, the clock chip is provided with a register, and the configuration information is written into the register.
Optionally, an I2C interface or an SPI interface is provided between the processor and the programmable logic device and between the programmable logic device and the clock chip.
The configuration information of the clock chip is stored in the storage module of the programmable logic device, after the system is powered on, the programmable logic device loads the configuration information in the storage module and writes the configuration information into the clock chip, and the clock chip loads the configuration information and generates output information based on the configuration information. And then when different systems need to realize different functions of the clock chip and need to update the firmware of the clock chip, only the configuration information in the storage module needs to be changed, so that the firmware of the clock chip is convenient to update, the firmware does not need to be returned to a factory for burning, the material normalization is facilitated, and the material management and control difficulty and the production cost are reduced.
Drawings
Fig. 1 shows a schematic block diagram of an electronic device according to an embodiment of the present application.
Fig. 2 shows a schematic block diagram of an electronic device according to another embodiment of the present application.
Fig. 3 is a flowchart illustrating a firmware updating method for a clock chip according to an embodiment of the present disclosure.
Detailed Description
In order to explain technical contents, structural features, and objects and effects of the present application in detail, the following detailed description is given with reference to the embodiments and the accompanying drawings.
Referring to fig. 1, the present application discloses an electronic device, which includes a processor 1, a programmable logic device 2, and a clock chip 3, where the processor 1 is connected to the programmable logic device 2, the programmable logic device 2 is connected to the clock chip 3, the programmable logic device 2 is provided with a storage module, the storage module stores configuration information of the clock chip 3, after a system is powered on, the programmable logic device 2 loads the configuration information in the storage module and writes the configuration information into the clock chip 3, and the clock chip 3 loads the configuration information and generates output information based on the configuration information.
Specifically, after the configuration of the clock chip 3 is updated, the clock chip 3 enters software reset to load the changed configuration, and then performs initialization again and finally enters Locked Mode stable output. The process of resetting the clock chip 3 to complete stable output is known to those skilled in the art and will not be described herein.
Specifically, the programmable logic device 2 is controlled to send a reset signal to the clock chip 3 to enable the clock chip 3 to load the configuration information.
This application utilizes the configuration information in the storage module to carry out initial configuration to clock chip 3 after the power-on, and then when different systems need realize clock chip 3's different functions and will update clock chip 3's firmware, only need change the configuration information in the storage module can, be convenient for update clock chip 3's firmware, need not to return the factory and burn, be favorable to the material normalization, reduce the material management and control degree of difficulty and manufacturing cost.
Specifically, an I2C interface or SPI interface is provided between the processor 1 and the programmable logic device 2 and between the programmable logic device 2 and the clock chip 3.
Referring to fig. 2, in some embodiments, the electronic device includes a central processing unit 4(CPU) and a baseboard management controller 5(BMC), the CPU 4 is connected to the clock chip 3, and the processor 1 is the baseboard management controller 5 or the CPU 4.
In the example shown in fig. 2, the processor 1 is a baseboard management controller 5, and after the system is powered on, the baseboard management controller 5 loads the configuration information in the storage module through the programmable logic device 2 and the related interface, and updates the configuration information to the clock chip 3 after the interface of the clock chip 3 is ready. Specifically, an I2C interface or SPI interface is provided between the baseboard management controller 5 and the programmable logic device 2 and between the programmable logic device 2 and the clock chip 3.
Specifically, in this example, the OUT0 pin of the clock chip 3 outputs a signal to the TIME pin of the central processor 4, and the OUT2 pin of the clock chip 3 outputs a signal to the CLK pin of the other module 8. The crystal oscillator 6 and the crystal 7 respectively output signals to the CLKIN _ OSC pin and the CLKIN _ XTAL pin of the cpu 4, and the CLKOUT pin of the cpu 4 outputs signals to the IN pin of the clock chip 3. The working principle of the clock chip 3 is known to those skilled in the art and will not be described herein.
It is understood that, in some other embodiments, the electronic device may not include the bmc 5, the cpu 4 is connected to the programmable logic device 2, and after the system is powered on, the cpu 4 loads the configuration information in the storage module through the programmable logic device 2 and the related interface, and updates the configuration information to the clock chip 3 after the interface of the clock chip 3 is ready.
In some embodiments, the electronic device is a server, but is not limited to this, for example, the electronic device may also be a switch or the like.
In some embodiments, the storage module is Flash memory (Flash). Because the flash memory has a fast reading speed and a large number of erasable times (100 to 1000 ten thousand times), the configuration information can be written into the clock chip 3 conveniently and rapidly, and the configuration information can be updated repeatedly. It is understood that the memory module is not limited to a flash memory, but may be other memory modules capable of reading multiple times.
In some embodiments, programmable logic device 2 is a CPLD, but is not so limited.
Specifically, the clock chip 3 is provided with a register to which configuration information is written.
Specifically, a nonvolatile memory (NVM) is also provided in the clock chip 3.
Referring to fig. 3, an embodiment of the present application discloses a firmware updating method for a clock chip, where the method performs firmware updating based on an electronic device, where the electronic device includes a programmable logic device 2, and a processor 1 and a clock chip 3 that are respectively connected to the programmable logic device 2, and the method includes:
101. storing the configuration information of the clock chip 3 in a storage module of the programmable logic device 2;
102. when the system is powered on, the configuration information in the storage module is loaded through the programmable logic device 2 and is written into the clock chip 3;
103. the clock chip 3 loads the configuration information and generates output information based on the configuration information.
This application utilizes the configuration information of storage in storage module to carry out initial configuration to clock chip 3 after the power-on, and then when different systems need realize clock chip 3's different functions and will update clock chip 3's firmware, only need change the configuration information in the storage module can, be convenient for update clock chip 3's firmware, need not to return the factory and burn, be favorable to the material normalization, reduce the material management and control degree of difficulty and manufacturing cost.
Specifically, before the clock chip 3 loads the configuration information, the method further includes: the programmable logic device 2 sends a reset signal to the clock chip 3;
the clock chip 3 loads configuration information according to the reset signal.
Specifically, the clock chip 3 is provided with a register to which configuration information is written.
Specifically, an I2C interface or an SPI interface is provided between the processor 1 and the programmable logic device 2 and between the programmable logic device 2 and the clock chip 3.
The above disclosure is only for the purpose of illustrating the preferred embodiments of the present application and is not to be construed as limiting the scope of the present application, therefore, the present application is not limited thereto, and all equivalent variations made in the scope of the present application are included in the scope of the present application.
Claims (10)
1. An electronic device is characterized by comprising a processor, a programmable logic device and a clock chip, wherein the processor is connected with the programmable logic device, the programmable logic device is connected with the clock chip, the programmable logic device is provided with a storage module, the storage module stores configuration information of the clock chip, after a system is powered on, the programmable logic device loads the configuration information in the storage module and writes the configuration information into the clock chip, and the clock chip loads the configuration information and generates output information based on the configuration information.
2. The electronic device of claim 1, wherein the electronic device comprises a central processing unit and a baseboard management controller, the central processing unit is connected to the clock chip, and the processor is the baseboard management controller or the central processing unit.
3. The electronic device of claim 1, wherein the clock chip is provided with a register, the configuration information being written to the register.
4. The electronic device of claim 1, wherein a non-volatile memory is disposed within the clock chip.
5. The electronic device of claim 1, wherein an I2C interface or an SPI interface is provided between the processor and the programmable logic device and between the programmable logic device and the clock chip.
6. The electronic device of claim 1, wherein the programmable logic device sends a reset signal to the clock chip to cause the clock chip to load the configuration information.
7. A firmware updating method of a clock chip is characterized in that the method is based on electronic equipment for updating firmware, the electronic equipment comprises a programmable logic device, a processor and a clock chip, and the processor and the clock chip are respectively connected with the programmable logic device, and the method comprises the following steps:
storing the configuration information of the clock chip in a storage module of the programmable logic device;
when the system is powered on, the configuration information in the storage module is loaded through the programmable logic device and is written into the clock chip;
the clock chip loads the configuration information and generates output information based on the configuration information.
8. The firmware update method of a clock chip according to claim 7,
before the clock chip loads the configuration information, the method further includes: the programmable logic device sends a reset signal to the clock chip;
and the clock chip loads the configuration information according to the reset signal.
9. The firmware updating method of the clock chip according to claim 7, wherein the clock chip is provided with a register, and the configuration information is written to the register.
10. The firmware update method of the clock chip according to claim 7, wherein an I2C interface or an SPI interface is provided between the processor and the programmable logic device and between the programmable logic device and the clock chip.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210765021.7A CN115033263A (en) | 2022-06-30 | 2022-06-30 | Electronic equipment and firmware updating method of clock chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210765021.7A CN115033263A (en) | 2022-06-30 | 2022-06-30 | Electronic equipment and firmware updating method of clock chip |
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| Publication Number | Publication Date |
|---|---|
| CN115033263A true CN115033263A (en) | 2022-09-09 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202210765021.7A Pending CN115033263A (en) | 2022-06-30 | 2022-06-30 | Electronic equipment and firmware updating method of clock chip |
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| Country | Link |
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| CN (1) | CN115033263A (en) |
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2022
- 2022-06-30 CN CN202210765021.7A patent/CN115033263A/en active Pending
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