CN115020377A

CN115020377A - Semiconductor structure and preparation method thereof

Info

Publication number: CN115020377A
Application number: CN202210608807.8A
Authority: CN
Inventors: 于业笑
Original assignee: Changxin Memory Technologies Inc
Current assignee: Changxin Memory Technologies Inc
Priority date: 2022-05-31
Filing date: 2022-05-31
Publication date: 2022-09-06

Abstract

The embodiment of the disclosure discloses a semiconductor structure and a preparation method thereof, wherein the semiconductor structure comprises: a substrate; a bit line comprising a first portion within the substrate, the bit line extending in a first direction; the node contact plug is positioned in the substrate and positioned between two adjacent bit lines; a first spacer layer located in the substrate between the first portion of the bit line and the node contact plug and covering sidewalls of the first portion of the bit line.

Description

Semiconductor structure and preparation method thereof

Technical Field

The present disclosure relates to the field of semiconductor manufacturing, and more particularly, to a semiconductor structure and a method for fabricating the same.

Background

The development of dynamic memories pursues high speed, high integration density, low power consumption, and the like. However, as the structure size of the semiconductor device is reduced, especially in the manufacturing process of DRAM with critical dimension smaller than 15nm, the distance between the Bit Line (BL) and the contact plug (NC) is too close, which easily causes current Leakage (Leakage), resulting in increased parasitic capacitance between the bit line and the contact plug, and affecting the device performance.

Disclosure of Invention

Embodiments of the present disclosure provide a semiconductor structure and a method for fabricating the same.

According to a first aspect of embodiments of the present disclosure, there is provided a semiconductor structure comprising:

a substrate;

a bit line comprising a first portion within the substrate, the bit line extending in a first direction;

the node contact plug is positioned in the substrate and positioned between two adjacent bit lines;

a first spacer layer located in the substrate between the first portion of the bit line and the node contact plug and covering sidewalls of the first portion of the bit line.

In some embodiments, the first spacer layer comprises a first sub-spacer layer, a second sub-spacer layer, and a third sub-spacer layer, the second sub-spacer layer being located between the first sub-spacer layer and the third sub-spacer layer;

the material of the first sub-spacer layer and the third sub-spacer layer includes nitride, and the material of the second sub-spacer layer includes oxide.

In some embodiments, the bit line further comprises a second portion located on the substrate;

the semiconductor structure further includes: and a second spacer covering sidewalls of the second portion of the bit line.

In some embodiments, the second spacer layer includes a fourth sub-spacer layer, a fifth sub-spacer layer, and a sixth sub-spacer layer disposed in sequence;

the material of the fourth sub-spacer layer and the sixth sub-spacer layer includes nitride, and the material of the fifth sub-spacer layer includes oxide.

In some embodiments, further comprising:

an isolation layer on the node contact plug.

In some embodiments, further comprising:

a word line located within the substrate, the word line extending along a second direction, wherein the first direction and the second direction are perpendicular to each other;

the word line further includes a barrier fence in a direction perpendicular to the substrate, the second portion of the bit line being located on the barrier fence.

In some embodiments, further comprising:

the first doping area and the second doping area are positioned in the substrate, and the first doping area and the second doping area are respectively positioned on two sides of the word line;

the bit line is connected with the first doped region, and the node contact plug is connected with the second doped region.

According to a second aspect of the embodiments of the present disclosure, there is provided a method for manufacturing a semiconductor structure, including:

providing a substrate;

forming a first spacer layer within the substrate;

forming a bit line comprising a first portion within the substrate, the bit line extending in a first direction;

forming a node contact plug in the substrate, wherein the node contact plug is positioned between two adjacent bit lines;

wherein the first spacer is positioned between the first portion of the bit line and the node contact plug and covers sidewalls of the first portion of the bit line.

In some embodiments, the forming the first spacer layer comprises:

forming a first contact hole in the substrate;

forming a first sub spacing layer, a second sub spacing layer and a third sub spacing layer in the first contact hole in sequence;

In some embodiments, the forming the first sub spacer layer, the second sub spacer layer, and the third sub spacer layer includes:

depositing a first sub-spacer layer in the first contact hole;

etching and removing part of the first sub spacer layer pre-layer to form a first sub spacer layer on the side wall of the first contact hole;

forming a second sub spacing layer pre-layer in the first sub spacing layer;

etching and removing part of the second sub-spacer layer pre-layer to form a second sub-spacer layer on the side wall of the first sub-spacer layer;

forming a third sub spacing layer pre-layer in the second sub spacing layer;

and etching and removing part of the third sub-spacer layer pre-layer to form a third sub-spacer layer on the side wall of the second sub-spacer layer.

In some embodiments, the forming a bit line comprises:

forming a conducting layer in the first contact hole after the third sub-spacing layer is formed and on the surface of the substrate;

sequentially forming a first mask layer, a first insulating layer and a first photoresist layer on the conducting layer;

patterning the first photoresist layer to form a patterned first photoresist layer;

etching the first insulating layer and the first mask layer according to the patterned first photoresist layer to form a patterned first insulating layer and a patterned first mask layer; the patterned first insulating layer and the patterned first mask layer extend along a first direction and expose part of the conductive layer;

forming a first dielectric layer pre-layer on the side walls and the top surfaces of the patterned first insulating layer and the patterned first mask layer and on the top surface of the exposed partial conducting layer;

etching to remove part of the first dielectric layer pre-layer, and reserving the first dielectric layer pre-layer on the side walls of the patterned first insulating layer and the patterned first mask layer to form a first dielectric layer extending along a first direction;

and removing the patterned first insulating layer and the patterned first mask layer, and etching the conductive layer on the surface of the substrate by taking the first dielectric layer as a mask so as to form a bit line extending along the first direction.

after forming the bit line, the method further comprises:

forming a second spacer layer; the second spacer covers a second portion of the sidewall of the bit line.

In some embodiments, the forming the second spacer layer comprises:

forming a fourth sub-spacing layer, a fifth sub-spacing layer and a sixth sub-spacing layer on the side wall of the second part of the bit line in sequence;

In some embodiments, further comprising:

after forming a node contact plug, an isolation layer is formed on the node contact plug.

In some embodiments, further comprising:

forming word lines extending in a second direction in the substrate before forming the first spacers, wherein the first direction and the second direction are perpendicular to each other;

the word line further includes a barrier fence in a direction perpendicular to the substrate, and the second portion of the bit line is formed on the barrier fence.

In some embodiments, further comprising:

after a word line is formed, forming a first doped region and a second doped region in the substrate, wherein the first doped region and the second doped region are respectively positioned on two sides of the word line;

In the embodiment of the disclosure, the first spacer layer is disposed between the bit line and the node contact plug, so that the thickness of the insulating material between the bit line and the node contact plug is increased, which is beneficial to reducing the leakage current between the bit line and the node contact plug, and further reducing the parasitic capacitance.

Drawings

In order to more clearly illustrate the embodiments of the present disclosure or technical solutions in the conventional art, the drawings required to be used in the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present disclosure, and other drawings can be obtained by those skilled in the art without inventive efforts.

Fig. 1 is a three-dimensional view of a semiconductor structure provided by an embodiment of the present disclosure;

fig. 2 is a top view of a semiconductor structure provided by an embodiment of the present disclosure;

FIG. 3 is a cross-sectional view taken along the line A-A' in FIGS. 1 and 2;

FIG. 4 is a cross-sectional view taken along the line B-B' in FIGS. 1 and 2;

fig. 5 is a schematic flow chart illustrating a method for fabricating a semiconductor structure according to an embodiment of the present disclosure;

fig. 6a to 6o are schematic structural diagrams of a semiconductor structure provided in an embodiment of the present disclosure during a manufacturing process;

fig. 7a to 7e are schematic structural diagrams of the first spacer layer in the preparation process in the embodiment of the present disclosure.

Description of reference numerals:

10-a substrate; 11-an active region; 12-an isolation structure; 13-a first doped region; 14-a second doped region; 15-a filling layer;

20-bit line; 21-a first part; 22-a second part; 201' -a first conductive layer; 202' -a second conductive layer; 200-a conductive layer; 201-an initial first conductive layer; 202-an initial second conductive layer;

30-node contact plugs; 301-node contact plug via;

41-a first spacer layer; 411-the first sub-spacer layer; 412-a second sub-spacer layer; 413-a third sub spacer layer; 42-a second spacer layer; 421-fourth sub spacer layer; 422-a fifth sub-spacer layer; 423-sixth sub-spacer layer; 401 — a first contact hole; 411' -a first sub-spacer layer pre-layer; 412' -a second sub-spacer layer pre-layer; 413' -a third sub-spacer layer pre-layer;

50-an isolation layer;

60-word lines; 61-segregator barrier; 601-patterning a word line mask layer; 602 a word line trench;

71-a first mask layer; 72-a first insulating layer; 73-a first photoresist layer; 74-first dielectric layer; 710-a patterned first mask layer; 720-a patterned first insulating layer; 730-a patterned first photoresist layer; 74' -first dielectric pre-layer

81-a first sub-mask layer; 82-a first sub-insulating layer; 83-second sub-mask layer; 84-a second sub-insulating layer; 85-second photoresist layer.

Detailed Description

Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be embodied in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present disclosure. It will be apparent, however, to one skilled in the art, that the present disclosure may be practiced without one or more of these specific details. In other instances, well-known features of the art have not been described in order to avoid obscuring the present disclosure; that is, not all features of an actual embodiment are described herein, and well-known functions and constructions are not described in detail.

In the drawings, the size of layers, regions, elements, and relative sizes may be exaggerated for clarity. Like reference numerals refer to like elements throughout.

It will be understood that when an element or layer is referred to as being "on" … …, "adjacent to … …," "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to the other elements or layers or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on … …," "directly adjacent to … …," "directly connected to" or "directly coupled to" other elements or layers, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present disclosure. And the discussion of a second element, component, region, layer or section does not necessarily imply that the first element, component, region, layer or section is necessarily present in the disclosure.

Spatial relationship terms such as "under … …", "under … …", "below", "under … …", "above … …", "above", and the like, may be used herein for ease of description to describe the relationship of one element or feature to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, then elements or features described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary terms "below … …" and "below … …" can encompass both an orientation of up and down. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.

In order to thoroughly understand the present disclosure, detailed steps and detailed structures will be set forth in the following description so as to explain the technical aspects of the present disclosure. The following detailed description of the preferred embodiments of the present disclosure, however, the present disclosure may have other embodiments in addition to these detailed descriptions.

The disclosed embodiments provide a semiconductor structure. Fig. 1 is a three-dimensional view of a semiconductor structure provided in an embodiment of the present disclosure, fig. 2 is a top view of the semiconductor structure provided in an embodiment of the present disclosure, fig. 3 is a cross-sectional view taken along a-a 'direction in fig. 1 and 2, and fig. 4 is a cross-sectional view taken along a B-B' direction in fig. 1 and 2. It should be noted that only the active region, word line, and bit line structures are shown in fig. 2, and other device structures are not shown.

Referring to fig. 1 to 4, the semiconductor structure includes:

a substrate 10;

a bit line 20, the bit line 20 including a first portion 21 within the substrate 10, the bit line 20 extending in a first direction;

a node contact plug 30 located in the substrate 10 and located between two adjacent bit lines 20;

a first spacer 41 positioned in the substrate 10 between the first portion 21 of the bit line 20 and the node contact plug 30 and covering sidewalls of the first portion 21 of the bit line 20.

In the embodiment of the disclosure, the first spacer layer is arranged between the bit line and the node contact plug, so that the thickness of the insulating material between the bit line and the node contact plug is increased, which is beneficial to reducing the leakage current between the bit line and the node contact plug, and further reducing the parasitic capacitance.

The substrate 10 may be a Silicon substrate, a Germanium substrate, a Silicon carbide substrate, an SOI (Silicon On Insulator) substrate, a GOI (Germanium On Insulator) substrate, or the like, may be a substrate including other element semiconductors or compound semiconductors, such as a glass substrate or a III-V compound substrate (e.g., a gallium nitride substrate, a gallium arsenide substrate, or the like), may be a stacked structure, such as Si/SiGe, or the like, or may be another epitaxial structure, such as an SGOI (Silicon Germanium On Insulator) or the like.

In an embodiment, the substrate 10 comprises an active region 11 and an isolation structure 12, wherein the isolation structure 12 defines the substrate 10 as a plurality of discrete active regions 11. The material of the isolation structure 12 may include one or more of an oxide (e.g., silicon oxide), a nitride (e.g., silicon nitride), and an oxynitride (e.g., silicon oxynitride).

With continued reference to fig. 1-4, the semiconductor structure further includes: a first doped region 13 and a second doped region 14 located in the substrate 10, wherein the first doped region 13 and the second doped region 14 are respectively located at two sides of the word line 60; the bit line 20 is connected to the first doped region 13, and the node contact plug 30 is connected to the second doped region 14.

In one embodiment, the substrate 10 further comprises a fill layer 15. The filling layer 15 is located between two adjacent word lines 60. The material of the filling layer 15 includes, but is not limited to, oxide.

In one embodiment, as shown in fig. 3, the bit line 20 includes a first portion 21 located in the substrate 10, and specifically, the first portion 21 of the bit line is a portion below the upper surface of the filling layer 15.

The bit line 20 includes a first conductive layer 201 ' and a second conductive layer 202 ' on the first conductive layer 201 '. The material of the first conductive layer 201 'includes, but is not limited to, titanium nitride, and the material of the second conductive layer 202' includes, but is not limited to, metal tungsten.

In some embodiments, the bit line 20 further includes a third conductive layer (not shown) located below the first conductive layer. The material of the third conductive layer includes, but is not limited to, one or more of cobalt silicide, nickel silicide, and titanium silicide. Ohmic contacts may be formed between the third conductive layer and the substrate to reduce contact resistance between the first and second conductive layers and the substrate.

In one embodiment, referring to fig. 3, the first spacer layer 41 includes a first sub-spacer layer 411, a second sub-spacer layer 412 and a third sub-spacer layer 413, and the second sub-spacer layer 412 is located between the first sub-spacer layer 411 and the third sub-spacer layer 413; the material of the first sub-spacer 411 and the third sub-spacer 413 includes nitride, and the material of the second sub-spacer 412 includes oxide.

In some embodiments, since the silicon on the periphery of the bit line is not completely removed, that is, the bit line and the node contact plug are not completely separated by the insulating material, and the distance between the bit line and the node contact plug is too close, which is easy to cause current leakage, so that the parasitic capacitance between the bit line and the node contact plug is increased, and the device performance is affected, in the embodiments of the present disclosure, the first spacer layer is disposed between the bit line and the node contact plug, and the first spacer layer is a stacked layer structure of nitride-oxide-nitride, which increases the thickness of the insulating material, and is more favorable for reducing the leakage current between the bit line and the node contact plug, and reducing the parasitic capacitance.

In some embodiments, a parasitic Capacitance (CBL) of a bit line of the semiconductor device may be obtained by the following equation (1):

CBL＝CBL_BL+CBL_NC+CBL_BW (1)

CBL _ BL denotes a parasitic capacitance between the bit line BL and the bit line BL, CBL _ NC denotes a parasitic capacitance between the bit line BL and the node contact plug NC, CBL _ BW denotes a parasitic capacitance between the bit line BL and the word line WL, and CBL is a sum of these three parasitic capacitances.

In the current semiconductor structure, through a semiconductor process device simulation (TCAD), CBL _ BL + CBL _ NC + CBL _ BW is 7.0aF/cell +21.0aF/cell +13.3aF/cell is 41.3 aF/cell. In the embodiment of the present disclosure, CBL _ BL + CBL _ NC + CBL _ BW is 4.8aF/cell +12.2aF/cell +13.3aF/cell is 30.3 aF/cell. Through simulation results, it can be seen that the parasitic capacitance between the bit line BL and the node contact plug NC in the embodiment of the present disclosure is reduced from 21.0aF/cell to 12.2aF/cell, which shows that the parasitic capacitance between the bit line BL and the node contact plug NC can be significantly reduced by providing the first spacer layer, and the parasitic capacitance CBL of the bit line is also significantly reduced by approximately 26.6%.

In an embodiment, the bit line 20 further comprises a second portion 22 located on the substrate 10; the semiconductor structure further includes: and a second spacer 42 covering sidewalls of the second portion 22 of the bit line.

Specifically, as shown in fig. 3, the second portion 22 of the bit line is a portion above the surface of the fill layer 15.

In one embodiment, the semiconductor structure further comprises: a first dielectric layer 74 is located over the second portion 22 of the bit line. The material of the first dielectric layer 74 includes, but is not limited to, silicon nitride.

The second spacer 42 covers not only the sidewalls of the second portion 22 of the bit line, but also the sidewalls and surface of the first dielectric layer 74.

In one embodiment, the second spacer layer 42 includes a fourth sub-spacer layer 421, a fifth sub-spacer layer 422, and a sixth sub-spacer layer 423; the material of the fourth sub spacer layer 421 and the sixth sub spacer layer 423 includes nitride, and the material of the fifth sub spacer layer 422 includes oxide.

In the embodiment of the disclosure, the second spacer is disposed on the sidewall of the second portion of the bit line, so that leakage current between the bit line and the node contact plug can be reduced, and parasitic capacitance can be reduced.

In one embodiment, the semiconductor structure further comprises: a word line 60 located within the substrate 10, the word line 60 extending along a second direction, wherein the first direction and the second direction are perpendicular to each other; the word line 60 further comprises a barrier fence 61, in a direction perpendicular to the substrate 10, the second portion 22 of the bit line being located on the barrier fence 61.

Specifically, as shown in fig. 1 and 4, in the embodiment of the present disclosure, the second portion of the bit line is located above the barrier fence in the direction perpendicular to the substrate, so that the barrier fence 61 and the bit line 20 may enclose a self-aligned via hole for forming the node contact plug, reducing the use of a mask layer for forming the via hole for the node contact plug.

In one embodiment, the material of the word line 60 includes tungsten (W), copper (Cu), titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), metal silicide, metal alloy, or any combination thereof. The material of the barrier fence 61 includes, but is not limited to, silicon nitride.

With continued reference to fig. 4, since the second portions of the bit lines are formed on the barrier ribs such that the surfaces of the bit lines are higher than the surfaces of the word lines, the spacing between the word lines and the bit lines is increased, which is beneficial for reducing the parasitic capacitance between the word lines and the bit lines.

In one embodiment, as shown in fig. 3, the semiconductor structure further comprises: and an isolation layer 50 on the node contact plug 30. The material of the isolation layer 50 includes, but is not limited to, silicon nitride. The material of the node contact plug 30 includes, but is not limited to, polysilicon.

The isolation layer is formed on the node contact plug, so that the node contact plug can be protected, the node contact plug is prevented from being oxidized in other subsequent processes, and the isolation layer is etched when the structures such as a landing pad (landing pad) and the like are required to be formed subsequently, and the node contact plug is exposed.

The embodiment of the present disclosure further provides a method for manufacturing a semiconductor structure, specifically referring to fig. 5, as shown in the drawing, the method includes the following steps:

step 501: providing a substrate;

step 502: forming a first spacer layer within the substrate;

step 503: forming a bit line comprising a first portion within the substrate, the bit line extending in a first direction;

step 504: forming a node contact plug in the substrate, wherein the node contact plug is positioned between two adjacent bit lines; wherein the first spacer layer is between the first portion of the bit line and the node contact plug and covers sidewalls of the first portion of the bit line.

The following describes the method for fabricating a semiconductor structure according to the embodiments of the present disclosure in further detail with reference to specific embodiments.

Fig. 6a to 6o are schematic structural diagrams of a semiconductor structure provided in an embodiment of the disclosure during a manufacturing process. Fig. 7a to 7e are schematic structural diagrams of the first spacer layer in the preparation process in the embodiment of the disclosure. It should be noted that fig. 6a to 6o (2) and fig. 7a to 7e are sectional views in the direction of a-a' in fig. 1 and 2 during the manufacturing process.

First, referring to fig. 6a, a step 501 is performed, providing a substrate 10.

In an embodiment, the isolation structures 12 define the substrate 10 as a plurality of discrete active regions 11. The material of the isolation structure 12 may include one or more of an oxide (e.g., silicon oxide), a nitride (e.g., silicon nitride), and an oxynitride (e.g., silicon oxynitride).

Next, referring to fig. 6b and 6c, the method further includes: before forming the first spacer layer, a word line 60 extending in a second direction is formed in the substrate 10, wherein the first direction and the second direction are perpendicular to each other.

Specifically, referring first to fig. 6b, a word line mask layer (not shown) may be grown on the upper surface of the substrate 10, and then patterned to form a patterned word line mask layer 601, and to show the pattern of the word line trench 602 to be etched, and the word line mask layer may be patterned by a photolithography process. The word line mask layer can be a photoresist mask or a hard mask patterned based on a photolithographic mask; when the word line mask layer is a photoresist mask, the word line mask layer is specifically patterned by exposure, development, photoresist stripping and other steps. A wordline trench 602 is then etched to a depth in accordance with the wordline trench pattern to be etched.

Next, referring to fig. 6c, a word line 60 is formed within the word line trench 602. The material of the word line 60 includes tungsten (W), copper (Cu), titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), metal silicide, metal alloy, or any combination thereof.

With continued reference to FIG. 6c, the word line 60 also includes a segregator barrier 61. The material of the barrier fence 61 includes, but is not limited to, silicon nitride.

In the embodiment of the present disclosure, the barrier rib 61 and the bit line formed later may enclose a self-aligned via hole for forming the node contact plug, reducing the use of a mask layer for forming the via hole for the node contact plug.

And as shown in fig. 4, since the second portion of the bit line is formed on the isolation barrier, the surface of the subsequently formed bit line is higher than the surface of the word line, so that the distance between the word line and the bit line is increased, which is beneficial to reducing the parasitic capacitance between the word line and the bit line.

Next, with continued reference to fig. 6c, after forming the word line 60, forming a first doped region 13 and a second doped region 14 in the substrate 10, where the first doped region 13 and the second doped region 14 are respectively located at two sides of the word line 60; the subsequently formed bit line is connected to the first doped region 13, and the subsequently formed node contact plug is connected to the second doped region 14.

The first doped region 13 and the second doped region 14 may be formed in the active region 11 by means of ion implantation. In a specific embodiment, the first doped region 13 and the second doped region 14 have the same conductivity type, such as n-type.

Next, referring to fig. 6d to 6f, step 502 is performed to form a first spacer layer 41 in the substrate 10.

In one embodiment, the forming the first spacer layer 41 includes: forming a first contact hole 401 in the substrate 10; forming a first sub spacer layer 411, a second sub spacer layer 412 and a third sub spacer layer 413 in the first contact hole 401 in sequence; the material of the first sub-spacer 411 and the third sub-spacer 413 includes nitride, and the material of the second sub-spacer 412 includes oxide.

In the embodiment of the disclosure, the first spacer layer is arranged between the bit line and the node contact plug, and the first spacer layer is a nitride-oxide-nitride stacked structure, so that the thickness of the insulating material is increased, and the leakage current between the bit line and the node contact plug and the parasitic capacitance can be reduced.

Specifically, referring first to fig. 6d, a filling layer 15 is formed between two adjacent word lines 60 to fill the space between the protruded portions of the barrier fences 61 of the two adjacent word lines. The material of the filling layer 15 includes, but is not limited to, oxide.

Next, a first sub mask layer 81, a first sub insulating layer 82, a second sub mask layer 83, a second sub insulating layer 84, and a second photoresist layer 85 are sequentially formed on the barrier rib 61 and the filling layer 15. The second photoresist layer 85 is patterned to show a pattern of the first contact hole to be etched on the second photoresist layer 85.

The material of the first sub-mask Layer 81 includes, but is not limited to, Amorphous Carbon (ACL), the material of the first sub-insulating Layer 82 includes, but is not limited to, oxide, the material of the second sub-mask Layer 83 includes, but is not limited to, Spin On Hard mask (SOH) material, and the material of the second sub-insulating Layer 84 includes, but is not limited to, silicon oxynitride (SiON).

Next, referring to fig. 6e, the second sub-insulating layer 84, the second sub-mask layer 83, the first sub-insulating layer 82 and the first sub-mask layer 81 are sequentially transferred according to the pattern of the first contact hole to be etched until the first contact hole 401 having a certain depth is etched in the substrate.

Next, referring to fig. 6f, a first sub spacer layer 411, a second sub spacer layer 412, and a third sub spacer layer 413 are sequentially formed within the first contact hole 401.

Specifically, referring to fig. 6f and fig. 7a to 7e, the forming of the first sub-spacer layer 411, the second sub-spacer layer 412 and the third sub-spacer layer 413 includes:

depositing a first sub-spacer layer pre-layer 411' in said first contact hole 401, see fig. 7 a;

etching away part of the first sub spacer layer pre-layer 411' to form a first sub spacer layer 411 on the sidewall of the first contact hole 401, see fig. 7 b;

forming a second sub-spacer layer pre-layer 412' within the first sub-spacer layer 411, see fig. 7 c;

etching away part of the second sub-spacer layer pre-layer 412' to form a second sub-spacer layer 412 on the sidewall of the first sub-spacer layer 411, see fig. 7 d;

forming a third sub spacer layer pre-layer 413' within said second sub spacer layer 412, see fig. 7 e;

etching away part of the third sub-spacer layer pre-layer 413' to form a third sub-spacer layer 413 on the sidewalls of the second sub-spacer layer 412, see fig. 6 f.

Specifically, a first sub-spacer layer pre-layer 411 'is formed by deposition on the sidewall and bottom of the first contact hole 401 and the surface of the filling layer 15, and then the bottom of the first contact hole 401 is removed to form a first sub-spacer layer 411' on the surface of the filling layer 15, so as to form a first sub-spacer layer 411 on the sidewall of the first contact hole 401; then depositing a second sub-spacer layer pre-layer 412 'on the sidewalls of the first sub-spacer layer 411, the bottom surface of the first contact hole 401 and the surface of the filling layer 15, and then removing the second sub-spacer layer pre-layer 412' on the bottom surface of the first contact hole 401 and the surface of the filling layer 15 to form a second sub-spacer layer 412 on the sidewalls of the first sub-spacer layer 411; then, a third sub spacer layer pre-layer 413 'is deposited on the sidewalls of the second sub spacer layer 412, the bottom surface of the first contact hole 401, and the surface of the filling layer 15, and then the third sub spacer layer pre-layer 413' on the bottom surface of the first contact hole 401 and the surface of the filling layer 15 is removed to form a third sub spacer layer 413 on the sidewalls of the second sub spacer layer 412.

Next, referring to fig. 6g to 6l, step 503 is executed to form a bit line 20, where the bit line 20 includes a first portion 21 located in the substrate 10, and the bit line 20 extends along a first direction.

In one embodiment, the forming the bit line 20 includes:

forming a conductive layer 200 in the first contact hole 401 after the third sub spacer layer 413 is formed and on the surface of the substrate 10;

forming a first mask layer 71, a first insulating layer 72 and a first photoresist layer 73 on the conductive layer 200 in sequence;

patterning the first photoresist layer 73 to form a patterned first photoresist layer 730;

etching the first insulating layer 72 and the first mask layer 71 according to the patterned first photoresist layer 730 to form a patterned first insulating layer 720 and a patterned first mask layer 710; the patterned first insulating layer 720 and the patterned first mask layer 710 extend along a first direction and expose a portion of the conductive layer 200;

forming a first dielectric pre-layer 74' on the sidewalls and the top surfaces of the patterned first insulating layer 720 and the patterned first mask layer 710, and the top surface of the exposed portion of the conductive layer 200;

etching to remove a part of the first dielectric layer pre-layer 74 ', and remaining the first dielectric layer pre-layer 74' on the sidewalls of the patterned first insulating layer 720 and the patterned first mask layer 710 to form a first dielectric layer 74 extending along a first direction;

the patterned first insulating layer 720 and the patterned first mask layer 710 are removed, and the conductive layer 200 on the surface of the substrate 10 is etched using the first dielectric layer 74 as a mask, so as to form the bit lines 20 extending along the first direction.

Specifically, referring to fig. 6g, a conductive layer 200 is formed in the first contact hole 401 after the third sub-spacer layer 413 is formed and on the surface of the substrate 10. In particular, the conductive layer 200 is located on the surface of the infill layer 15 and the segregator barrier 61.

The conductive layer 200 includes an initial first conductive layer 201 and an initial second conductive layer 202 on the initial first conductive layer 201.

Then, referring to fig. 6h, a first mask layer 71, a first insulating layer 72, and a first photoresist layer 73 are sequentially formed on the conductive layer 200.

The material of the first mask layer 71 includes, but is not limited to, a spin-on hard mask material, and the material of the first insulating layer 72 includes, but is not limited to, silicon oxynitride (SiON).

Then, referring to fig. 6i, the first photoresist layer 73 is patterned to form a patterned first photoresist layer 730.

Then, referring to fig. 6j, the first insulating layer 72 and the first mask layer 71 are etched according to the patterned first photoresist layer 730 to form a patterned first insulating layer 720 and a patterned first mask layer 710; the patterned first insulating layer 720 and the patterned first mask layer 710 extend along a first direction and expose a portion of the conductive layer 200; a first dielectric pre-layer 74' is formed on the sidewalls and top surfaces of the patterned first insulating layer 720 and the patterned first mask layer 710, and the top surface of the exposed portion of the conductive layer 200.

The material of the first dielectric pre-layer 74' includes, but is not limited to, silicon nitride.

Then, referring to fig. 6k, a portion of the first dielectric layer pre-layer 74 'is removed by etching, the first dielectric layer pre-layer 74' located on the sidewalls of the patterned first insulating layer 720 and the patterned first mask layer 710 is remained to form the first dielectric layer 74 extending along the first direction, and the patterned first insulating layer 720 and the patterned first mask layer 710 are removed.

Then, referring to fig. 6l, the conductive layer 200 on the surface of the substrate 10 is etched using the first dielectric layer 74 as a mask to form the bit lines 20 extending along the first direction.

In practice, the bit lines may be formed using a self-aligned reverse patterning (SARP) process.

The bit line includes a first conductive layer 201 'etched from an initial first conductive layer 201, and a second conductive layer 202' etched from an initial second conductive layer 202. The material of the first conductive layer 201 'includes, but is not limited to, titanium nitride, and the material of the second conductive layer 202' includes, but is not limited to, metal tungsten.

As shown in (2) of fig. 6l, the bit line 20 includes a first portion 21 located within the substrate 10, specifically, the first portion 21 of the bit line is a portion below the surface of the filling layer 15.

In one embodiment, the bit line 20 further includes a second portion 22 located on the substrate 10. Specifically, the second portion 22 of the bit line is a portion above the surface of the fill layer 15.

Referring to fig. 6l, a second portion 22 of the bit line is formed on the barrier fence 61 in a direction perpendicular to the substrate 10.

Next, referring to fig. 6m, after forming the bit line 20, the method further comprises: forming a second spacer 42; the second spacers 42 cover the sidewalls of the second portion 22 of the bit line.

In one embodiment, the forming the second spacer layer 42 includes: forming a fourth sub spacer layer 421, a fifth sub spacer layer 422 and a sixth sub spacer layer 423 in sequence on sidewalls of the second portion 22 of the bit line; the material of the fourth sub spacer 421 and the sixth sub spacer 423 includes nitride, and the material of the fifth sub spacer 422 includes oxide.

In the embodiment of the present disclosure, the second spacer is disposed on the sidewall of the second portion of the bit line, so that leakage current between the bit line and the node contact plug can be reduced, and parasitic capacitance can be reduced.

Next, referring to fig. 6n and 6o, step 504 is performed to form a node contact plug 30 in the substrate 10, wherein the node contact plug 30 is located between two adjacent bit lines 20; wherein the first spacer 41 is located between the first portion 21 of the bit line and the node contact plug 30, and covers sidewalls of the first portion 21 of the bit line.

Specifically, referring first to fig. 6n, the second spacer layer 42 and the substrate 10 are etched to form a node contact plug via hole 301. As shown in (3) of fig. 6n, a self-aligned node contact plug via 301 is surrounded by the barrier fence 61 and the bit line located under the second spacer 42.

Then, referring to fig. 6o, the node contact plugs 30 are formed within the node contact plug via holes 301. The material of the node contact plug 30 includes, but is not limited to, polysilicon.

With continued reference to fig. 6o, the method further comprises: after the node contact plug 30 is formed, an isolation layer 50 is formed on the node contact plug 30. The material of the isolation layer 50 includes, but is not limited to, silicon nitride.

The above description is meant to be illustrative of the preferred embodiments of the present disclosure and not to limit the scope of the disclosure, which is intended to include all modifications, equivalents, and improvements that are within the spirit and scope of the disclosure.

Claims

1. A semiconductor structure, comprising:

a substrate;

2. The semiconductor structure of claim 1,

the first spacing layer comprises a first sub spacing layer, a second sub spacing layer and a third sub spacing layer, and the second sub spacing layer is positioned between the first sub spacing layer and the third sub spacing layer;

3. The semiconductor structure of claim 1,

the bit line further includes a second portion located on the substrate;

4. The semiconductor structure of claim 3,

the second spacing layer comprises a fourth sub spacing layer, a fifth sub spacing layer and a sixth sub spacing layer which are arranged in sequence;

5. The semiconductor structure of claim 1, further comprising:

an isolation layer on the node contact plug.

6. The semiconductor structure of claim 3, further comprising:

7. The semiconductor structure of claim 6, further comprising:

8. A method for fabricating a semiconductor structure, comprising:

providing a substrate;

forming a first spacer layer within the substrate;

9. The method of claim 8,

the forming a first spacer layer includes:

forming a first contact hole in the substrate;

10. The method of claim 9,

the forming of the first sub spacer layer, the second sub spacer layer and the third sub spacer layer includes:

depositing a first sub-spacer layer in the first contact hole;

forming a second sub spacing layer pre-layer in the first sub spacing layer;

forming a third sub spacing layer pre-layer in the second sub spacing layer;

and etching and removing part of the third sub-spacing layer pre-layer to form a third sub-spacing layer on the side wall of the second sub-spacing layer.

11. The method of claim 9,

the forming a bit line includes:

12. The method of claim 8,

the bit line further includes a second portion located on the substrate;

after forming the bit line, the method further comprises:

forming a second spacer layer; the second spacer covers a second portion of the sidewalls of the bit line.

13. The method of claim 12,

the forming the second spacer layer includes:

14. The method of claim 8, further comprising:

15. The method of claim 12, further comprising:

16. The method of claim 15, further comprising: