CN115016068B - Photon integrated chip of 1 XN optical switch based on M-level binary tree - Google Patents
Photon integrated chip of 1 XN optical switch based on M-level binary tree Download PDFInfo
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- 230000005697 Pockels effect Effects 0.000 description 1
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- 238000003491 array Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
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- GQYHUHYESMUTHG-UHFFFAOYSA-N lithium niobate Chemical compound [Li+].[O-][Nb](=O)=O GQYHUHYESMUTHG-UHFFFAOYSA-N 0.000 description 1
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- G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
- G02B6/24—Coupling light guides
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- G02B6/35—Optical coupling means having switching means
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- G02B6/10—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type
- G02B6/12—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
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- G—PHYSICS
- G02—OPTICS
- G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
- G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
- G02B6/10—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type
- G02B6/12—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
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- G02B2006/12085—Integrated
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- G—PHYSICS
- G02—OPTICS
- G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
- G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
- G02B6/10—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type
- G02B6/12—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
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Abstract
A photonic integrated chip based on 1 × N optical switches of M-level binary tree comprises 1 × 2 optical switches on N-1 integrated photonic chips, and N =2 M (ii) a Each 1 × 2 optical switch is composed of 1 input terminal, a first output terminal and a second output terminal; N-1X 2 optical switches are aligned at the center of a photonic chip along the y-axis direction and are arranged into a one-dimensional array, the distance between two adjacent 1X 2 optical switches is equal, the distance just passes through one optical waveguide, and waveguide routing is carried out between every two adjacent 1X 2 optical switches according to a certain rule. The invention can greatly reduce the area of a rectangular chip occupied by the total 1 XN optical switch on the premise of not changing a binary tree topological structure, not having waveguide intersection and not changing the sequence of output waveguides.
Description
Technical Field
The invention relates to a photonic integrated chip structure design, in particular to a photonic integrated chip of a1 XN optical switch based on an M-level binary tree.
Background
1 xn optical switches are widely available in integrated photonic chips, which contain one input and N outputs. In a planar integrated photonic chip, 1 XN optical switches (N) are implemented directly>2) It is relatively inconvenient to implement the method by cascading the 1 × 2 optical switches in a binary tree, where each branch node of the binary tree is a1 × 2 optical switch. The number of output ports N is an exponential power of 2 at this time, i.e., N =2 M M is a series of binary trees, and N and M are both positive integers. By controlling the output gating of each stage of 1 × 2 optical switch, the input optical signal can be guided to any output terminal for output. In order to realize an optical switch that can support a wide spectrum operation and is high-speed, it is necessary to use a mach-zehnder type optical switch based on an electro-optical effect, such as a carrier dispersion effect based mach-zehnder type optical switch in a silicon-based photonic waveguide or a Pockels effect based mach-zehnder type optical switch in a lithium niobate waveguide. Such 1 x 2 optical switches are characterized by very large aspect ratios, typically up to 1cm in length and typically only on the order of hundreds of microns in width, which can reach several tens or even more. If a topology design of sequential stepwise arrangement is adopted in the binary tree structure, that is, each stage of the binary tree occupies an area of one column in the longitudinal direction, the total 1 × N optical switch occupies a very large area of a rectangular chip. Therefore, a new structural design scheme is needed, which can greatly reduce the rectangular chip area occupied by the 1 × N optical switch, and still maintain the topology structure of the binary tree, avoid waveguide crossing, and not change the output waveguide orderAnd the path delay from the input end to each output end is the same.
Disclosure of Invention
Aiming at the defects of the existing scheme, the invention provides a photonic integrated chip structure design scheme of a binary tree switch formed by a1 x 2 optical switch with a large length-width ratio. The invention can greatly reduce the rectangular chip area occupied by the total 1 xN optical switch by staggering the 1 x 2 optical switches with large length-width ratio, can keep the topological structure of the binary tree, has no waveguide intersection, does not change the sequence of the output waveguides, and has the same path delay from the input end to each output end. Therefore, the area utilization rate of the rectangular chip can be improved, and the chip cost is reduced.
The technical solution of the invention is as follows:
a photon integrated chip of 1 XN optical switch based on M-level binary tree is characterized by comprising N-1 integrated photon chips with 1 X2 optical switches, and N =2 M (ii) a Each 1 × 2 optical switch is composed of 1 input terminal, a first output terminal and a second output terminal; m is the progression of a binary tree;
1, 1 st level of 1 × 2 optical switches are arranged, and the serial number is 1..1; the 2 nd stage has 2 1 × 2 optical switches with the numbers 2..1 and 2..2, wherein the first output end of the optical switch with the number 1..1 is connected with the input end of the optical switch with the number 2..1, and the second output end of the optical switch with the number 1..1 is connected with the input end of the optical switch with the number 2.. 2; by analogy, the j-th stage has 2 (j-1) Optical switches with numbers of j.1 to j.2 (j-1) Wherein the first and second output terminals of the optical switch with the number (j-1). K at the upper stage are respectively connected with the input terminals of the optical switches with the numbers j. (2 k-1) and j..2k, wherein j and k are positive integers, j is more than or equal to 2 and is less than or equal to M, and k is more than or equal to 1 and is less than or equal to 2 (j-2) ；
Setting the length direction of a 1X 2 optical switch as the x-axis direction and the width direction as the y-axis direction;
the N-1 multiplied by 2 optical switches are aligned at the center of the photonic chip along the y-axis direction and are arranged into a one-dimensional array according to the following rule A, the distance between two adjacent 1 multiplied by 2 optical switches is equal, the distance can just walk one optical waveguide, and the N-1 multiplied by 2 optical switches are wired according to the following rule B; the input waveguide and the output waveguide of the 1 × 2 optical switch are along the x-axis direction and are located at two sides of the 1 × 2 optical switch in the x-axis direction, and the propagation direction of the optical signal in the optical switch is along the + x-axis
Rule A:1 × 2 optical switch arrangement:
step A1: a 1..1 optical switch is first placed, e.g., the 1..1 optical switch center is placed at coordinates x =0, y =0.
Step A2: two optical switches of j. (2 k-1) and j..2k are respectively arranged on the + y-axis side and the-y-axis side of the (j-1). K optical switch and are aligned along the y-axis. It should be ensured that both the j. (2 k-1) and j..2k optical switches are closer to the (j-1). K optical switch than the other arranged optical switches. Wherein j is more than or equal to 2 and less than or equal to M, k is more than or equal to 1 and less than or equal to 2 (j-2) 。
Step A3: sequentially increasing k and repeating the step A2 until all the optical switches of the j-th stage are arranged.
Step A4: j is sequentially incremented and steps A2-A3 are repeated until all stages have completed the permutation.
Step A5: the positions of all the optical switches on the y axis are adjusted, the centers of all the optical switches are aligned, the distances between every two adjacent optical switches are equal, and the distance between every two adjacent optical switches can just run on one optical waveguide.
Thus, the arrangement of all the optical switches is completed, and the arranged optical switches are one-dimensional arrays aligned along the y-axis.
Rule B1 × 2 optical switch waveguide routing mode:
step B1: leading out the output ends of all the optical switches of the Mth stage by using waveguides with the same length as the N paths of output of the 1 xN optical switch, wherein N =2 M 。
And step B2: the input ends of two optical switches of j. (2 k-1) and j..2k are connected to the first and second output ends of the (j-1). K optical switch by waveguides, and the waveguides pass through the optical switch array from two sides of the optical switch respectively close to the (j-1). K optical switch in a zigzag mode and are prevented from crossing the existing waveguides. Wherein j is more than or equal to 2 and less than or equal to M, k is more than or equal to 1 and less than or equal to 2 (j-2) 。
And step B3: and increasing k in sequence, and repeating the step B2 until the input ends of all the optical switches of the j level complete waveguide routing and ensure that the waveguide routing are equal in length.
And step B4: and sequentially reducing j, and repeating the steps 2 and 3 until the input ends of all the optical switches except the 1.
And step B5: the input end of the 1..1 optical switch is led out by a waveguide to be used as the input of the 1 XN optical switch.
Thus, routing of all optical waveguides is completed.
A1 x 2 optical switch typically also contains 2 metal electrodes. The ground electrode can be shared, is led out from the right side (namely + x direction side) of the optical switch array, and is wired to the edge of the chip along the y-axis direction. The other control electrode may be routed from the left side of the optical switch array (i.e., the-x direction side), each routing an electrode along the y-axis to the chip edge. Or, instead of routing the electrodes to the edge of the chip, metal pads are directly fabricated near the two metal electrodes of each 1 × 2 optical switch, and the electrical chip controlling the optical switch is connected to the optical chip by flip-chip bonding.
The invention can also carry out the above arrangement on partial areas in the binary tree structure according to the actual chip size. For example: for an M-level binary tree, the 1 st to M-1 st level optical switches are arranged as described above, and the M-th level optical switches are arranged in a column along the y-axis on the right side (+ x direction).
The invention has the advantages that the area of a rectangular chip occupied by the total 1 XN optical switch can be greatly reduced on the premise of not changing a binary tree topological structure, not having waveguide intersection and not changing the sequence of output waveguides. Assuming that the length of the 1 × 2 optical switch is L and the width is W, the rectangular chip area occupied by the entire 1 × N optical switch is equal to lx (2) (since the waveguide width is on the order of micrometers and the bending radius is on the order of ten micrometers, which is much smaller than the size of the optical switch) while ignoring the chip area occupied by the waveguide traces (since the waveguide width is on the order of micrometers and the bending radius is much smaller than the size of the optical switch) M -1)W＝(2 M -1) LW. In contrast, if the binary tree is directly arranged in order along the x-axis direction, the occupied rectangular chip area is equal to ML (2) M-1 )W＝M(2 M-1 ) LW, is about M/2 times the area of the present invention. Obviously, the more the output ends of the optical switches are, the larger the number of stages M is, and the larger the area saved by the invention is.
Drawings
Fig. 1 is a schematic diagram of an embodiment of the present invention in which 1 × 2 optical switches are arranged in a stepwise manner.
Fig. 2 is a schematic diagram of an embodiment of the present invention for performing step-by-step waveguide routing on a completely arranged 1 × 2 optical switch array.
Fig. 3 is a schematic diagram of an optical switch arrangement employing the present invention for the first 3 levels of a 4-level binary tree.
Fig. 4 is a schematic diagram of an unoptimized binary tree of optical switch arrangements arranged sequentially along the x-axis direction.
Detailed Description
The invention will be further illustrated with reference to the following figures and examples, without thereby limiting the scope of the invention. Embodiments of the present invention include, but are not limited to, the following examples.
Referring to fig. 1, fig. 1 is a schematic diagram of an embodiment of the invention for arranging 1 × 2 optical switches in a cascade manner, and as shown in the drawing, in the embodiment, M is a 4-stage binary tree switch, N =2 output terminals are N in total M And (4) the total number of 16,1 multiplied by 2 optical switches is N-1. The photonic integrated circuit is composed of 15 1 × 2 optical switches on an integrated photonic chip, wherein each 1 × 2 optical switch is composed of 1 input end, a first output end and a second output end; the 1 st stage has 1 × 2 optical switch, and the number is 1..1; the 2 nd stage has 2 1 × 2 optical switches, the numbers are 2..1 and 2..2, wherein the first output end of the 1..1 optical switch is connected with the input end of the 2..1 optical switch, and the second output end of the 1..1 optical switch is connected with the input end of the 2..2 optical switch; by analogy, when j =4, that is, the 4 th stage has 8 optical switches, the numbers are 4..1 to 4..8, respectively, wherein the first and second output terminals of the optical switch of the previous stage, which is numbered 3.. K, are connected to the input terminals of the optical switches of numbers 4. (2 k-1) and 4..2k, respectively.
Let the length direction of the 1 × 2 optical switch be the x-axis direction and the width direction be the y-axis direction.
The N-1 multiplied by 2 optical switches are aligned at the center of the photonic chip along the y-axis direction and are arranged into a one-dimensional array according to the following rule A, the distance between two adjacent 1 multiplied by 2 optical switches is equal, the distance can just walk one optical waveguide, and the N-1 multiplied by 2 optical switches are wired according to the following rule B; the input waveguide and the output waveguide of the 1 × 2 optical switch are along the x-axis direction and located on two sides of the 1 × 2 optical switch in the x-axis direction, and the propagation direction of the optical signal in the optical switch is along the + x-axis.
In this embodiment: assuming that the 1 × 2 optical switch of No. 1..1 is centered and the center coordinates x =0 and y =0, two optical switches of No. 2..1 and No. 2..2 of the 2 nd stage are respectively placed on the + y axis side and the-y axis side of the optical switch of No. 1.. 1. The 3 rd-level optical switches with numbers 3..1 and 3..2 are respectively arranged on the side of the + y axis and the side of the-y axis of the optical switch with the number 2..1, and the two optical switches with numbers 3..3 and 3..4 are respectively arranged on the side of the + y axis and the side of the-y axis of the optical switch with the number 2.. 2. The 4 th-level optical switches with numbers 4..1 and 4..2 are respectively arranged on the side of the + y axis and the side of the-y axis of the optical switch with the number 3..1, the two optical switches with the numbers 4..3 and 4..4 are respectively arranged on the side of the + y axis and the side of the-y axis of the optical switch with the number 3..2, the two optical switches with the numbers 4..5 and 4..6 are respectively arranged on the side of the + y axis and the side of the-y axis of the optical switch with the number 3..3, and the two optical switches with the numbers 4..7 and 4..8 are respectively arranged on the side of the + y axis and the side of the-y axis of the optical switch with the number 3.. 4.
The input waveguide and the output waveguide of all the optical switches are along the x-axis direction and are positioned at two sides of the optical switches along the x-axis direction, and the propagation direction of optical signals in the optical switches is along the + x-axis. All the optical switches are aligned and arranged into a one-dimensional array along the y axis, the spacing between every two adjacent optical switches is equal, and the spacing between every two adjacent optical switches can just run on one optical waveguide.
Fig. 2 is a schematic diagram of an embodiment of step-by-step waveguide routing for a completely arranged 1 × 2 optical switch array according to the present invention, and as shown in the figure, M is a 4-step binary tree switch in this embodiment.
In this embodiment: firstly, the output ends of all the optical switches of the 4 th level are led out by using waveguides to be used as 16 paths of output of the 1 x 16 optical switches; the input ends of two 4 th-stage optical switches with numbers 4..1 and 4..2 are connected to the first and second output ends of the optical switch with number 3..1 by waveguides, and the waveguides pass through the optical switch array from two sides of the optical switch with number 3..1 in a zigzag mode, and are prevented from crossing the existing waveguides. In the same way, the input ends of the two optical switches with the numbers 4..3 and 4..4 are connected to the first output end and the second output end of the optical switch with the number 3..2 by using waveguides; connecting input ends of two optical switches numbered 4..5 and 4..6 to first and second output ends of an optical switch numbered 3..3 by using waveguides; connecting the input ends of the two optical switches with the numbers 4..7 and 4..8 to the first and second output ends of the optical switch with the numbers 3..4 by using waveguides, so that the input ends of all the optical switches of the 4 th level complete waveguide routing and enter the 3 rd level waveguide routing; the input ends of the 3 rd-level optical switches with the numbers of 3..1 and 3..2 are connected to the first output end and the second output end of the optical switch with the numbers of 2..1 by waveguides, and the input ends of the 3 rd-level optical switches with the numbers of 3..3 and 3..4 are connected to the first output end and the second output end of the optical switch with the numbers of 2..2 by waveguides, so far, the input ends of all the 3 rd-level optical switches complete waveguide wiring and enter the 2 nd-level waveguide wiring. The input ends of the 2 nd-level optical switches with the numbers 2..1 and 2..2 are connected with the first output end and the second output end of the optical switch with the number 1..1 by using waveguides, so that the waveguide wiring is completed at the input ends of all the optical switches except the optical switch with the number 1.. 1. And finally, leading out the input end of the optical switch with the number 1..1 by using a waveguide as the input of the 1 × 16 optical switch.
It can be seen that assuming that the length and width of the optical switch are L and W, respectively, the total chip area is 15LW ignoring the waveguide trace size.
Fig. 3 is a schematic diagram of an optical switch arrangement employing the present invention for the first 3 levels of a 4-level binary tree. It can be seen that the total chip area is 16LW.
Fig. 4 is a schematic diagram of an unoptimized binary tree of optical switch arrangements arranged sequentially along the x-axis direction. It can be seen that the total chip area is 32LW, much larger than the chip area in fig. 2 and 3.
The above detailed description of a preferred embodiment of the invention is not intended to limit the scope of the invention. All changes, equivalents, and improvements that come within the scope of the invention are intended to be embraced therein.
Claims (2)
1. A photonic integrated chip of 1 xN optical switches based on an M-level binary tree is characterized by consisting of 1 x 2 optical switches on N-1 integrated photonic chips, and N =2 M (ii) a Each 1 × 2 optical switch is composed of 1 input terminal, a first output terminal and a second output terminal;m is the progression of a binary tree;
1, 1 st level of 1X 2 photoswitch is provided with the number 1..1; the 2 nd stage has 2 1 × 2 optical switches, the numbers are 2..1 and 2..2, wherein the first output end of the 1..1 optical switch is connected with the input end of the 2..1 optical switch, and the second output end of the 1..1 optical switch is connected with the input end of the 2..2 optical switch; by analogy, the j-th level has 2 (j-1) Optical switches with numbers of j.1 to j.2 (j-1) Wherein the first and second output terminals of the optical switch with the number (j-1). K at the previous stage are respectively connected with the input terminals of the optical switches with the numbers j. (2 k-1) and j..2k, wherein j and k are positive integers, j is more than or equal to 2 and less than or equal to M, and k is more than or equal to 1 and less than or equal to 2 (j-2) ；
The length direction of a 1X 2 optical switch is set as the x-axis direction, and the width direction is set as the y-axis direction;
the N-1 multiplied by 2 optical switches are aligned at the center of the photonic chip along the y-axis direction and are arranged into a one-dimensional array according to the following rule A, the distance between two adjacent 1 multiplied by 2 optical switches is equal, the distance just passes through one optical waveguide, and the N-1 multiplied by 2 optical switches are wired according to the following rule B; the input waveguide and the output waveguide of the 1 × 2 optical switch are along the x-axis direction and are positioned at two sides of the 1 × 2 optical switch in the x-axis direction, and the propagation direction of an optical signal in the optical switch is along the + x-axis;
the rule a is specifically:
step A1, using a1 multiplied by 2 optical switch with the number 1..1 as a center, namely a center coordinate (0, 0);
step A2, placing the two optical switches with the numbers j. (2 k-1) and j..2k on the side of the + y axis and the side of the-y axis of the optical switch with the number j-1, respectively, and aligning along the y axis, and ensuring that the two optical switches with the numbers j. (2 k-1) and j..2k are closer to the optical switch with the number (j-1). K than the other arranged optical switches;
step A3, increasing k in sequence, and repeating the step A2 until all the optical switches of the j level are arranged;
step A4: sequentially increasing j and repeating the steps A2-A3 until all stages are arranged;
the rule B is specifically:
b1, leading out the output ends of all the optical switches of the Mth level by using waveguides with the same length as N paths of output of the 1 xN optical switch;
and step B2: connecting input ends of two optical switches with the serial number j.2k-1 and the serial number j.2k to a first output end and a second output end of an optical switch with the serial number (j-1). K by using waveguides, wherein the waveguides respectively pass through the optical switch array from two sides of the optical switch with the serial number (j-1) in a Z-shaped mode and avoid crossing with the existing waveguides, j is more than or equal to 2 and less than or equal to M, k is more than or equal to 1 and less than or equal to 2 (j-2) ；
And step B3: sequentially increasing k, and repeating the step B2 until the input ends of all the optical switches of the j level complete waveguide routing, and ensuring the waveguide routing lengths among all levels to be equal;
and step B4: sequentially reducing j, and repeating the steps B2-B3 until the input ends of all the optical switches except the optical switch numbered 1..1 finish waveguide routing;
and step B5: the input end of the optical switch No. 1..1 is led out by a waveguide as the input of the 1 × N optical switch.
2. The photonic integrated chip of the M-level binary tree based 1 × N optical switches according to claim 1, wherein each 1 × 2 optical switch further includes two metal electrodes, wherein the ground electrode is shared and led out from the right side of the optical switch array, i.e. one side in the + x direction, and is routed to the chip edge along the y-axis direction, and the other control electrode can be led out from the left side of the optical switch array, i.e. one side in the-x direction, and is respectively routed to the chip edge along the y-axis direction; or,
metal pads are directly manufactured near two metal electrodes of each 1X 2 optical switch, and an electric chip for controlling the optical switch is connected with the optical chip by using a flip chip mode.
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| CN112630889A (en) * | 2021-03-05 | 2021-04-09 | 苏州海光芯创光电科技股份有限公司 | Photon integrated chip for processing multimode optical signal |
| CN113589435A (en) * | 2021-07-07 | 2021-11-02 | 北京大学 | Full passive polarization quantum state chromatography method and chip |
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