CN115015618A

CN115015618A - Radio frequency power supply signal acquisition method and device

Info

Publication number: CN115015618A
Application number: CN202210943879.8A
Authority: CN
Inventors: 唐亚海; 林桂浩; 乐卫平; 张桂东; 金娜
Original assignee: Shenzhen CSL Vacuum Science and Technology Co Ltd
Current assignee: Shenzhen CSL Vacuum Science and Technology Co Ltd
Priority date: 2022-08-08
Filing date: 2022-08-08
Publication date: 2022-09-06
Anticipated expiration: 2042-08-08
Also published as: CN115015618B; TW202407355A

Abstract

The application discloses and provides a radio frequency power supply signal acquisition method and a radio frequency power supply signal acquisition device, wherein the method comprises the following steps: determining a rising edge interval and a falling edge interval in the current pulse period; the data bits corresponding to the rising edge interval and the falling edge interval in the sampling array are set to be 0, and the signals are low-order or empty signals, so that the problem that in the prior art, because the acquisition board continuously acquires the voltage and current signals and continuously outputs the signals, even in a startup and shutdown mode and a PULSE mode, the signals are continuously acquired and output in a ramp generation stage, and output data are inaccurate is solved.

Description

Radio frequency power supply signal acquisition method and device

Technical Field

The invention relates to the technical field of radio frequency power supply signal acquisition, in particular to a radio frequency power supply signal acquisition method and device.

Background

A typical data acquisition system collects signals from the surrounding environment or from various objects through various sensors. Generally, these signals are generated randomly, so the data acquisition system must sample constantly to ensure that any significant signal is not missed. In a radio frequency power supply, a current acquisition board acquires voltage and current signals in a continuous sampling mode, and in the prior art, because the acquisition board continuously acquires the voltage and current signals and continuously outputs the signals, even in a switching on/off mode and a PULSE mode, the signals are continuously acquired and output in a ramp generation stage, so that the problem of inaccurate output data is caused.

Disclosure of Invention

Therefore, the technical problem to be solved by the present invention is to overcome the problem of inaccurate output data caused by the fact that the acquisition board continuously acquires the voltage and current signals and continuously outputs the signals even in the on-off and PULSE modes during the ramp generation phase in the conventional rf power supply technology, thereby providing a method and a device for acquiring rf power supply signals.

In order to solve the above technical problem, the disclosed embodiments of the present invention at least provide a method and an apparatus for acquiring a radio frequency power signal.

In a first aspect, an embodiment of the present disclosure provides a radio frequency power signal acquisition method, including:

determining a rising edge interval and a falling edge interval in the current pulse period;

and setting data bits corresponding to the rising edge interval and the falling edge interval in the sampling array as 0, a signal low bit or a null signal.

Optionally, the setting of the data bit corresponding to the rising edge interval and the falling edge interval in the sampling array to be 0, and the signal low bit or null signal are: and setting data bits corresponding to the rising edge interval and the falling edge interval in the sampling array as 0, signal low-order bits or null signals in a sampling delay or sampling data output 0 mode.

Optionally, the setting the data bits corresponding to the rising edge interval and the falling edge interval in the sampling array to 0, the signal low bit or the null signal by means of sampling delay or sampling data output to 0 includes: in a rising edge interval, setting a data bit corresponding to the rising edge interval in a sampling array as 0, a signal low bit or a null signal by delaying sampling time during data sampling, or setting the data bit corresponding to the rising edge interval in the sampling array as 0, a signal low bit or a null signal during sampling data output; in the falling edge interval, during data sampling, setting the data bit corresponding to the falling edge interval in the sampling array as 0, signal low bit or null signal through delaying sampling time, or, during sampling data output, setting the falling edge interval in the sampling array or the data bit corresponding to the falling edge interval as 0, signal low bit or null signal.

Optionally, the setting the data bit corresponding to the rising edge interval in the sampling array to 0, the signal low bit or the null signal by delaying the sampling time includes: starting from a rising edge starting point in a current pulse period, starting a first sampling delay, and setting a data bit corresponding to the first sampling delay in a sampling array as 0, a signal low bit or a null signal; the setting of the data bit corresponding to the falling edge interval in the sampling array to 0, the signal low order or the null signal by delaying the sampling time comprises: starting from the starting point of the falling edge in the current pulse period, starting second sampling delay, and setting the data bit corresponding to the second sampling delay in the sampling array as 0, a signal low bit or a null signal.

Optionally, the setting the data bit corresponding to the rising edge interval in the sampling array to 0, the signal low bit, or the null signal includes: when signal sampling of a rising edge end point in a current pulse period is finished, determining first abnormal data, wherein the first abnormal data is data in a sampling array, which starts from a data bit corresponding to the rising edge end point and counts forwards within a first preset length, the first abnormal data is set to be 0, a signal is low or a null signal, and the first preset length is the array length corresponding to a rising edge interval;

the setting of the data bit corresponding to the falling edge interval in the sampling array to 0, the signal low bit or the null signal includes: and determining second abnormal data while finishing signal sampling of a falling edge end point in the current pulse period, wherein the second abnormal data is data in a sampling array, which starts from a data bit corresponding to the falling edge end point and counts forwards within a second preset length, the second abnormal data is set to be 0, a signal is low or a null signal, and the second preset length is the array length corresponding to a falling edge interval.

Optionally, the setting of the data bit corresponding to the first sampling delay in the sampling array to 0, and the signal low order or null signal is: setting a data bit corresponding to a first preset sampling duration in the sampling array as 0, and ending the time delay when the signal is low or null; setting the data bit corresponding to the second sampling delay in the sampling array to be 0, and setting the signal low bit or the null signal as follows: and setting the data bit corresponding to the second preset sampling duration in the sampling array as 0, and ending the time delay when the signal is low or empty.

Optionally, the setting of the data bit corresponding to the first sampling delay in the sampling array to be 0, and the signal low bit or the null signal are: setting a data bit corresponding to the length of a first preset array in the sampling array as 0, and ending the time delay when the signal is low or empty; setting the data bit corresponding to the second sampling delay in the sampling array to be 0, and setting the signal low bit or the null signal as follows: and setting the data bit corresponding to the second preset array length in the sampling array as 0, and setting the signal low bit or the null signal, and finishing the time delay.

Optionally, the determining the rising edge interval and the falling edge interval in the current pulse period includes:

determining a rising edge interval and a falling edge interval in the current pulse period through a reference threshold, the rising edge duration and the falling edge duration, wherein the reference threshold is used for marking the low bit of a signal; or the like, or, alternatively,

determining a rising edge interval and a falling edge interval in the current pulse period according to the reference threshold and a top threshold, wherein the top threshold is used for marking the high bits of the signal; or the like, or, alternatively,

and determining a rising edge interval and a falling edge interval in the current pulse period through the power change of the sampling points.

Optionally, the first preset sampling duration is equal to a rising edge duration, and the second preset sampling duration is equal to a falling edge duration.

Optionally, the first preset array length and the second preset array length are determined according to a preset operational relationship between the rising edge duration or the falling edge duration and a sampling period.

Optionally, the first preset array length = rising edge duration/sampling period, and the second preset array length = falling edge duration/sampling period; or the first preset array length = the second preset array length = rising edge duration/sampling period; or, the first preset array length = the second preset array length = falling edge duration/sampling period.

Optionally, the determining the rising edge interval and the falling edge interval in the current pulse period according to the power variation of the sampling point includes: acquiring a rising edge starting point, wherein the rising edge starting point is a sampling point of which the power is greater than a rising edge reference threshold value for the first time in the current pulse period; and acquiring a falling edge starting point, wherein the falling edge starting point is a sampling point of which the power is smaller than a falling edge reference threshold value for the first time in the current pulse period.

Optionally, the method further includes: and reading and sequentially outputting sampling data by the sampling array outside the rising edge interval and the falling edge interval.

Optionally, if the first preset array length = the second preset array length = rising edge duration/sampling period, and the rising edge duration is greater than the falling edge duration, setting the data bits corresponding to the rising edge interval and the falling edge interval in the sampling array to 0, a signal low bit or a null signal by means of sampling delay or sampling data output of 0 includes: when sampling data is output, when signal sampling is finished on a falling edge end point in a current pulse period, calculating the duration of a third delay, wherein the third delay duration is the difference value between the rising edge duration and the falling edge duration, starting the third delay, when the third delay is finished, determining third different constant data, wherein the third different constant data is data in a third preset length counted from a data bit corresponding to the third delay end point in the sampling array, setting the third different constant data to be 0, a signal low bit or an empty signal, and the third preset length is the array length corresponding to the falling edge interval.

In a second aspect, an embodiment of the disclosure further provides a radio frequency power signal acquisition apparatus, including:

the abnormal data interval determining module is used for determining a rising edge interval and a falling edge interval in the current pulse period;

and the sampling data 0 setting module is used for setting the data bit corresponding to the falling edge interval in the rising edge interval in the sampling array to be 0, a signal low bit or a null signal.

In a third aspect, an embodiment of the present disclosure further provides a computer device, including: a processor, a memory and a bus, the memory storing machine-readable instructions executable by the processor, the processor and the memory communicating via the bus when the computer device is running, the machine-readable instructions when executed by the processor performing the steps of the first aspect described above, or any possible implementation of the first aspect.

In a fourth aspect, the disclosed embodiments of the present invention further provide a computer-readable storage medium, where a computer program is stored on the computer-readable storage medium, and the computer program is executed by a processor to perform the steps in the first aspect or any possible implementation manner of the first aspect.

The technical scheme provided by the embodiment of the invention has the following beneficial effects:

determining a rising edge interval and a falling edge interval in the current PULSE period, setting data bits corresponding to the rising edge interval and the falling edge interval in a sampling array as 0, a signal low bit or a null signal, and using FIFO (First Input First Output) sampling array set 0 to shield data of an abnormal section, namely enabling the data of a slope section to be Output to be 0 in the on-off and PULSE modes, and outputting power only in a correct time period outside the slope.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention, as claimed.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and other drawings can be obtained by those skilled in the art without creative efforts.

FIG. 1 is a flow chart illustrating a method for collecting a radio frequency power signal according to an embodiment of the disclosure;

FIG. 2 is a flow chart illustrating another method for collecting RF power signals according to the disclosed embodiment of the invention;

FIG. 3 is a schematic diagram showing a pulse structure in a disclosed embodiment of the invention;

FIG. 4 shows a schematic diagram of a pulse structure of example 1 in an embodiment of the present disclosure;

FIG. 5 is a schematic diagram showing a pulse structure of example 2 in an embodiment of the present disclosure;

FIG. 6 shows a schematic diagram of a pulse structure of example 3 in an embodiment of the present disclosure;

FIG. 7 is a schematic structural diagram of a radio frequency power signal acquisition device according to an embodiment of the disclosure;

fig. 8 shows a schematic structural diagram of a computer device according to an embodiment of the present disclosure.

Detailed Description

Reference will now be made in detail to the exemplary embodiments, examples of which are illustrated in the accompanying drawings. The following description refers to the accompanying drawings in which the same numbers in different drawings represent the same or similar elements unless otherwise indicated. The implementations described in the following exemplary examples do not represent all implementations consistent with the present invention. Rather, they are merely examples of apparatus and methods consistent with certain aspects of the invention, as detailed in the appended claims.

Example 1

As shown in fig. 1, a flowchart of a radio frequency power signal acquisition method provided in an embodiment of the present disclosure includes:

s11: determining a rising edge interval and a falling edge interval in the current pulse period;

s12: setting data bits corresponding to a rising edge interval and a falling edge interval in a sampling array as 0, and setting a signal low bit or a null signal;

s13: and reading and sequentially outputting sampling data by the sampling array outside the rising edge interval and the falling edge interval.

It can be understood that, in the technical scheme provided in this embodiment, a rising edge interval and a falling edge interval in a current PULSE period are determined, data bits corresponding to the rising edge interval and the falling edge interval in a sampling array are set to 0, a signal is low or a null signal, and a FIFO (First Input First Output) is used to sample the array set to 0 to mask off data in an abnormal section, that is, the data in a slope section in the on-off and PULSE modes is Output as 0, and power is Output only in a correct time period other than the slope.

Example 2

Referring to fig. 3, a flow chart of another rf power signal acquisition method according to an embodiment of the disclosure is shown in fig. 2, and the method masks off abnormal data generated in a ramp phase in a pulse period, and includes:

s21: determining a rising edge interval and a falling edge interval in the current pulse period;

s22: setting data bits corresponding to a rising edge interval and a falling edge interval in a sampling array as 0, and setting a signal low bit or a null signal;

s23: and reading and sequentially outputting sampling data by the sampling array outside the rising edge interval and the falling edge interval.

In some embodiments, the S22 setting the data bits corresponding to the rising edge interval and the falling edge interval in the sample array to 0, the low signal or the null signal may be: and setting data bits corresponding to the rising edge interval and the falling edge interval in the sampling array as 0, signal low bits or null signals in a sampling delay or sampling data output 0 mode.

In some embodiments, S22 may include the steps of:

s221: in the rising edge interval, different data processing modes can be adopted according to different data judgment modes. The data determination mode includes:

(A) whether the input signal is converted from the signal low position to the rising edge section is judged through the reference threshold, namely, when the signal data is lower than the reference threshold, the signal is considered to be the signal low position (or the signal zero position is output, or the signal is output by 0), when the signal data is higher than the reference threshold, the signal is considered to climb to the high position, and the climbing process is considered to be the rising edge section.

When the sampling data is read, once the sampling data read and preset in the sampling array exceeds a reference threshold value, the signal is considered to enter a rising edge, and the sampling delay is started at the moment. And when the sampling delay is finished, the normal reading operation of the sampling data is resumed. In some embodiments, the duration of the sampling delay is the duration of the rising edge interval. According to the length of the corresponding acquisition array, a corresponding data processing mode is adopted, and the following description is given:

(A-1) when the time length corresponding to the data bit of the acquisition array is greater than or equal to the time length of the rising edge interval, selecting and processing the following modes:

and (A-11) in the sampling delay period, the read sampling data is firstly set to be 0, and the signal is low or empty, and then the sampling array is filled.

And (A-12) marking the sampling data read in the sampling delay period, importing the sampling data of the sampling array, and setting the data bit corresponding to the rising edge interval in the sampling array as 0, signal low bit or null signal when the sampling data is output.

(A-13) starting the time of the delayed sampling time, keeping the data of the whole sampling array still in FIFO operation no matter what kind of sampling data is read, and when the delayed sampling time is over, setting the total number of data columns in the sampling array to be 0, and setting the signal to be low or null signals, and simultaneously carrying out normal data sampling operation.

And (A-2) when the time length corresponding to the data bit of the acquisition array is less than the time length of the rising edge interval, processing the read data in a mode of (A-11) or (A-12).

(B) And judging whether the input signal is converted from the low signal position to the rising edge section or not through the reference threshold value, and judging whether the input signal is converted from the rising edge section to the high signal position or not through the top threshold value.

When the sampling data is read, once the sampling data read and preset to be led into the sampling array exceeds a reference threshold value, the signal is considered to enter a rising edge, and the sampling delay is started at the moment. When the sample data read and predetermined to be led into the sample array exceeds the top threshold value, the signal is considered to enter the high bit of the signal from the rising edge. At this time, the sampling delay is finished, and the normal operation of reading and filling the sampling data array is recovered.

In some embodiments, when the duration of the rising edge interval is known, the corresponding data processing method according to the length of the corresponding acquisition array is as described in (a-1) and (a-2).

In some embodiments, the duration of the sampling delay is dependent on the duration of the read sample value between the base threshold and the top threshold, i.e., by the actual duration of the rising edge interval. That is, the low, rising, and high signal bits are determined only by the reference threshold and the top threshold. The data processing is performed as described in (A-1) and (A-2).

(C) And comparing the sampled values read before and after, and judging whether the input signal is converted from a signal low position to a rising edge interval or not and whether the input signal is converted from the rising edge interval to a signal high position or not according to the change of the data size.

When the sampling data is read, once a plurality of continuous sampling data which are preset to be led into the sampling array are read, the constant low-order data are changed into rising data (the read front data is lower than the read back data), the signal is considered to enter the rising edge, and the sampling delay is started. When a plurality of continuous sampling data which are read and are preset to be led into the sampling array are changed into constant high-order data from rising data (the read front data is equal to the read back data), the signal is considered to enter the high order of the signal from the rising edge, the sampling delay is finished, and the normal operation of reading and filling the sampling array of the sampling data is recovered.

In some embodiments, the duration of the sampling delay is dependent on the duration of the read sample value between the base threshold and the top threshold, i.e., by the actual duration of the rising edge interval. That is, the low, rising and high signal bits can be determined by the conversion between the constant data and the rising data without considering the duration of the rising edge interval. The data processing is as described in (A-11) and (A-12).

S222: in the falling edge interval, different data processing modes can be adopted according to different data judgment modes. The data determination mode includes:

(D) whether the input signal reaches the falling edge interval and turns to the low position of the signal is judged through the reference threshold value, namely, the signal reaches the tail end of the falling edge interval, and further the signal can be regarded as the low position, zero position or no output of the incoming signal.

When the sampling data is read, once the sampling data read and preset to be led into the sampling array is lower than a reference threshold value, the signal is considered to pass through the tail end of the falling edge, even the signal reaches the low position, the zero position or no output, and the sampling delay is started at the moment. And when the sampling delay is finished, the normal reading operation of the sampling data is resumed.

In some embodiments, the sampling delay is equal to the sum of the sampling durations of the data bits of the acquisition array and the duration of the falling edge. And the sum of the data sampling duration corresponding to the data bits of the acquisition array is not less than the falling edge duration. According to the length of the corresponding acquisition array, the delay processing mode is as follows:

(D-1) the sum of the data sampling time lengths corresponding to the data bits of the acquisition array is equal to the falling edge time length, and the sampling delay time length is 0, namely, the sampling delay is not started, and the subsequent data processing is directly carried out.

(D-2) acquiring data sampling time length sum corresponding to the data bits of the array, wherein the data sampling time length sum is larger than the falling edge time length, the sampling delay time length is the difference value of the sampling delay time length sum and the falling edge time length, and performing subsequent data processing after the delay time is finished.

In some embodiments, if the sample-delay period (D-2) is enabled, no matter what sample data is read, the data in the entire sample array still keeps FIFO operation, and when the sample delay time is over (or the sample delay is not enabled in D-1), the total number of data fields in the sample array is set to 0, and the signal is low or null, and normal data sampling operation is performed.

(E) Whether the input signal is converted from the high signal level to the falling edge section is determined through the top threshold, that is, when the signal data is higher than the top threshold, the signal data is regarded as the high signal level, and when the signal data is lower than the top threshold, the signal data is regarded as the falling of the signal towards the low level, and the falling process is regarded as the falling edge section.

When the sampling data is read, once the sampling data read and preset to be led into the sampling array is lower than a top threshold value, the signal is considered to enter a falling edge, and the sampling delay is started at the moment. And when the sampling delay is finished, the normal reading operation of the sampling data is resumed.

In some embodiments, the duration of the sampling delay is the sum of the duration of the falling edge interval and the data sampling duration corresponding to the data bits of the acquisition array, whichever is longer; if the two are the same, any one of them is acceptable. Therefore, after the delay is over, the read collected data will fall to the low signal level.

According to the length of the corresponding acquisition array, a corresponding data processing mode is adopted, and the following description is given:

(E-1) when the time length corresponding to the data bit of the acquisition array is greater than or equal to the time length of the falling edge interval, selecting for processing in the following mode:

and (E-11) during the sampling delay period, the read sampling data is firstly set to be 0, and the signal is low or empty, and then the sampling array is filled.

And (E-12) marking the sampling data read in the sampling delay period, importing the sampling data of the sampling array, and setting the data bit corresponding to the falling edge interval in the sampling array as 0, signal low bit or null signal when the sampling data is output.

(E-13) starting the time of the delayed sampling time, keeping the data of the whole sampling array still in FIFO operation no matter what kind of sampling data is read, and when the delayed sampling time is over, setting the total number of data columns in the sampling array to be 0, and setting the signal to be low or null signals, and simultaneously carrying out normal data sampling operation.

And (E-2) when the time length corresponding to the data bit of the acquisition array is less than the time length of the falling edge interval, processing the read data in the mode of (E-11) or (E-12).

(F) And judging whether the input signal is converted from a high signal position to a low signal position or not through a top threshold value and judging whether the input signal is converted from the low signal position or not through a reference threshold value.

When the sampling data is read, once the sampling data read and preset to be led into the sampling array is lower than a top threshold value, the signal is considered to enter a falling edge, and the sampling delay is started at the moment. When the sample data read and predetermined to be led into the sample array is lower than the reference threshold value, the signal is considered to enter the low position of the signal from the falling edge. At this time, the sampling delay is finished, and the normal operation of reading and filling the sampling data array is recovered.

In some embodiments, the duration of the sampling delay is dependent on the duration of the read sample value between the base threshold and the top threshold, i.e., the actual duration of the falling edge interval. That is, the high, low, and low signal bits are determined only by the reference threshold and the top threshold. The data processing is performed as described in (E-1) and (E-2).

(G) And comparing the sampled values read before and after, and judging whether the input signal is converted from a high signal position to a falling edge interval or not and whether the input signal is converted from the falling edge interval to a low signal position or not according to the change of the data size.

When the sampling data is read, once a plurality of continuous sampling data which are preset to be led into the sampling array are read, the constant high-order data are changed into ascending data (the read front data is lower than the read back data), the signal is considered to enter a falling edge, and the sampling delay is started. When a plurality of continuous sampling data which are read and are preset to be led into the sampling array are changed into constant low-order data from falling data (the read front data is equal to the read back data), the signal is considered to enter the low-order of the signal from the falling edge, the sampling delay is finished at the moment, and the normal operation of reading and filling the sampling array of the sampling data is recovered.

In some embodiments, when the duration of the falling edge interval is known, the corresponding data processing method is adopted according to the length of the corresponding acquisition array as described in (E-1) and (E-2).

In some embodiments, the duration of the sampling delay is dependent on the duration of the read sample value between the base threshold and the top threshold, i.e., by the actual duration of the rising edge interval. That is, the low, rising and high bits of the signal can be determined by the conversion between the constant data and the rising data without considering the duration of the rising edge interval. The data processing is as described above in (E-11) and (E-12).

In some embodiments, S22 includes: and during data sampling, setting the data bit corresponding to the falling edge interval in the sampling array as 0, signal low bit or null signal by delaying the sampling time, or setting the data bit corresponding to the falling edge interval or falling edge interval in the sampling array as 0, signal low bit or null signal when the sampling data is output.

In some embodiments, S221 may include: starting from a rising edge starting point in a current pulse period, starting a first sampling delay, and setting a data bit corresponding to the first sampling delay in a sampling array as 0, a signal low bit or a null signal;

the setting of the data bit corresponding to the falling edge interval in the sampling array to 0 and the signal low bit or null signal by delaying the sampling time may include: starting from the starting point of the falling edge in the current pulse period, starting second sampling delay, and setting the data bit corresponding to the second sampling delay in the sampling array as 0, a signal low bit or a null signal.

In some embodiments, especially in some cases where the rising edge power reference threshold is not available, S222 may include: when signal sampling is finished on a rising edge end point in a current pulse period, determining first abnormal data, wherein the first abnormal data is data in a sampling array, the data in a first preset length is counted from a data bit corresponding to the rising edge end point to the front, the first abnormal data is set to be 0, a signal is low or a null signal, and the first preset length is the array length corresponding to a rising edge interval;

the setting of the data bit corresponding to the falling edge interval in the sampling array to 0, the signal low bit or the null signal may be implemented through the following processes: and determining second abnormal data while finishing signal sampling of a falling edge end point in the current pulse period, wherein the second abnormal data is data in a sampling array, starting from a data bit corresponding to the falling edge end point and counting forward within a second preset length, the second abnormal data is set to be 0, and a signal is low or a null signal, and the second preset length is an array length corresponding to a falling edge interval.

In some embodiments, the setting of the data bit corresponding to the first sample delay in the sample array to 0, and the low-order or null signal may be: setting a data bit corresponding to a first preset sampling time length in the sampling array as 0, and ending the time delay when the signal is low or null; the setting of the data bit corresponding to the second sampling delay in the sampling array to 0, and the signal low bit or null signal may be: and setting the data bit corresponding to the second preset sampling duration in the sampling array as 0, and ending the time delay when the signal is low or empty.

In some embodiments, the setting of the data bit corresponding to the first sample delay in the sample array to 0, and the low-order or null signal may be: setting a data bit corresponding to the length of a first preset array in the sampling array as 0, and ending the time delay when the signal is low or empty; the setting of the data bit corresponding to the second sampling delay in the sampling array to 0, and the signal low bit or null signal may be: and setting the data bit corresponding to the second preset array length in the sampling array as 0, and setting the signal low bit or the null signal, and finishing the time delay.

In some embodiments, S21 may include:

a. determining a rising edge interval and a falling edge interval in the current pulse period through a reference threshold, the rising edge duration and the falling edge duration, wherein the reference threshold is used for marking the low bit of a signal; or the like, or, alternatively,

b. determining a rising edge interval and a falling edge interval in the current pulse period through a reference threshold and a top threshold, wherein the top threshold is used for marking the high position of a signal; or the like, or, alternatively,

c. and determining a rising edge interval and a falling edge interval in the current pulse period through the power change of the sampling points.

In some embodiments, the method specifically includes performing detection sampling, taking a sampling period as a base number, taking the sampling period as a starting time when the power rises above an ascending threshold value, taking the power rises above a descending threshold value as an ending time, and calculating the number of samples or sampling timing to obtain an ascending edge interval; on the contrary, the number of samples or the sampling timing is calculated to obtain a falling edge section starting when the power falls below the falling threshold and ending when the power reaches the rising threshold.

In some embodiments, the first sampling delay time period is equal to the rising edge time period and the second sampling delay time period is equal to the falling edge time period.

In some embodiments, the first predetermined array length is greater than or equal to the falling edge duration/sampling period, and the second predetermined array length is greater than or equal to the falling edge duration/sampling period.

In some embodiments, the first preset array length and the second preset array length are determined by the rising edge duration or the falling edge duration and the sampling period according to a preset operational relationship.

In one embodiment, the first predetermined array length = rising edge duration/sampling period, and the second predetermined array length = falling edge duration/sampling period; or the first preset array length = the second preset array length = the rising edge duration/sampling period; or, the first preset array length = the second preset array length = the falling edge duration/sampling period.

In some embodiments, if the first preset array length = the second preset array length = the rising edge duration/sampling period, and the rising edge duration is greater than the falling edge duration, setting the data bit corresponding to the rising edge interval and the falling edge interval in the sampling array to 0, the signal low bit or the null signal by sampling the delay or sampling the data output to 0 includes:

when sampling data are output, signal sampling is completed on a falling edge end point in a current pulse period, meanwhile, the duration of a third delay is calculated, the third delay duration is the difference value of the rising edge duration and the falling edge duration, the third delay is started, when the third delay is ended, third different constant data are determined, the third different constant data are data in a sampling array group and count forwards within a third preset length from a data bit corresponding to the third delay end point, the third different constant data are set to be 0, signal low bits or null signals, and the third preset length is the array length corresponding to a falling edge interval.

In some embodiments, S21 may include: acquiring a rising edge starting point, wherein the rising edge starting point is a sampling point of which the power is greater than a reference threshold value for the first time in the current pulse period; acquiring a rising edge end point, wherein the rising edge end point is a sampling point of which the power is greater than a top threshold value for the first time in the current pulse period; acquiring a falling edge starting point, wherein the falling edge starting point is a sampling point of which the power is smaller than a falling edge reference threshold value for the first time in the current pulse period; and acquiring a falling edge end point, wherein the falling edge end point is a sampling point of which the power is smaller than the reference threshold value for the first time in the current pulse period.

For the convenience of the reader to understand, the above rf power signal acquisition method is explained below by using a specific example, first, assuming that the rising edge duration is 10 μ s (T1), and the falling edge duration is 4 μ s (T2), the length of the sample array is set to 5, and the period is 1 μ s:

example 1 (known reference threshold), as shown in fig. 7, 4:

and in the rising edge interval, judging whether the input signal is converted from the low position of the signal to the rising edge interval or not through a reference threshold, and once the sampling data read and preset in a sampling array exceeds the reference threshold, considering that the signal enters the rising edge, and starting sampling delay at the moment. When the first digit of the FIFO array runs to the rising edge A, and the power (Pa) of the next acquisition point exceeds the reference threshold, 10 mus of delay T1 is started, and each datum of the FIFO array is limited to 0. When the first digit of the FIFO array runs to the B point of the rising edge, the sampling delay is finished at the moment, the first digit of the FIFO array starts to fill data, the whole FIFO array is initially filled up until the C point, then according to the FIFO theory, the data is first in first out, the data output before the FIFO array reaches the C point is still 0, the initially input B point data is output until the C point, and the data output until the E point is normal output.

And in the falling edge interval, judging whether the input signal reaches the falling edge interval and turns to a signal low position or not through a reference threshold value, and when the sampling data is read, once the sampling data which is preset to be led into a sampling array is lower than the reference threshold value, considering that the signal passes through the tail end of the falling edge, even reaches the signal low position, zero position or no output, and starting sampling delay at the moment. In the falling edge stage, when the FIFO array initial digit runs to a falling edge F point, the power (Pb) of the acquisition point is lower than a reference threshold value, the data is substantially output as D point data, the starting delay T2=5us-4us =1us, when the delay is finished, the FIFO array initial digit reaches the G point, the mantissa digit reaches the E point, and the FIFO array performs data clear 0 output.

Example 2 (known base threshold, top threshold), as shown in fig. 7, 5:

and in the rising edge interval, judging whether the input signal is converted from the low signal position to the rising edge interval through a reference threshold value, and judging whether the input signal is converted from the rising edge interval to the high signal position through a top threshold value. And in the rising edge stage, when the first digit of the FIFO array runs to the point A of the rising edge and the power (Pa) of the next acquisition point is higher than the reference threshold value, starting sampling delay. When the first digit of the FIFO array runs to the point B of the rising edge and the power (Pa) of the next acquisition point is higher than the top threshold value, the sampling delay is finished at the moment. The first digit of the FIFO array starts to fill data, the whole FIFO array is filled initially until the C digit, then according to the FIFO theory, the data is first in first out, the data output before the FIFO array reaches the C digit is still 0, the data of the B point input initially is output until the C point, and the data output until the E point is normal output.

And in the falling edge interval, judging whether the input signal is converted from a high signal position to a falling edge interval or not through a top threshold value, judging whether the input signal is converted from the falling edge interval to a low signal position or not through a reference threshold value, setting the data bit corresponding to the falling edge interval in the sampling array to be 0, the low signal position or a null signal, and processing the data in the mode of (E-1). When the first digit of the FIFO array runs to the point E of the falling edge, the power (Pb) of the acquisition point is lower than the top threshold value, and the sampling delay is started at the moment; when the first digit of the FIFO array runs to the point F of the falling edge, the power (Pb) of the acquisition point is lower than the reference threshold value, the sampling delay is ended, and the normal operation of reading and filling the sampling data is recovered.

Example 3, as shown in fig. 6:

in the rising edge interval, comparing the sampled values read from front to back, judging whether the input signal is converted from a signal low position to the rising edge interval or not and whether the input signal is converted from the rising edge interval to a signal high position or not according to the change of the data size, specifically determining the rising edge interval in the current pulse period according to the power change of the sampling point, setting the data bit corresponding to the falling edge interval in the sampling array as 0, the signal low position or a null signal, and processing the data in the mode of (A-1) or (A-1) as described above.

The low power data collected from the start to point a is accurate; the point A to the point B are ascending slopes, and the acquired data are inaccurate; the high power data collected from point B to point C is accurate.

In the falling edge interval, the data processing mode is as above (E-1) and (E-2) by comparing the sampled values read back and forth and determining whether the input signal is converted from the high signal level to the falling edge interval and from the falling edge interval to the low signal level according to the data size change.

The point C to the point D is a descending slope, and the acquired data is inaccurate at the moment; the low power data collected from point D to point E is accurate. The chronological order of the acquired successive three-point power values P1, P2 and P3 is shown in fig. 6, with P1 being the latest acquired data, P2 times, and P3 being the earliest acquired data.

Sequentially carrying out difference on the acquired power values to obtain variation quantity delta 1= P1-P2, and delta 2= P2-P3; Δ th is greater than 0, a threshold for determining whether the acquired data is accurate. When the absolute values of the two variations are both greater than or equal to 0, a null signal value or a signal low-order value, and less than a decision threshold Δ th, the acquired data is accurate. At this time, the acquired corresponding data is retained, otherwise, the abnormal data bit is set to be 0, a null signal value or a signal low-order value, or, when the sampling data is output, the data output of the abnormal data bit is skipped, that is, the absolute value of at least one of Δ 1 and Δ 2 is greater than or equal to + Δ th, the data is incorrect, and the acquired data is completely discarded under the condition.

It should be noted that, in the embodiment of the present invention, the rising edge duration (c) isT ₁ ) And falling edge duration (T ₂ ) The sampling number or sampling timing can be calculated by taking detection sampling as a base number, taking the sampling period as a base number, taking the power as the beginning when the power rises and exceeds the rising threshold value, and taking the power as the end when the power reaches the falling threshold value, so as to obtain the duration of the rising edge; conversely, the meter starts when the power drops above the drop threshold and ends when the power reaches the rise thresholdThe calculation of the number of samples or the sampling timing to obtain the falling edge duration may also be other manners selected by those skilled in the art according to the engineering requirements, and will not be described herein again. The method is particularly suitable for solving the problem of inaccurate signal acquisition in one PULSE period in the on-off and PULSE modes.

Example 3

As shown in fig. 7, an embodiment of the present invention further provides a radio frequency power signal acquisition apparatus, including:

an abnormal data interval determining module 71, configured to determine a rising edge interval and a falling edge interval in a current pulse period;

a sample data set 0 module 72, configured to set data bits corresponding to the rising edge interval and the falling edge interval in the sample array to 0, a signal low bit, or a null signal.

In some embodiments, as shown in phantom in fig. 7, the apparatus further comprises:

and a FIFO array output module 73, configured to read and output the sample data in sequence by the sample array outside the rising edge interval and the falling edge interval.

In some embodiments, the sample data set to 0 module 72 sets the data bits corresponding to the rising edge interval and the falling edge interval in the sample array to 0, and the low signal or the null signal is: the sample data set 0 module 72 sets the data bits corresponding to the rising edge interval and the falling edge interval in the sample array to 0, signal low or null signals by means of sample delay or sample data output set 0.

In some embodiments, as shown in phantom in fig. 7, sample data set-0 module 72 includes:

the rising edge exception handling sub-module 721 is configured to set, in the rising edge interval, a data bit corresponding to the rising edge interval in the sampling array to 0, a signal low bit, or a null signal by delaying sampling time during data sampling, or set, in the sampling array, the data bit corresponding to the rising edge interval to 0, a signal low bit, or a null signal when sampling data is output;

and the falling edge exception handling submodule 722 is configured to, in the falling edge interval, set the data bit corresponding to the falling edge interval in the sampling array to 0, a signal low bit or a null signal by delaying the sampling time during data sampling, or set the data bit corresponding to the falling edge interval or the falling edge interval in the sampling array to 0, a signal low bit or a null signal during sampling data output.

In some embodiments, the above-mentioned rising edge exception handling sub-module 721 sets the data bit corresponding to the rising edge interval in the sample array to 0, and sets the low bit or the null signal by delaying the sampling time during the sampling process, including: the rising edge exception handling sub-module 721 starts the first sampling delay from the rising edge starting point in the current pulse period, and sets the data bit corresponding to the first sampling delay in the sampling array to 0, a signal low bit or a null signal. The falling edge exception handling submodule 722 sets the data bit corresponding to the falling edge interval in the sample array to 0, sets the signal low bit or null signal by delaying the sampling time, and includes: starting from the starting point of the falling edge in the current pulse period, starting second sampling delay, and setting the data bit corresponding to the second sampling delay in the sampling array as 0, a signal low bit or a null signal.

In some embodiments, the above-mentioned rising edge exception handling sub-module 721 setting the data bit corresponding to the rising edge interval in the sample array to 0, signaling low or null includes: when signal sampling of a rising edge ending point in a current pulse period is finished, determining first abnormal data, wherein the first abnormal data is data in a sampling array, which is counted from a data bit corresponding to the rising edge ending point to a first preset length, the first abnormal data is set to be 0, a signal is low-order or a null signal, and the first preset length is an array length corresponding to a rising edge interval; the falling edge exception handling submodule 722 sets the data bit corresponding to the falling edge interval in the sample array to 0, and sets the signal low bit or null signal to include: and determining second abnormal data while finishing signal sampling of a falling edge end point in the current pulse period, wherein the second abnormal data is data in a sampling array, starting from a data bit corresponding to the falling edge end point and counting forward within a second preset length, the second abnormal data is set to be 0, and a signal is low or a null signal, and the second preset length is an array length corresponding to a falling edge interval.

In some embodiments, the rising edge exception handling sub-module 721 sets the data bit corresponding to the first sampling delay in the sampling array to 0, and the low or null signal is: setting a data bit corresponding to a first preset sampling duration in the sampling array as 0, and ending the time delay when the signal is low or null; the falling edge exception handling submodule 722 sets the data bit corresponding to the second sampling delay in the sampling array to 0, and the signal low bit or null signal is: and setting the data bit corresponding to the second preset sampling duration in the sampling array as 0, and ending the time delay when the signal is low or empty.

In some embodiments, the rising edge exception handling sub-module 721 sets the data bit corresponding to the first sampling delay in the sampling array to 0, and the low or null signal is: the rising edge exception handling sub-module 721 sets the data bit corresponding to the first preset array length in the sampling array to 0, a signal low bit or a null signal, and the delay is finished; the falling edge exception handling submodule 722 sets the data bit corresponding to the second sampling delay in the sampling array to 0, and the signal low bit or null signal is: the falling edge exception handling submodule 722 sets the data bit corresponding to the second preset array length in the sampling array to 0, a signal low bit or a null signal, and the delay is finished.

In some embodiments, the abnormal data interval determination module 71 includes:

a reference threshold determining unit, configured to determine a rising edge interval and a falling edge interval in a current pulse period according to a reference threshold, a rising edge duration, and a falling edge duration, where the reference threshold is used to mark a low bit of a signal; or the like, or, alternatively,

a top threshold determining unit, configured to determine a rising edge interval and a falling edge interval in a current pulse period according to the reference threshold and a top threshold, where the top threshold is used to mark a high bit of a signal; or the like, or, alternatively,

and the power determining unit is used for determining a rising edge interval and a falling edge interval in the current pulse period according to the power change of the sampling point.

In some embodiments, the first preset sampling duration is equal to the rising edge duration and the second preset sampling duration is equal to the falling edge duration.

In some embodiments, as shown by the dashed content in fig. 7, the abnormal data interval determination module 71 includes:

a rising edge starting point obtaining submodule 711, where the rising edge starting point is a sampling point where the power is first greater than a rising edge reference threshold in the current pulse period;

the falling edge starting point obtaining sub-module 712 is a sampling point where the power is first less than the falling edge reference threshold value in the current pulse period.

In some embodiments, if the first preset array length = the second preset array length = the rising edge duration/sampling period, and the rising edge duration is greater than the falling edge duration, the sample data set 0 module 72 sets the data bits corresponding to the rising edge interval and the falling edge interval in the sample array to 0, the signal low bit or the null signal by sampling delay or sampling data output set 0, including: when the sampling data is output, the sampling data setting 0 module 72 calculates a duration of a third delay while completing signal sampling of a falling edge end point in a current pulse period, where the third delay duration is a difference between the rising edge duration and the falling edge duration, starts the third delay, determines a third difference data when the third delay is ended, where the third difference data is data in a sampling array counted from a data bit corresponding to the third delay end point forward within a third preset length, sets the third difference data to 0, a signal low bit or an empty signal, and the third preset length is an array length corresponding to a falling edge interval.

Example 4

Based on the same technical concept, an embodiment of the present application further provides a computer device, which includes a memory 1 and a processor 2, as shown in fig. 8, where the memory 1 stores a computer program, and the processor 2 implements the radio frequency power signal acquisition method according to any one of the above descriptions when executing the computer program.

The memory 1 includes at least one type of readable storage medium, which includes a flash memory, a hard disk, a multimedia card, a card type memory (e.g., SD or DX memory, etc.), a magnetic memory, a magnetic disk, an optical disk, and the like. The memory 1 may in some embodiments be an internal storage unit of the OTT video traffic monitoring system, e.g. a hard disk. The memory 1 may also be an external storage device of the OTT video service monitoring system in other embodiments, such as a plug-in hard disk, a Smart Media Card (SMC), a Secure Digital (SD) Card, a Flash memory Card (Flash Card), and the like. Further, the memory 1 may also include both an internal storage unit and an external storage device of the OTT video service monitoring system. The memory 1 may be used to store not only application software installed in the OTT video service monitoring system and various data, such as codes of OTT video service monitoring programs, but also temporarily store data that has been output or is to be output.

The processor 2 may be a Central Processing Unit (CPU), a controller, a microcontroller, a microprocessor or other data Processing chip in some embodiments, and is used to run program codes stored in the memory 1 or process data, for example, execute an OTT video service monitoring program.

The disclosed embodiment of the present invention further provides a computer-readable storage medium, where a computer program is stored on the computer-readable storage medium, and when the computer program is executed by a processor, the steps of the radio frequency power signal acquisition method described in the above method embodiment are executed. The storage medium may be a volatile or non-volatile computer-readable storage medium.

The computer program product of the radio frequency power signal acquisition method provided by the embodiment of the disclosure of the present invention includes a computer readable storage medium storing a program code, where instructions included in the program code may be used to execute the steps of the radio frequency power signal acquisition method described in the above method embodiment, which may be referred to in the above method embodiment specifically, and are not described herein again.

The embodiments disclosed herein also provide a computer program, which when executed by a processor implements any one of the methods of the preceding embodiments. The computer program product may be embodied in hardware, software or a combination thereof. In an alternative embodiment, the computer program product is embodied in a computer storage medium, and in another alternative embodiment, the computer program product is embodied in a Software product, such as a Software Development Kit (SDK) or the like.

It is understood that the same or similar parts in the above embodiments may be mutually referred to, and the same or similar parts in other embodiments may be referred to for the content which is not described in detail in some embodiments.

It should be noted that the terms "first," "second," and the like in the description of the present invention are used for descriptive purposes only and are not to be construed as indicating or implying relative importance. Further, in the description of the present invention, the meaning of "a plurality" means at least two unless otherwise specified.

Any process or method descriptions in flow charts or otherwise described herein may be understood as representing modules, segments, or portions of code which include one or more executable instructions for implementing specific logical functions or steps of the process, and alternate implementations are included within the scope of the preferred embodiment of the present invention in which functions may be executed out of order from that shown or discussed, including substantially concurrently or in reverse order, depending on the functionality involved, as would be understood by those reasonably skilled in the art of the present invention.

It should be understood that portions of the present invention may be implemented in hardware, software, firmware, or a combination thereof. In the above embodiments, the various steps or methods may be implemented in software or firmware stored in memory and executed by a suitable instruction execution system. For example, if implemented in hardware, as in another embodiment, any one or combination of the following techniques, which are known in the art, may be used: a discrete logic circuit having a logic gate circuit for implementing a logic function on a data signal, an application specific integrated circuit having an appropriate combinational logic gate circuit, a Programmable Gate Array (PGA), a Field Programmable Gate Array (FPGA), or the like.

It will be understood by those skilled in the art that all or part of the steps carried by the method for implementing the above embodiments may be implemented by hardware related to instructions of a program, which may be stored in a computer readable storage medium, and when the program is executed, the program includes one or a combination of the steps of the method embodiments.

In addition, functional units in the embodiments of the present invention may be integrated into one processing module, or each unit may exist alone physically, or two or more units are integrated into one module. The integrated module can be realized in a hardware mode, and can also be realized in a software functional module mode. The integrated module, if implemented in the form of a software functional module and sold or used as a stand-alone product, may also be stored in a computer readable storage medium.

The storage medium mentioned above may be a read-only memory, a magnetic or optical disk, etc.

In the description of the specification, reference to the description of "one embodiment," "some embodiments," "an example," "a specific example," or "some examples" or the like means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

Although embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention, and that variations, modifications, substitutions and alterations can be made to the above embodiments by those of ordinary skill in the art within the scope of the present invention.

Claims

1. A radio frequency power signal acquisition method is characterized by comprising the following steps:

2. The method according to claim 1, wherein the setting of the data bit corresponding to the rising edge interval and the falling edge interval in the sampling array to 0, the signal low bit or the null signal is: and setting data bits corresponding to the rising edge interval and the falling edge interval in the sampling array as 0, signal low-order bits or null signals in a sampling delay or sampling data output 0 mode.

3. The method of claim 2, wherein the setting the data bits corresponding to the rising edge interval and the falling edge interval in the sampling array to 0, signal low or null by sampling delay or sampling data output to 0 comprises:

in a rising edge interval, setting a data bit corresponding to the rising edge interval in a sampling array as 0, a signal low bit or a null signal by delaying sampling time during data sampling, or setting the data bit corresponding to the rising edge interval in the sampling array as 0, a signal low bit or a null signal during sampling data output;

in the falling edge interval, during data sampling, setting the data bit corresponding to the falling edge interval in the sampling array as 0, signal low bit or null signal through delaying sampling time, or, during sampling data output, setting the falling edge interval in the sampling array or the data bit corresponding to the falling edge interval as 0, signal low bit or null signal.

4. The method of claim 3, wherein the setting the data bit corresponding to the rising edge interval in the sampling array to 0, a signal low bit or a null signal by delaying the sampling time comprises: starting from a rising edge starting point in a current pulse period, starting a first sampling delay, and setting a data bit corresponding to the first sampling delay in a sampling array as 0, a signal low bit or a null signal;

the setting the data bit corresponding to the falling edge interval in the sampling array to 0, the signal low bit or the null signal by delaying the sampling time comprises: starting from the starting point of the falling edge in the current pulse period, starting second sampling delay, and setting the data bit corresponding to the second sampling delay in the sampling array as 0, a signal low bit or a null signal.

5. The method of claim 3, wherein the setting the data bit corresponding to the rising edge interval in the sample array to 0, a signal low bit, or a null signal comprises: when signal sampling of a rising edge end point in a current pulse period is finished, determining first abnormal data, wherein the first abnormal data is data in a sampling array, which starts from a data bit corresponding to the rising edge end point and counts forwards within a first preset length, the first abnormal data is set to be 0, a signal is low or a null signal, and the first preset length is the array length corresponding to a rising edge interval;

6. The method according to claim 4, wherein the setting of the data bit corresponding to the first sampling delay in the sampling array to 0, the signal low bit or the null signal is: setting a data bit corresponding to a first preset sampling duration in the sampling array as 0, and ending the time delay when the signal is low or null;

setting the data bit corresponding to the second sampling delay in the sampling array to be 0, and setting the signal low bit or the null signal as follows: and setting the data bit corresponding to the second preset sampling time length in the sampling array as 0, and ending the time delay when the signal is low or null.

7. The method according to claim 4, wherein the setting of the data bit corresponding to the first sampling delay in the sampling array to 0, the signal low bit or the null signal is: setting a data bit corresponding to the length of a first preset array in the sampling array as 0, and ending the time delay when the signal is low or empty;

setting the data bit corresponding to the second sampling delay in the sampling array to be 0, and setting the signal low bit or the null signal as follows: and setting the data bit corresponding to the second preset array length in the sampling array as 0, and setting the signal low bit or the null signal, and finishing the time delay.

8. The method of claim 4, wherein the determining the rising edge interval and the falling edge interval in the current pulse period comprises:

9. The method of claim 6, wherein the first predetermined sampling duration is equal to a rising edge duration and the second predetermined sampling duration is equal to a falling edge duration.

10. The method of claim 7, wherein the first predetermined array length and the second predetermined array length are determined by a predetermined operational relationship between the rising edge duration or the falling edge duration and a sampling period.

11. The method of claim 10, wherein the first preset array length = rising edge duration/sampling period, and the second preset array length = falling edge duration/sampling period; or the first preset array length = the second preset array length = rising edge duration/sampling period; or, the first preset array length = the second preset array length = falling edge duration/sampling period.

12. The method according to claim 8, wherein the determining the rising edge interval and the falling edge interval in the current pulse period according to the power variation of the sampling points comprises:

acquiring a rising edge starting point, wherein the rising edge starting point is a sampling point of which the power is greater than a rising edge reference threshold value for the first time in the current pulse period;

and acquiring a falling edge starting point, wherein the falling edge starting point is a sampling point of which the power is smaller than a falling edge reference threshold value for the first time in the current pulse period.

13. The radio frequency power supply signal acquisition method of any one of claims 1-12, further comprising: and reading and sequentially outputting sampling data by the sampling array outside the rising edge interval and the falling edge interval.

14. The method of claim 11, wherein if the first preset array length = the second preset array length = rising edge duration/sampling period, and the rising edge duration is greater than the falling edge duration, the setting the data bits corresponding to the rising edge interval and the falling edge interval in the sampling array to 0, signal low or null signal by sampling delay or sampling data output of 0 comprises:

when sampling data is output, when signal sampling is finished on a falling edge end point in a current pulse period, calculating the duration of a third delay, wherein the third delay duration is the difference value between the rising edge duration and the falling edge duration, starting the third delay, when the third delay is finished, determining third different constant data, wherein the third different constant data is data in a third preset length counted from a data bit corresponding to the third delay end point in the sampling array, setting the third different constant data to be 0, a signal low bit or an empty signal, and the third preset length is the array length corresponding to the falling edge interval.

15. A radio frequency power signal acquisition device, comprising:

and the sampling data setting 0 module is used for setting data bits corresponding to the rising edge interval and the falling edge interval in a sampling array to be 0, a signal low bit or a null signal.

16. A computer device, comprising: a processor, a memory and a bus, the memory storing machine readable instructions executable by the processor, the processor and the memory communicating via the bus when a computer device is running, the machine readable instructions when executed by the processor performing the radio frequency power signal acquisition method of any one of claims 1 to 14.

17. A computer-readable storage medium, having a computer program stored thereon, the computer program being executed by a processor to perform the radio frequency power signal acquisition method according to any one of claims 1 to 14.