TW202407355A - Radio frequency power supply signal acquisition method and device - Google Patents

Abstract

The invention provides a radio frequency power supply signal acquisition method and device, and the method comprises the steps: determining a rising edge interval and a falling edge interval in a current pulse period; data bits corresponding to a rising edge interval and a falling edge interval in a sampling array are set to be 0, signal low bits or null signals, and the problem that in the prior art, due to the fact that an acquisition board continuously acquires voltage and current signals and continuously outputs the signals, even in a startup and shutdown mode and a PULSE mode, the sampling efficiency is low is solved. And signals are still continuously collected and output in a slope generation stage, so that the problem of inaccurate output data is caused.

Description

A radio frequency power signal acquisition method and device (1)

The invention relates to the technical field of radio frequency power signal acquisition, and in particular to a radio frequency power signal acquisition method and device.

A typical data acquisition system collects signals from the surrounding environment or various objects under test through various sensors. Generally speaking, these signals are generated randomly, so the data acquisition system must continuously sample to ensure that no important signals are missed. In radio frequency power supplies, the current acquisition board collects voltage and current signals through continuous sampling. In the existing technology, the acquisition board continuously collects voltage and current signals and outputs signals continuously, even when turning on and off and pulse (PULSE). In mode, signals are still continuously collected and output during the ramp generation stage, resulting in inaccurate output data.

Therefore, the technical problem to be solved by the present invention is to overcome the existing radio frequency power supply technology. Since the acquisition board continuously collects voltage and current signals and continuously outputs signals, even in the on/off and pulse (PULSE) modes, during the ramp generation stage The signal is still continuously collected and output, resulting in the problem of inaccurate output data, thereby providing a radio frequency power signal collection method and device.

In order to solve the above technical problems, disclosed embodiments of the present invention provide at least one radio frequency power signal acquisition method and device.

In a first aspect, disclosed embodiments of the present invention provide a method for collecting radio frequency power signals, which includes: determining the rising edge interval and the falling edge interval within the current pulse period; and comparing the sampling array with the rising edge interval and the falling edge interval. The corresponding data bit is set to 0, signal low, or null signal.

Optionally, setting the data bits corresponding to the rising edge interval and the falling edge interval in the sampling array to 0, low signal bits or empty signals is: setting the sampling delay or sampling data output to 0. The data bits in the array corresponding to the rising edge interval and the falling edge interval are set to 0, low signal, or empty signal.

Optionally, setting the data bits in the sampling array corresponding to the rising edge interval and the falling edge interval to 0, a low signal or a null signal in the sampling array by sampling delay or setting the sampling data output to 0 includes: In the edge interval, when data is sampled, the data bit corresponding to the rising edge interval in the sampling array is set to 0, low signal or empty signal by delaying the sampling time, or, when the sampling data is output, the data bit in the sampling array is set to The data bits corresponding to the rising edge interval are set to 0, low signal or empty signal; in the falling edge interval, when data is sampled, the data bits corresponding to the falling edge interval in the sampling array are set to 0, signal by delaying the sampling time. Low bit or empty signal, or, when the sampled data is output, the falling edge interval or the data bit corresponding to the falling edge interval in the sampling array is set to 0, signal low bit or empty signal.

Optionally, setting the data bit corresponding to the rising edge interval in the sampling array to 0, low signal or empty signal by delaying the sampling time includes: starting from the starting point of the rising edge in the current pulse period, starting the first sampling Delay, set the data bit corresponding to the first sampling delay in the sampling array to 0, low signal or empty signal; set the data bit corresponding to the falling edge interval in the sampling array to 0, signal by delaying the sampling time The low or empty signal includes: starting from the starting point of the falling edge in the current pulse cycle, starting the second sampling delay, setting the data bit corresponding to the second sampling delay in the sampling array to 0, signal low or empty signal.

Optionally, setting the data bit corresponding to the rising edge interval in the sampling array to 0, a low signal, or a null signal includes: while completing signal sampling of the rising edge end point in the current pulse cycle, determining the first An abnormal data, the first abnormal data is the data within the first preset length starting from the data bit corresponding to the rising edge end point in the sampling array, and counting forward The first abnormal data is set to 0, the signal is low or the signal is empty, the first preset length is the array length corresponding to the rising edge interval; the data bit corresponding to the falling edge interval in the sampling array is set to 0, The signal low or empty signal includes: while completing the signal sampling of the falling edge end point in the current pulse cycle, determining the second abnormal data, the second abnormal data is within the sampling array and ends from the falling edge. Starting from the data bit corresponding to the point, count the data within the second preset length forward, and set the second abnormal data to 0, signal low or empty signal, and the second preset length is the corresponding falling edge interval. Array length.

Optionally, the step of setting the data bit corresponding to the first sampling delay in the sampling array to 0 and the low signal or empty signal is: setting the data bit corresponding to the first preset sampling duration in the sampling array to 0, The signal is low or empty, and the delay ends; the data bit corresponding to the second sampling delay in the sampling array is set to 0, the signal is low or the empty signal is: the data corresponding to the second preset sampling duration in the sampling array is set The bit is set to 0, the signal is low or the signal is empty, and the delay ends.

Optionally, the step of setting the data bit corresponding to the first sampling delay in the sampling array to 0 and the signal low bit or the empty signal is: setting the data bit corresponding to the first preset array length in the sampling array to 0, signaling Low or empty signal, the delay ends; setting the data bit corresponding to the second sampling delay in the sampling array to 0, signal low or empty signal is: setting the data bit corresponding to the second preset array length in the sampling array If it is 0, the signal is low or empty, the delay ends.

Optionally, determining the rising edge interval and falling edge interval in the current pulse period includes: determining the rising edge interval and falling edge interval in the current pulse period through a reference threshold, rising edge duration and falling edge duration, said The reference threshold is used to mark the low level of the signal; or, the rising edge interval and the falling edge interval in the current pulse cycle are determined through the base threshold and the top threshold, and the top threshold is used to mark the high level of the signal; or, the power change of the sampling point is used Determine the rising edge interval and falling edge interval within the current pulse cycle.

Optionally, the first preset sampling duration is equal to the rising edge duration, and the second preset sampling duration is equal to the falling edge duration.

Optionally, the first preset array length and the second preset array length are determined according to a preset operation relationship between the rising edge duration or the falling edge duration and the sampling period.

Optionally, the first preset array length = rising edge duration/sampling period, the second preset array length = falling edge duration/sampling period; or, the first preset array length = the third Two preset array length = rising edge duration/sampling period; or, the first preset array length = the second preset array length = falling edge duration/sampling period.

Optionally, determining the rising edge interval and falling edge interval in the current pulse period through the power change of the sampling point includes: obtaining the rising edge starting point, the rising edge starting point is the first power in the current pulse period. The sampling point that is greater than the rising edge reference threshold for the first time; obtain the falling edge starting point, which is the sampling point where the power is less than the falling edge reference threshold for the first time in the current pulse period.

Optionally, the above method further includes: outside the rising edge interval and the falling edge interval, the sampling array reads and outputs sampled data in sequence.

Optionally, if the first preset array length = the second preset array length = rising edge duration/sampling period, and the rising edge duration is longer than the falling edge duration, then the sampling delay or sampling period The method of setting the data output to 0 sets the data bits corresponding to the rising edge interval and the falling edge interval in the sampling array to 0, low signal or empty signal including: when the sampling data is output, after completing the current pulse period While sampling the signal at the falling edge end point, calculate the third delay duration. The third delay duration is the difference between the rising edge duration and the falling edge duration. The third delay is started. When the third delay ends, third abnormal data is determined. The third abnormal data is within the third preset length in the sampling array starting from the data bit corresponding to the third delay end point and counting forward. data, the third abnormal data is set to 0, the signal is low, or the signal is empty, and the third preset length is the array length corresponding to the falling edge interval.

In a second aspect, disclosed embodiments of the present invention also provide a radio frequency power signal acquisition device, including: an abnormal data interval determination module, used to determine the rising edge interval and falling edge interval within the current pulse cycle; a sampling data setting module of 0, Used to set the data bits in the sampling array corresponding to the rising edge interval and the falling edge interval to 0, a low signal, or a null signal.

In a third aspect, disclosed embodiments of the present invention also provide a computer device, including: a processor, a memory, and a bus. The memory stores machine-readable instructions executable by the processor. When the computer device is running, the The processor communicates with the memory through a bus, and when the machine-readable instructions are executed by the processor, the steps in the above-mentioned first aspect, or any possible implementation manner of the first aspect, are performed.

In a fourth aspect, the disclosed embodiments of the present invention also provide a computer-readable storage medium. The computer-readable storage medium stores a computer program. When the computer program is run by a processor, it executes the above-mentioned first aspect, or any of the first aspects. steps in a possible implementation.

The technical solution provided by the embodiments of the present invention can have the following beneficial effects:

Determine the rising edge interval and falling edge interval in the current pulse period, set the data bits corresponding to the rising edge interval and falling edge interval in the sampling array to 0, low signal or empty signal, use FIFO (First Input First Output, first in first Out) sampling array is set to 0 to mask out the data in the abnormal segment, that is, to output 0 in the ramp segment data in the on/off and pulse (PULSE) modes, and only output power in the correct time period other than the slope.

It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and do not limit the present invention.

S11, S12, S13; S21, S22, S221, S222, S23: steps

1: memory

2: Processor

71: Abnormal data interval determination module

711: Rising edge starting point acquisition sub-module

712: Falling edge starting point acquisition sub-module

72:Sampling data is set to 0 module

721: Rising edge exception handling sub-module

722: Falling edge exception handling sub-module

73:FIFO array output module

In order to more clearly explain the specific embodiments of the present invention or the technical solutions in the prior art, the drawings that need to be used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings in the following description are: Some embodiments of the present invention are common in the art For ordinary technicians, other drawings can also be obtained based on these drawings without exerting creative work.

Figure 1 shows a flow chart of a radio frequency power signal acquisition method provided by a disclosed embodiment of the present invention.

Figure 2 shows a flow chart of another radio frequency power signal acquisition method provided by the disclosed embodiment of the present invention.

Figure 3 shows a schematic diagram of the pulse structure in the disclosed embodiment of the present invention.

FIG. 4 shows a schematic diagram of the pulse structure of Example 1 in the disclosed embodiment of the present invention.

Figure 5 shows a schematic diagram of the pulse structure of Example 2 in the disclosed embodiment of the present invention.

Figure 6 shows a schematic diagram of the pulse structure of Example 3 in the disclosed embodiment of the present invention;

Figure 7 shows a schematic structural diagram of a radio frequency power signal acquisition device provided by a disclosed embodiment of the present invention;

Figure 8 shows a schematic structural diagram of a computer device provided by a disclosed embodiment of the present invention.

Exemplary embodiments will be described in detail herein, examples of which are illustrated in the accompanying drawings. When the following description refers to the drawings, the same numbers in different drawings refer to the same or similar elements unless otherwise indicated. The implementations described in the following exemplary embodiments do not represent all implementations consistent with the invention. Rather, they are merely examples of apparatus and methods consistent with aspects of the invention as detailed in the appended claims.

Example 1:

As shown in Figure 1, there is a flow chart of a radio frequency power signal acquisition method provided by an embodiment disclosed in the present invention. The method includes:

Step S11: Determine the rising edge interval and falling edge interval within the current pulse cycle;

Step S12: Set the data bits corresponding to the rising edge interval and the falling edge interval in the sampling array to 0, low signal, or empty signal;

Step S13: Outside the rising edge interval and falling edge interval, the sampling array reads and outputs the sampling data in sequence.

It can be understood that the technical solution provided by this embodiment determines the rising edge interval and falling edge interval within the current pulse cycle, and sets the data bits corresponding to the rising edge interval and falling edge interval in the sampling array to 0, signal low bit, or For an empty signal, use the FIFO (First Input First Output, first in first out) sampling array to set it to 0 to mask out the data in the abnormal section, that is, to make the data in the slope section output 0 in the power on and off and pulse (PULSE) modes, only in Output power at the correct time period outside of the ramp.

Example 2:

As shown in Figure 2, there is a flow chart of another radio frequency power signal acquisition method provided by the disclosed embodiment of the present invention. See Figure 3. This method masks abnormal data generated during the ramp phase within the pulse cycle. The method includes:

Step S21: Determine the rising edge interval and falling edge interval within the current pulse cycle;

Step S22: Set the data bits corresponding to the rising edge interval and the falling edge interval in the sampling array to 0, low signal, or empty signal;

Step S23: Outside the rising edge interval and falling edge interval, the sampling array reads and outputs the sampled data in sequence.

In some embodiments, step S22 sets the data bits corresponding to the rising edge interval and the falling edge interval in the sampling array to 0, and the signal low bit or empty signal can be: setting the sampling array to 0 through sampling delay or sampling data output. The data bits corresponding to the rising edge interval and falling edge interval are set to 0, low signal or empty signal.

In some embodiments, step S22 may include the following steps:

Step S221: In the rising edge interval, different data processing methods can be adopted according to different data determination modes. Data judgment modes include:

(A) Use the reference threshold to determine whether the input signal changes from the low signal level to the rising edge interval, that is, when the signal data is lower than the reference threshold, it is regarded as the signal low level (or signal zero output, or 0 output), When the signal data is higher than the reference threshold, it is regarded as the signal climbing to a high level, and the climbing process is regarded as the rising edge interval.

When reading sampling data, once the sampling data read and scheduled to be imported into the sampling array exceeds the reference threshold, the signal is considered to enter a rising edge, and the sampling delay is started at this time. When the sampling delay ends, the normal reading operation of sampling data is resumed. In some embodiments, the length of the sampling delay is the length of the rising edge interval. Among them, according to the length of the corresponding acquisition array, the corresponding data processing method is adopted, which is explained as follows:

(A-1) When the duration corresponding to the data bits of the acquisition array is greater than or equal to the duration of the rising edge interval, choose one of the following methods to process:

(A-11) During the sampling delay period, the sampled data read is first set to 0, low signal or empty signal, and then filled in the sampling array.

(A-12) Mark the sampled data read during the sampling delay period and imported into the sampling array. When the sampling data is output, the data bit corresponding to the rising edge interval in the sampling array is set to 0, low signal or empty signal.

(A-13) During the period of starting the delayed sampling time, no matter what kind of sample data is read, the data of the entire sampling array still maintains FIFO operation. When the delayed sampling time ends, all data fields in the sampling array are set to 0, The signal is low or empty, and normal data sampling operations are performed at the same time.

(A-2) When the duration corresponding to the data bits of the acquisition array is less than the duration of the rising edge interval, process the read data through (A-11) or (A-12).

(B) Use the reference threshold to determine whether the input signal changes from the low signal level to the rising edge interval, and use the top threshold to determine whether the input signal changes from the rising edge interval to the signal high level.

When reading sampling data, once the sampling data read and scheduled to be imported into the sampling array exceeds the reference threshold, the signal is considered to enter a rising edge, and the sampling delay is started at this time. When the sample data read and scheduled to be imported into the sampling array exceeds the top threshold, the signal is considered to enter the signal high position from the rising edge. At this time, the sampling delay ends, and normal operations of reading sampled data and filling in the sampled array resume.

In some embodiments, when the duration of the rising edge interval is known, the corresponding data processing method is adopted according to the length of the corresponding collection array as described above (A-1) and (A-2).

In some embodiments, the length of the sampling delay depends on the length of time the read sample value is between the base threshold and the top threshold, that is, based on the actual length of the rising edge interval. That is to say, the low level, rising edge and high level of the signal are determined only by the reference threshold and the top threshold. The data processing methods are as described above (A-1) and (A-2).

(C) Compare the sample values read before and after, and determine whether the input signal changes from the low signal level to the rising edge interval, and whether it changes from the rising edge interval to the signal high level based on the change in data size.

When reading sampling data, once multiple consecutive sampling data that are scheduled to be imported into the sampling array are read and change from constant low-bit data to rising data (the previous data read is lower than the subsequent data), the signal is considered to enter the rising edge. , start the sampling delay at this time. When multiple consecutive sampled data that are read and scheduled to be imported into the sampling array change from rising data to constant high-bit data (the pre-read data is equal to the post-data), it is considered that the signal enters the signal high-bit from the rising edge, and sampling ends at this time Delay and resume normal sampling data reading and filling in sampling array operations.

In some embodiments, when the duration of the rising edge interval is known, the corresponding data processing method is adopted according to the length of the corresponding acquisition array as described above (A-1) and (A-2).

In some embodiments, the length of the sampling delay depends on the length of time the read sample value is between the base threshold and the top threshold, that is, based on the actual length of the rising edge interval. That is to say, the length of the rising edge interval can be ignored, and the low level, rising edge and high level of the signal can be determined through the conversion of constant data and rising data. The data processing methods are as described above (A-11) and (A-12).

Step S222: In the falling edge interval, different data processing methods can be adopted according to different data determination modes. Data judgment modes include:

(D) Use the reference threshold to determine whether the input signal has reached the falling edge interval and turned to the signal low position, that is, the signal has reached the end of the falling edge interval, and further can be regarded as entering the signal low position, zero position or no output.

When reading sampling data, once the sampling data read and scheduled to be imported into the sampling array is lower than the reference threshold, it is considered that the signal has passed the end of the falling edge, or even reached the low position, zero position or no output of the signal. At this time, the sampling delay is started. . When the sampling delay ends, the normal reading operation of sampling data is resumed.

In some embodiments, the duration of the sampling delay is the sum of the data sampling durations corresponding to the data bits of the collection array - the falling edge duration. Among them, the sum of the data sampling duration corresponding to the data bits of the collection array is not less than the falling edge duration. According to the length of the corresponding acquisition array, the delay processing method is as follows:

(D-1) The sum of the data sampling durations corresponding to the data bits of the collection array is equal to the falling edge duration, and the sampling delay duration is 0, which means that the sampling delay is not enabled and subsequent data processing is performed directly.

(D-2) The sum of the data sampling duration corresponding to the data bits of the acquisition array is greater than the falling edge duration. The duration of the sampling delay is the difference between the two. After the delay is over, subsequent data processing is performed.

In some embodiments, if the delayed sampling period (D-2 above) is started, no matter what kind of sample data is read, the data of the entire sampling array still maintains FIFO operation. When the sampling delay time expires, Beam (or disable the sampling delay of D-1 above), set all data fields in the sampling array to 0, low signal or empty signal, and perform normal data sampling operations at the same time.

(E) Use the top threshold to determine whether the input signal changes from a high signal level to a falling edge interval, that is, when the signal data is higher than the top threshold, the signal is deemed to be high, and when the signal data is lower than the top threshold, the signal is deemed to be falling to a low level. , the falling process is regarded as the falling edge interval.

When reading sampling data, once the sampling data that is read and scheduled to be imported into the sampling array is lower than the top threshold, the signal is considered to have entered a falling edge, and the sampling delay is started at this time. When the sampling delay ends, the normal reading operation of sampling data is resumed.

In some embodiments, the length of the sampling delay is the sum of the length of the falling edge interval and the length of data sampling corresponding to the data bits of the collection array, whichever is longer; if they are the same, choose either one. . Therefore, after the delay is over, the acquired data read will fall to the low level of the signal.

Among them, according to the length of the corresponding collection array, the corresponding data processing method is adopted, which is explained as follows:

(E-1) When the duration corresponding to the data bits of the acquisition array is greater than or equal to the duration of the falling edge interval, choose one of the following methods to process:

(E-11) During the sampling delay period, the sampled data read is first set to 0, low signal or empty signal, and then filled in the sampling array.

(E-12) Mark the sampled data read during the sampling delay period and imported into the sampling array. When the sampling array is output, the data bit corresponding to the falling edge interval in the sampling array is set to 0, low signal or empty signal.

(E-13) During the period of starting the delayed sampling time, no matter what kind of sampling data is read, the data of the entire sampling array still maintains FIFO operation. When the delayed sampling time ends, all data fields in the sampling array are set to 0, The signal is low or empty, and normal data sampling operations are performed at the same time.

(E-2) When the duration corresponding to the data bits of the collection array is less than the duration of the falling edge interval, process the read data through (E-11) or (E-12).

(F) Use the top threshold to determine whether the input signal changes from the high signal level to the falling edge interval, and use the reference threshold to determine whether the input signal changes from the falling edge interval to the signal low level.

When reading sampling data, once the sampling data that is read and scheduled to be imported into the sampling array is lower than the top threshold, the signal is considered to have entered a falling edge, and the sampling delay is started at this time. When the sampled data read and scheduled to be imported into the sampling array is lower than the reference threshold, the signal is considered to enter the signal low position from the falling edge. At this time, the sampling delay ends, and normal operations of reading sampled data and filling in the sampled array resume.

In some embodiments, the length of the sampling delay depends on the length of time the read sample value is between the base threshold and the top threshold, that is, based on the actual length of the falling edge interval. That is to say, the high level, falling edge and low level of the signal are determined only by the reference threshold and the top threshold value. The data processing methods are as described above (E-1) and (E-2).

(G) Compare the sample values read before and after, and determine whether the input signal changes from the high signal level to the falling edge interval, and whether it changes from the falling edge interval to the signal low level based on the change in data size.

When reading sampling data, once multiple consecutive sampling data that are scheduled to be imported into the sampling array are read and change from constant high data to rising data (the previous data read is lower than the latter data), the signal is considered to enter the falling edge. , start the sampling delay at this time. When multiple consecutive sampled data that are read and scheduled to be imported into the sampling array change from falling data to constant low-bit data (the pre-read data is equal to the post-data), it is considered that the signal enters the low level of the signal from the falling edge, and it ends at this time Sampling delay, resume normal sampling data reading and filling sampling array operations.

In some embodiments, when the length of the falling edge interval is known, the corresponding data processing method is adopted according to the length of the corresponding collection array as in (E-1) and (E-2) above.

In some embodiments, the length of the sampling delay depends on the length of time the read sample value is between the base threshold and the top threshold, that is, based on the actual length of the rising edge interval. That is to say, the duration of the rising edge interval can be ignored, and the low level, rising edge and high level of the signal can be determined through the conversion of constant data and rising data. The data processing methods are as described in (E-11) and (E-12) above.

In some embodiments, step S22 includes: when sampling data, setting the data bit corresponding to the falling edge interval in the sampling array to 0, a low signal or a null signal by delaying the sampling time, or, when outputting the sampling data, setting the sampling The data bit corresponding to the falling edge interval or falling edge interval in the array is set to 0, low signal or empty signal.

In some embodiments, step S221 may include: starting from the starting point of the rising edge in the current pulse cycle, starting the first sampling delay, and setting the data bit corresponding to the first sampling delay in the sampling array to 0, low signal, or empty signal. ;

The above-mentioned setting of the data bit corresponding to the falling edge interval in the sampling array to 0, the signal low bit or the empty signal by delaying the sampling time may include: starting from the starting point of the falling edge in the current pulse period, starting the second sampling delay, changing the sampling array The data bit corresponding to the second sampling delay is set to 0, low signal or empty signal.

In some embodiments, especially in some cases where the rising edge power reference threshold cannot be obtained, step S222 may include: determining the first abnormal data while completing signal sampling of the rising edge end point in the current pulse cycle, The first abnormal data is in the sampling array, starting from the data bit corresponding to the rising edge end point, counting forward the data within the first preset length, setting the first abnormal data to 0, low signal or empty signal, the first preset The length is the array length corresponding to the rising edge interval.

Among them, the data bit corresponding to the falling edge interval in the sampling array is set to 0. The signal low or empty signal can be realized through the following process: while completing the signal sampling of the falling edge end point in the current pulse cycle, determine the second abnormal data. The second abnormal data is within the sampling array and corresponds to the falling edge end point. Starting from the data bit, count forward the data within the second preset length, and add the second The abnormal data is set to 0, the signal is low or the signal is empty, and the second preset length is the array length corresponding to the falling edge interval.

In some embodiments, the above-mentioned setting of the data bit corresponding to the first sampling delay in the sampling array to 0, the signal low bit or the empty signal may be: setting the data bit corresponding to the first preset sampling duration in the sampling array to 0, The signal is low or empty, and the delay ends; the above-mentioned setting of the data bit corresponding to the second sampling delay in the sampling array to 0, the signal low or empty signal can be: setting the data bit corresponding to the second preset sampling duration in the sampling array If it is 0, the signal is low or empty, the delay ends.

In some embodiments, the above-mentioned setting of the data bit corresponding to the first sampling delay in the sampling array to 0 and the signal low bit or empty signal may be: setting the data bit corresponding to the first preset array length in the sampling array to 0, signaling Low or empty signal, the delay ends; the above is to set the data bit corresponding to the second sampling delay in the sampling array to 0. The signal low or empty signal can be: set the data bit corresponding to the second preset array length in the sampling array to 0 , low signal or empty signal, the delay ends.

In some embodiments, step S21 may include:

a. Determine the rising edge interval and falling edge interval in the current pulse cycle through the reference threshold, rising edge duration and falling edge duration. The reference threshold is used to mark the low level of the signal; or,

b. Determine the rising edge interval and falling edge interval within the current pulse cycle through the base threshold and the top threshold. The top threshold is used to mark the high level of the signal; or,

c. Determine the rising edge interval and falling edge interval within the current pulse period through the power change of the sampling point.

In some embodiments, the specific performance is to perform detection sampling, using the sampling period as the base, starting when the power rises beyond the rising threshold, and ending when the power reaches the falling threshold, calculating the number of samples or sampling timing, and obtaining Rising edge interval; on the contrary, it starts when the power drops beyond the falling threshold and ends when the power reaches the rising threshold. Calculate the number of samples or sampling timing to obtain the falling edge interval.

In some embodiments, the first sampling delay duration is equal to the rising edge duration, and the second sampling delay duration is equal to the falling edge duration.

In some embodiments, the first preset array length≧falling edge duration/sampling period, and the second preset array length≧falling edge duration/sampling period.

In some embodiments, the first preset array length and the second preset array length are determined according to a preset operation relationship between the rising edge duration or the falling edge duration and the sampling period.

In a specific embodiment, the first preset array length = rising edge duration/sampling period, the second preset array length = falling edge duration/sampling period; or, the first preset array length = the second preset Array length = rising edge duration/sampling period; or, first preset array length = second preset array length = falling edge duration/sampling period.

In some embodiments, if the first preset array length = the second preset array length = rising edge duration/sampling period, and the rising edge duration is greater than the falling edge duration, then the sampling delay or sampling data output is set to 0. The method of setting the data bits corresponding to the rising edge interval and falling edge interval in the sampling array to 0, low signal or empty signal includes:

When the sampling data is output, the third delay duration is calculated while completing the signal sampling of the falling edge end point in the current pulse cycle. The third delay duration is the difference between the rising edge duration and the falling edge duration. Start the third delay, and at the end of the third delay, determine the third abnormal data. The third abnormal data is the data within the third preset length in the sampling array starting from the data bit corresponding to the third delay end point and counting forward. , set the third abnormal data to 0, low signal or empty signal, and the third preset length is the array length corresponding to the falling edge interval.

In some embodiments, step S21 may include: obtaining the rising edge starting point, which is the sampling point where the power is greater than the reference threshold for the first time in the current pulse period; obtaining the rising edge end point, which is the sampling point where the power is greater than the reference threshold for the first time in the current pulse period; It is the sampling point where the power is greater than the top threshold for the first time in the current pulse period; obtain the starting point of the falling edge, which is the first time when the power is less than the falling edge in the current pulse period. The sampling point of the base threshold; obtain the falling edge end point, which is the sampling point where the power is less than the base threshold for the first time in the current pulse cycle.

In order to facilitate readers' understanding, the above-mentioned RF power signal acquisition method is explained below through a specific example. First, assume that the rising edge duration is 10μs (T1) and the falling edge duration is 4μs (T2). Set the sampling array length to 5 and the period to 1μs:

Example 1 (known baseline threshold), as shown in Figure 7 and Figure 4:

In the rising edge interval, the reference threshold is used to determine whether the input signal changes from the low signal level to the rising edge interval. Once the sampling data that is read and scheduled to be imported into the sampling array exceeds the reference threshold, the signal is considered to have entered the rising edge, and sampling is started at this time. Delay. When the first digit of the FIFO array reaches point A on the rising edge, and the power (Pa) of the next acquisition point exceeds the reference threshold, the 10μs delay T1 is started at this time, and each data in the FIFO array is limited to 0 at this time. When the first digit of the FIFO array reaches point B on the rising edge, the sampling delay ends at this time, and the first digit of the FIFO array begins to fill in data until the C position is initially filled with the entire FIFO array. Then according to the FIFO theory, the data is first in, first out. When the FIFO array The data output before reaching the C position is still 0, and the initially input point B data is not output until point C. The output data is normal output until it reaches point E.

In the falling edge interval, the reference threshold is used to determine whether the input signal has reached the falling edge interval and turned to the low level of the signal. When reading the sampling data, once the sampled data that is read and scheduled to be imported into the sampling array is lower than the reference threshold, it is considered When the signal passes the end of the falling edge, or even reaches the low level, zero level or no output of the signal, the sampling delay is started at this time. In the falling edge stage, when the first digit of the FIFO array reaches point F on the falling edge, the power (Pb) of the collection point will be lower than the reference threshold, and the actual output is point D data. At this time, the start delay T2=5us-4us=1us, the delay At the end, the first digit of the FIFO array reaches point G, the last digit reaches point E, and the FIFO array clears the data to 0 and outputs it.

Example 2 (known base threshold and top threshold), as shown in Figure 7 and Figure 5:

In the rising edge interval, the reference threshold is used to determine whether the input signal changes from a low signal level to a rising edge interval, and the top threshold is used to determine whether the input signal changes from a rising edge interval to a signal high level. In the rising edge stage, when the first digit of the FIFO array reaches point A on the rising edge, and the power (Pa) of the next acquisition point is higher than the reference threshold, the sampling delay is started at this time. When the first digit of the FIFO array reaches point B on the rising edge, and the power (Pa) of the next acquisition point is higher than the top threshold, the sampling delay ends at this time. The first digit of the FIFO array begins to fill in data, and the entire FIFO array is initially filled until the C position. Then according to the FIFO theory, the data is first in, first out. When the FIFO array reaches the C position, the output data is still 0, and the initial output is not until point C. The input data at point B and the output data until reaching point E are normal outputs.

In the falling edge interval, the top threshold is used to determine whether the input signal changes from the high signal level to the falling edge interval, and the reference threshold is used to determine whether the input signal changes from the falling edge interval to the signal low level. The data bits corresponding to the falling edge interval in the sampling array are Set to 0, low signal or empty signal, the data processing method is as above (E-1). When the first digit of the FIFO array reaches point E on the falling edge, the power (Pb) of the collection point will be lower than the top threshold, and the sampling delay is started at this time; when the first digit of the FIFO array reaches point F on the falling edge, the power (Pb) of the collection point will be lower than the baseline threshold. At this time, the sampling delay ends and normal sampling data reading and filling in the sampling array operations resume.

Example 3, as shown in Figure 6:

In the rising edge interval, compare the sample values read before and after, and determine whether the input signal changes from the low signal level to the rising edge interval, and whether it changes from the rising edge interval to the signal high level based on the change in data size. Specifically, you can use the sampling point The power change determines the rising edge interval in the current pulse cycle, and sets the data bit corresponding to the falling edge interval in the sampling array to 0, low signal, or empty signal. The data processing method is as described above (A-1) or (A-1).

When reading sampling data, once multiple consecutive sampling data that are scheduled to be imported into the sampling array are read and change from constant low-bit data to rising data (the previous data read is lower than the subsequent data), the signal is considered to enter the rising edge. , start the sampling delay at this time. When the sample array is read and scheduled to be imported, When multiple consecutive sampling data change from rising data to constant high-bit data (the read previous data is equal to the last data), it is considered that the signal enters the signal high-bit from the rising edge. At this time, the sampling delay ends and normal sampling data reading and return are resumed. Fill in the sample array job.

The low-power data collected from the beginning to point A is accurate; point A to point B is an upward slope, and the data collected at this time is inaccurate; the high-power data collected from point B to point C is accurate.

In the falling edge interval, compare the sample values read before and after, and determine whether the input signal changes from the high signal level to the falling edge interval, and whether it changes from the falling edge interval to the low signal level based on the change in data size. The data processing method is as above ( E-1) and (E-2).

When reading sampling data, once multiple consecutive sampling data that are scheduled to be imported into the sampling array are read and change from constant high-bit data to rising data (the previous data read is lower than the latter data), the signal is considered to enter the falling edge. , start the sampling delay at this time. When multiple consecutive sampled data that are read and scheduled to be imported into the sampling array change from falling data to constant low-bit data (the pre-read data is equal to the post-data), it is considered that the signal enters the low level of the signal from the falling edge, and it ends at this time Sampling delay, resume normal sampling data reading and filling sampling array operations.

There is a downward slope from point C to point D, and the data collected at this time is inaccurate; the low-power data collected from point D to point E is accurate. The time sequence of the collected three consecutive power values P1, P2 and P3 is shown in Figure 6. P1 is the latest data collected, followed by P2, and P3 is the earliest data collected.

The collected power values are successively differed to obtain the changes △1=P1-P2, △2=P2-P3; △th is greater than 0, which is the threshold to determine whether the collected data is accurate. When the absolute values of the two changes are greater than or equal to 0, empty signal value or low signal value, and less than the determination threshold Δth, the collected data is accurate. At this time, the corresponding data collected should be retained, otherwise the abnormal data bits should be set to 0, empty signal value or low signal value, or, when outputting the sampled data, skip the data output of the abnormal data bits, that is, A1 and △2 If at least one absolute value is greater than or equal to +△th, the data is incorrect. In this case, all collected data will be discarded.

It should be noted that the rising edge duration (T1) and falling edge duration (T2) in the embodiment of the present invention can be detected and sampled, using the sampling period as the base, and starting when the power rise exceeds the rising threshold. , it ends when the power reaches the falling threshold, calculates the number of samples or sampling timing, and obtains the rising edge duration; on the contrary, it starts when the power decreases beyond the falling threshold, and ends when the power reaches the rising threshold, and calculates the sampling Count or sampling timing to obtain the falling edge duration, or other methods selected by those skilled in the art according to engineering needs, which will not be described again here. This method is especially suitable for solving the problem of inaccurate signal acquisition within a pulse period in the power on and off and pulse (PULSE) modes.

It can be understood that the technical solution provided by this embodiment determines the rising edge interval and falling edge interval within the current pulse cycle, and sets the data bits corresponding to the rising edge interval and falling edge interval in the sampling array to 0, signal low bit, or For an empty signal, use the FIFO (First Input First Output, First In First Out) sampling array to set it to 0 to mask out the data in the abnormal section, that is, make the data in the slope section output 0 in the power on and off and PULSE modes, only in the other areas outside the slope. Output power in the correct time period.

Embodiment three:

As shown in Figure 7, the embodiment of the present invention also provides a radio frequency power signal acquisition device, including: an abnormal data interval determination module 71, used to determine the rising edge interval and falling edge interval within the current pulse cycle; the sampled data is set to 0 mode Group 72 is used to set the data bits corresponding to the rising edge interval and falling edge interval in the sampling array to 0, low signal, or empty signal.

In some embodiments, as shown in the dotted line in Figure 7, the device also includes: a FIFO array output module 73, used for reading and sequentially outputting sampled data from the sampling array outside the rising edge interval and falling edge interval.

In some embodiments, the above-mentioned sampling data setting 0 module 72 sets the data bits corresponding to the rising edge interval and the falling edge interval in the sampling array to 0, and the signal low bit or empty signal is: sampling data setting The 0 module 72 sets the data bits corresponding to the rising edge interval and the falling edge interval in the sampling array to 0, a low signal, or a null signal by setting the sampling delay or the sampling data output to 0.

In some embodiments, as shown in the dotted line part in Figure 7, the sample data setting module 72 includes:

The rising edge exception processing sub-module 721 is used to set the data bit corresponding to the rising edge interval in the sampling array to 0, low signal or empty signal by delaying the sampling time during data sampling in the rising edge interval, or, in When sampling data is output, set the data bit corresponding to the rising edge interval in the sampling array to 0, low signal, or empty signal;

The falling edge exception processing sub-module 722 is used to set the data bit corresponding to the falling edge interval in the sampling array to 0, low signal or empty signal by delaying the sampling time during data sampling in the falling edge interval, or, in When sampling data is output, set the falling edge interval or the data bit corresponding to the falling edge interval in the sampling array to 0, low signal, or empty signal.

In some embodiments, during the sampling process, the above-mentioned rising edge exception processing sub-module 721 sets the data bit corresponding to the rising edge interval in the sampling array to 0, low signal or empty signal by delaying the sampling time, including: rising edge exception processing Starting from the starting point of the rising edge in the current pulse period, sub-module 721 starts the first sampling delay, and sets the data bit corresponding to the first sampling delay in the sampling array to 0, low signal, or empty signal. The above-mentioned falling edge exception processing sub-module 722 sets the data bit corresponding to the falling edge interval in the sampling array to 0 by delaying the sampling time, and the signal low bit or empty signal includes: starting from the starting point of the falling edge in the current pulse cycle, starting the first Second sampling delay, set the data bit corresponding to the second sampling delay in the sampling array to 0, low signal, or empty signal.

In some embodiments, the above-mentioned rising edge exception processing sub-module 721 sets the data bit corresponding to the rising edge interval in the sampling array to 0, a low signal or an empty signal including: after completing the processing of the rising edge end point in the current pulse period. While the signal is being sampled, the first abnormal data is determined. The first abnormal data is the first preset length in the sampling array starting from the data bit corresponding to the rising edge end point and counting forward. The first abnormal data is set to 0, the signal is low or the empty signal, and the first preset length is the array length corresponding to the rising edge interval; the above-mentioned falling edge exception processing sub-module 722 will sample the array corresponding to the falling edge interval. Setting the data bit to 0, low signal or empty signal includes: while completing the signal sampling of the falling edge end point in the current pulse cycle, determine the second abnormal data. The second abnormal data is within the sampling array and ends from the falling edge. Starting from the data bit corresponding to the point, count the data within the second preset length forward, set the second abnormal data to 0, signal low or empty signal, and the second preset length is the array length corresponding to the falling edge interval.

In some embodiments, the above-mentioned rising edge exception processing sub-module 721 sets the data bit corresponding to the first sampling delay in the sampling array to 0, and the signal low bit or empty signal is: sets the first preset sampling duration in the sampling array to The data bit is set to 0, the signal is low or the null signal, and the delay ends; the above-mentioned falling edge exception processing sub-module 722 sets the data bit corresponding to the second sampling delay in the sampling array to 0, the signal is low or the null signal is: sample The data bit corresponding to the second preset sampling duration in the array is set to 0, low signal or empty signal, and the delay ends.

In some embodiments, the above-mentioned rising edge exception processing sub-module 721 sets the data bit corresponding to the first sampling delay in the sampling array to 0, and the signal low bit or empty signal is: the rising edge exception processing sub-module 721 sets the data bit in the sampling array to 0. The data bit corresponding to the first preset array length is set to 0, signal low or empty signal, and the delay ends; the above-mentioned falling edge exception processing sub-module 722 sets the data bit corresponding to the second sampling delay in the sampling array to 0, signal low Or an empty signal: the falling edge exception processing sub-module 722 sets the data bit corresponding to the second preset array length in the sampling array to 0, a low signal or an empty signal, and the delay ends.

In some embodiments, the abnormal data interval determination module 71 includes: a reference threshold determination unit, used to determine the rising edge interval and falling edge interval in the current pulse period through the reference threshold, the rising edge duration and the falling edge duration, so The reference threshold is used to mark the low level of the signal; or, the top threshold determination unit is used to determine the rising edge interval in the current pulse cycle through the reference threshold and the top threshold. and a falling edge interval, where the top threshold is used to mark the high level of the signal; or a power determination unit is used to determine the rising edge interval and falling edge interval within the current pulse period through the power change of the sampling point.

In some embodiments, the first preset sampling duration is equal to the rising edge duration, and the second preset sampling duration is equal to the falling edge duration.

In some embodiments, the first preset array length and the second preset array length are determined according to a preset operation relationship between the rising edge duration or the falling edge duration and the sampling period.

In a specific embodiment, the first preset array length = rising edge duration/sampling period, the second preset array length = falling edge duration/sampling period; or, the first preset array length = the second preset Array length = rising edge duration/sampling period; or, first preset array length = second preset array length = falling edge duration/sampling period.

In some embodiments, as shown in the dotted line in Figure 7, the abnormal data interval determination module 71 includes: a rising edge starting point acquisition sub-module 711. The rising edge starting point is the first time the power is in the current pulse cycle. The sampling point is greater than the rising edge reference threshold; the falling edge starting point acquisition sub-module 712, the falling edge starting point is the sampling point where the power is less than the falling edge reference threshold for the first time in the current pulse cycle.

In some embodiments, if the first preset array length = the second preset array length = rising edge duration/sampling period, and the rising edge duration is greater than the falling edge duration, then the sampling data is set to 0 by the module 72 through sampling The method of delaying or setting the sampling data output to 0 sets the data bits corresponding to the rising edge interval and the falling edge interval in the sampling array to 0. The signal low bit or the empty signal includes: when the sampling data is output, the sampling data is set to 0. The module 72 is in While completing the signal sampling of the falling edge end point in the current pulse cycle, calculate the third delay duration. The third delay duration is the difference between the rising edge duration and the falling edge duration. Start the third delay. At the end of the third delay, the third abnormal data is determined. The third abnormal data is the data within the third preset length in the sampling array starting from the data bit corresponding to the third delay end point and counting forward. The third abnormal data is Set to 0, low signal or empty signal, the third preset length is the array length corresponding to the falling edge interval.

It can be understood that the technical solution provided by this embodiment determines the rising edge interval and falling edge interval within the current pulse cycle, and sets the data bits corresponding to the rising edge interval and falling edge interval in the sampling array to 0, signal low bit, or For an empty signal, use the FIFO (First Input First Output, First In First Out) sampling array to set it to 0 to mask out the data in the abnormal section, that is, make the data in the slope section output 0 in the power on and off and PULSE modes, only in the other areas outside the slope. Output power in the correct time period.

Embodiment 4:

Based on the same technical concept, an embodiment of the present application also provides a computer device, including a memory 1 and a processor 2. As shown in Figure 8, the memory 1 stores a computer program. When the processor 2 executes the computer program Implement the radio frequency power signal acquisition method described in any of the above.

Wherein, the memory 1 includes at least one type of readable storage medium, and the readable storage medium includes flash memory, hard disk, multimedia card, card-type memory (for example, SD or DX memory, etc.), magnetic memory, magnetic disk , CD, etc. In some embodiments, the memory 1 may be an internal storage unit of the OTT video service monitoring system, such as a hard disk. In other embodiments, the memory 1 can also be an external storage device of the OTT video service monitoring system, such as a plug-in hard drive, a smart media card (SMC), a secure digital (SD) card, a fast Flash Card, etc. Furthermore, the memory 1 may also include both an internal storage unit and an external storage device of the OTT video service monitoring system. The memory 1 can not only be used to store application software and various data installed in the OTT video service monitoring system, such as the code of the OTT video service monitoring program, etc., but can also be used to temporarily store data that has been output or will be output.

In some embodiments, the processor 2 may be a central processing unit (CPU), a controller, a microcontroller, a microprocessor or other data processing chips, used to run program codes or processes stored in the memory 1 Data, such as executing OTT video service monitoring programs, etc.

It can be understood that the technical solution provided by this embodiment determines the rising edge interval and falling edge interval within the current pulse period, and records the corresponding rising edge interval and falling edge interval in the sampling array. The data bit is set to 0, the signal is low or empty, and the FIFO (First Input First Output, first in, first out) sampling array is set to 0 to mask out the data in the abnormal segment, that is, in the power on and off and pulse (PULSE) modes The data output in the ramp segment is 0, and the power is only output in the correct time period outside the ramp.

Disclosed embodiments of the present invention also provide a computer-readable storage medium. A computer program is stored on the computer-readable storage medium. When the computer program is run by a processor, the steps of the radio frequency power signal acquisition method described in the above method embodiment are executed. . The storage medium may be a volatile or non-volatile computer-readable storage medium.

The computer program product of the radio frequency power signal acquisition method provided by the disclosed embodiments of the present invention includes a computer-readable storage medium storing program code. The instructions included in the program code can be used to execute the radio frequency power supply described in the above method embodiments. For details of the steps of the signal acquisition method, please refer to the above method embodiments and will not be described again here.

Disclosed embodiments of the present invention also provide a computer program, which, when executed by a processor, implements any of the methods in the foregoing embodiments. The computer program product can be implemented specifically through hardware, software or a combination thereof. In an optional embodiment, the computer program product is embodied as a computer storage medium. In another optional embodiment, the computer program product is embodied as a software product, such as a Software Development Kit (SDK), etc. wait.

It can be understood that the same or similar parts in the above-mentioned embodiments can be referred to each other, and the content that is not described in detail in some embodiments can be referred to the same or similar content in other embodiments.

It should be noted that in the description of the present invention, the terms "first", "second", etc. are only used for description purposes and cannot be understood as indicating or implying relative importance. Furthermore, in the description of the present invention, unless otherwise stated, the meaning of "plurality" means at least two.

Any process or method description in a flowchart or otherwise described herein may be understood to represent a module, segment, or code that includes one or more executable instructions for implementing a specified logical function or step of the process. part, and the scope of the preferred embodiments of the present invention includes additionally Implementations in which functions may be performed out of the order shown or discussed, including in a substantially simultaneous manner or in a reverse order depending on the functionality involved, should be understood by those skilled in the art to which embodiments of the invention belong. understood.

It should be understood that various parts of the present invention may be implemented in hardware, software, firmware, or a combination thereof. In the above-described embodiments, various steps or methods may be implemented in software or firmware stored in a memory and executed by a suitable instruction execution system. For example, if it is implemented in hardware, as in another embodiment, it can be implemented by any one or a combination of the following technologies known in the art: having a logic gate circuit for implementing a logical function on the data signal Discrete logic circuits, special integrated circuits with appropriate combinational logic gates, programmable gate arrays (PGA), field programmable gate arrays (FPGA), etc.

Those of ordinary skill in the art can understand that all or part of the steps involved in implementing the methods of the above embodiments can be completed by instructing relevant hardware through a program. The program can be stored in a computer-readable storage medium, and the program can be stored in a computer-readable storage medium. When executed, one of the steps of the method embodiment or a combination thereof is included.

In addition, each functional unit in various embodiments of the present invention can be integrated in a processing module, or each unit can exist physically alone, or two or more units can be integrated in one module. The above integrated modules can be implemented in the form of hardware or software function modules. If the integrated module is implemented in the form of a software function module and sold or used as an independent product, it can also be stored in a computer-readable storage medium.

The storage medium mentioned above may be a read-only memory, a magnetic disk or an optical disk, etc.

In the description of this specification, reference to the terms "one embodiment," "some embodiments," "examples," "particular examples," or "some examples" or the like means that specific features are described in connection with the embodiment or example. , structures, materials or features are included in at least one embodiment or example of the invention. In this specification, schematic representations of the above terms do not necessarily refer to the same embodiment or example. and, The specific features, structures, materials or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

Although the embodiments of the present invention have been shown and described above, it can be understood that the above-mentioned embodiments are exemplary and cannot be understood as limitations of the present invention. Those of ordinary skill in the art can make various modifications to the above-mentioned embodiments within the scope of the present invention. The embodiments are subject to changes, modifications, substitutions and variations.

S11, S12, S13: steps

Claims (17)

A radio frequency power signal acquisition method, which includes: Determine the rising edge interval and falling edge interval within the current pulse cycle; Set the data bits in the sampling array corresponding to the rising edge interval and the falling edge interval to 0, a low signal, or a null signal. The radio frequency power signal acquisition method as described in request item 1, wherein the data bit corresponding to the rising edge interval and the falling edge interval in the sampling array is set to 0, the signal low bit or the empty signal is: through sampling The data bits corresponding to the rising edge interval and the falling edge interval in the sampling array are set to 0, low signal, or empty signal by delaying or setting the sampling data output to 0. The radio frequency power signal acquisition method as described in request item 2, wherein the data bits corresponding to the rising edge interval and the falling edge interval in the sampling array are set to 0 by sampling delay or setting the sampling data output to 0. 0. Low or empty signals include: In the rising edge interval, when data is sampled, the data bit corresponding to the rising edge interval in the sampling array is set to 0, low signal or empty signal by delaying the sampling time, or, when the sampling data is output, the data bit in the sampling array is set to The data bit corresponding to the rising edge interval is set to 0, low signal or empty signal; In the falling edge interval, when data is sampled, the data bit corresponding to the falling edge interval in the sampling array is set to 0, low signal or empty signal by delaying the sampling time, or, when the sampling data is output, the data bit in the sampling array is set to The falling edge interval or the data bit corresponding to the falling edge interval is set to 0, a low signal or a null signal. The radio frequency power signal acquisition method as described in request item 3, wherein the data bit corresponding to the rising edge interval in the sampling array is set to 0 by delaying the sampling time, and the signal low bit or empty signal includes: within the current pulse period Starting from the starting point of the rising edge, start the first sampling delay, and set the data bit corresponding to the first sampling delay in the sampling array to 0, low signal, or empty signal; Delaying the sampling time to set the data bit corresponding to the falling edge interval in the sampling array to 0, low signal or empty signal includes: starting from the starting point of the falling edge in the current pulse cycle, starting the second sampling delay, The data bit corresponding to the second sampling delay in the sampling array is set to 0, a low signal, or a null signal. The radio frequency power signal acquisition method as described in request item 3, wherein said setting the data bit corresponding to the rising edge interval in the sampling array to 0, low signal or empty signal includes: completing the rising edge in the current pulse period. While sampling the signal at the edge end point, the first abnormal data is determined. The first abnormal data is within the first preset length in the sampling array starting from the data bit corresponding to the rising edge end point and counting forward. data, set the first abnormal data to 0, low signal or empty signal, and the first preset length is the array length corresponding to the rising edge interval; Setting the data bit corresponding to the falling edge interval in the sampling array to 0, low signal, or empty signal includes: while completing signal sampling of the falling edge end point in the current pulse cycle, determining the second abnormal data, The second abnormal data is the data within the second preset length in the sampling array, starting from the data bit corresponding to the falling edge end point and counting forward. The second abnormal data is set to 0 and the signal is low. or an empty signal, and the second preset length is the array length corresponding to the falling edge interval. The radio frequency power signal acquisition method as described in request item 4, wherein the step of setting the data bit corresponding to the first sampling delay in the sampling array to 0, the low bit of the signal or the empty signal is: setting the first preset value in the sampling array The data bit corresponding to the sampling duration is set to 0, low signal or empty signal, and the delay ends; The step of setting the data bit corresponding to the second sampling delay in the sampling array to 0, low signal, or empty signal is: setting the data corresponding to the second preset sampling duration in the sampling array to 0, low signal, or empty signal. , the delay ends. The radio frequency power signal acquisition method as described in request item 4, wherein the step of setting the data bit corresponding to the first sampling delay in the sampling array to 0, the low bit of the signal or the empty signal is: setting the first preset value in the sampling array The data bit corresponding to the array length is set to 0, low signal or empty signal, and the delay ends; The step of setting the data bit corresponding to the second sampling delay in the sampling array to 0, low signal, or empty signal is: setting the data bit corresponding to the second preset array length in the sampling array to 0, low signal, or empty signal. , the delay ends. The radio frequency power signal acquisition method as described in claim 4, wherein determining the rising edge interval and falling edge interval within the current pulse cycle includes: The rising edge interval and falling edge interval in the current pulse cycle are determined by the reference threshold, the rising edge duration and the falling edge duration, and the reference threshold is used to mark the low level of the signal; or, The rising edge interval and falling edge interval in the current pulse cycle are determined by the reference threshold and the top threshold, and the top threshold is used to mark the high level of the signal; or, The rising edge interval and falling edge interval in the current pulse period are determined by the power change of the sampling point. The radio frequency power signal acquisition method according to claim 6, wherein the first preset sampling duration is equal to the rising edge duration, and the second preset sampling duration is equal to the falling edge duration. The radio frequency power signal acquisition method according to claim 7, wherein the first preset array length and the second preset array length are determined by the rising edge duration or the falling edge duration and the sampling period. Determined according to the preset operation relationship. The radio frequency power signal acquisition method according to claim 10, wherein the first preset array length=rising edge duration/sampling period, and the second preset array length=falling edge duration/sampling period; or , the first preset array length = the second preset array length = rising edge duration/sampling period; or, the first preset array length = the second preset array length = falling edge time long/sampling period. The radio frequency power signal acquisition method as described in claim 8, wherein determining the rising edge interval and falling edge interval in the current pulse period through the power change of the sampling point includes: Obtain the rising edge starting point, which is the sampling point where the power is greater than the rising edge reference threshold for the first time in the current pulse period; Obtain the starting point of the falling edge, which is the sampling point where the power is less than the falling edge reference threshold for the first time in the current pulse period. The radio frequency power signal acquisition method as described in any one of claims 1 to 12, further comprising: outside the rising edge interval and the falling edge interval, the sampling array reads and sequentially outputs the sampled data . The radio frequency power signal acquisition method as described in claim 11, wherein if the first preset array length = the second preset array length = rising edge duration/sampling period, and the rising edge duration is longer than the falling edge duration, then the data corresponding to the rising edge interval and the falling edge interval in the sampling array is set to 0 by sampling delay or setting the sampling data output to 0. The low signal or empty signal includes: When the sampling data is output, while completing the signal sampling of the falling edge end point in the current pulse cycle, the third delay duration is calculated. The third delay duration is the sum of the rising edge duration and the falling edge duration. Along the difference in duration, the third delay is started. At the end of the third delay, the third abnormal data is determined. The third abnormal data is the corresponding data in the sampling array from the end point of the third delay. Starting from the data bit, count the data within the third preset length forward, and set the third abnormal data to 0, signal low level or empty signal. The third preset length is the array length corresponding to the falling edge interval. A radio frequency power signal acquisition device, which includes: Abnormal data interval determination module is used to determine the rising edge interval and falling edge interval within the current pulse cycle; The sampling data setting module is used to set the data bits corresponding to the rising edge interval and the falling edge interval in the sampling array to 0, low signal or empty signal. A computer device including: A processor, a memory and a bus. The memory stores machine-readable instructions executable by the processor. When the computer device is running, the processor communicates with the memory through the bus, When the machine-readable instructions are executed by the processor, the radio frequency power signal acquisition method described in any one of claims 1 to 14 is executed. A computer-readable storage medium including: A computer program is stored on the computer-readable storage medium, and when the computer program is run by the processor, it executes the radio frequency power signal acquisition method described in any one of claims 1 to 14.

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