CN115001878B - Driver of Ethernet transceiver, control method thereof and Ethernet transceiver - Google Patents

Driver of Ethernet transceiver, control method thereof and Ethernet transceiver Download PDF

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Publication number
CN115001878B
CN115001878B CN202210494899.1A CN202210494899A CN115001878B CN 115001878 B CN115001878 B CN 115001878B CN 202210494899 A CN202210494899 A CN 202210494899A CN 115001878 B CN115001878 B CN 115001878B
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signal
voltage
resistor
output
driver
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CN115001878A (en
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庄志禹
孙飞阳
黄怡仁
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Lianyun Technology Hangzhou Co ltd
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Lianyun Technology Hangzhou Co ltd
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/02—Details
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/38—Transceivers, i.e. devices in which transmitter and receiver form a structural unit and in which at least one part is used for functions of transmitting and receiving
    • H04B1/40—Circuits
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/0264—Arrangements for coupling to transmission lines
    • H04L25/0278—Arrangements for impedance matching

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Power Engineering (AREA)
  • Dc Digital Transmission (AREA)

Abstract

The present disclosure provides a driver of an ethernet transceiver, which is connected to a remote ethernet transceiver through a transmission line, including: the signal conversion module is used for converting the differential current signal provided by the upper circuit into a differential voltage signal; the first driving module and the second driving module respectively generate a first voltage signal and a second voltage signal based on the differential current signal and respectively generate a first output signal with the voltage value equal to the first voltage signal and a second output signal with the voltage value equal to the second voltage signal under the driving of the differential voltage signal; the impedance matching module is connected between the output end of the first voltage signal and the output end of the second voltage signal; and the adjusting module is used for adjusting the impedance of the impedance matching module based on the signals received from the first driving module, the second driving module and the transmission line so as to match the impedance between the equivalent impedance of the driver and the characteristic impedance of the transmission line, thereby achieving the aim of minimizing the mixed residual voltage.

Description

Driver of Ethernet transceiver, control method thereof and Ethernet transceiver
Technical Field
The present disclosure relates to the technical field of ethernet transceivers, and in particular, to a driver of an ethernet transceiver, a control method thereof, and an ethernet transceiver.
Background
According to SPEC (Standard Performance Evaluation Corporation) requirements, GBE (Gigabit Ethernet) uses different output swings for its transceivers in different modes. For example, the output swing of the transceiver in the 10BASE-T mode is 4.4-5.6V, and the output swing of the transceiver in the 100BASE-TX and 1000BASE-T modes is 1.9-2.1V. To meet the output swing requirements, multimode ethernet transceivers have evolved. However, the existing multimode ethernet transceiver realizes the self-adaptive function of minimizing the mixed residual voltage by adjusting the active device, which has a nonlinear problem and is difficult to adjust.
Disclosure of Invention
In order to solve the technical problems, the present disclosure provides a driver of an ethernet transceiver, a control method thereof, and an ethernet transceiver, which achieve minimization of a hybrid residual voltage by adjustment of a passive device.
A first aspect of the present disclosure provides a driver of an ethernet transceiver, the driver having a first output port and a second output port, the first output port and the second output port being connected to a remote ethernet transceiver by a transmission line, the driver comprising:
the signal conversion module is connected with the upper circuit and used for converting the differential current signal provided by the upper circuit into a differential voltage signal;
A first driving module connected with the first output port and provided with a third output end, wherein the first driving module is used for generating a first voltage signal at the third output end based on one of the differential current signals and generating a first output signal with a voltage value equal to the first voltage signal at the first output port under the driving of one of the differential voltage signals;
A second driving module connected to the second output port and having a fourth output terminal for generating a second voltage signal at the fourth output terminal based on another one of the differential current signals, and generating a second output signal having a voltage value equal to the second voltage signal at the second output port under the driving of the other one of the differential voltage signals;
the impedance matching module is connected between the third output end and the fourth output end;
The signal output end of the adjusting module is connected with the impedance matching module;
The adjusting module is used for generating control signals based on signals received from the first driving module, the second driving module and the transmission line and transmitting the control signals to the impedance matching module so as to adjust the impedance of the impedance matching module through the control signals, and enable the equivalent impedance of the driver to be matched with the characteristic impedance of the transmission line.
Optionally, the adjustment module includes: the device comprises a mixing unit, an analog-to-digital converter and a controller;
The four input ends of the mixing unit are respectively connected with the third output end, the transmission line connected with the first output port, the fourth output end and the transmission line connected with the second output port, the first analog signal output port and the second analog signal output port of the mixing unit are respectively connected with the analog-to-digital converter, and are used for generating differential analog signals based on signals received by the four input ends and transmitting the differential analog signals to the analog-to-digital converter, wherein the difference value of the differential analog signals is the difference value of the transmission signals and the mixed residual voltage of the far-end Ethernet transceiver;
The two input ports of the analog-to-digital converter are respectively connected with the mixing unit, and the digital signal output port of the analog-to-digital converter is connected with the controller and is used for converting the differential analog signals into digital signals and transmitting the digital signals to the controller;
The input end of the controller is connected with the analog-to-digital converter, and the signal output end of the controller is connected with the impedance matching module and is used for generating the control signal based on the digital signal and transmitting the control signal to the impedance matching module.
Optionally, the mixing unit includes:
A first operational amplifier;
a ninth resistor and a tenth resistor are connected in series between the first input end of the mixing unit and the in-phase output end of the first operational amplifier, and a node between the ninth resistor and the tenth resistor is connected with the inverting input end of the first operational amplifier;
an eleventh resistor connected between the second input terminal of the mixing unit and the inverting input terminal of the first operational amplifier;
a twelfth resistor connected between the third input terminal of the mixing unit and the non-inverting input terminal of the first operational amplifier;
A thirteenth resistor and a fourteenth resistor connected in series between the fourth input terminal of the mixing unit and the inverting output terminal of the first operational amplifier, and a node between the thirteenth resistor and the fourteenth resistor is connected with the non-inverting input terminal of the first operational amplifier;
wherein the ninth resistor, the tenth resistor, the eleventh resistor, the twelfth resistor, the thirteenth resistor, and the fourteenth resistor have the same resistance value.
Optionally, the impedance matching module includes:
A first varistor and a second varistor connected in series between the third output terminal and the fourth output terminal;
the first rheostat and the second rheostat are connected with the adjusting module through respective resistance control ends so as to respectively adjust respective resistance values according to the control signals.
Optionally, the signal conversion module comprises a second operational amplifier, wherein,
The second operational amplifier is provided with a first current input end and a second current input end, and the first current input end and the second current input end are respectively connected with the upper-level circuit and are used for receiving the differential current signal from the upper-level circuit;
The second operational amplifier further has a first voltage output terminal and a second voltage output terminal for outputting the differential voltage signal.
Optionally, the first driving module includes:
the first resistor is connected in series between the first current input end and the third output end;
the third resistor is connected in series between the third output end and the first output port;
The drain electrodes of the first PMOS tube and the first NMOS tube are connected with the third output end, the grid electrodes of the first PMOS tube and the first NMOS tube are connected with the first voltage output end, the source electrode of the first PMOS tube is connected with the power supply end, and the source electrode of the first NMOS tube is grounded;
The drain electrodes of the third PMOS tube and the third NMOS tube are connected with the first output port, the grid electrodes of the third PMOS tube and the third NMOS tube are connected with the first voltage output end, the source electrode of the third PMOS tube is connected with the power supply end, and the source electrode of the third NMOS tube is grounded.
Optionally, the second driving module includes:
the second resistor is connected in series between the second current input end and the fourth output end;
the fourth resistor is connected in series between the fourth output end and the second output port;
The drain electrodes of the second PMOS tube and the second NMOS tube are connected with the fourth output end, the grid electrodes of the second PMOS tube and the second NMOS tube are connected with the second voltage output end, the source electrode of the second PMOS tube is connected with the power supply end, and the source electrode of the second NMOS tube is grounded;
The drain electrodes of the fourth PMOS tube and the fourth NMOS tube are connected with the second output port, the grid electrodes of the fourth PMOS tube and the fourth NMOS tube are connected with the second voltage output end, the source electrode of the fourth PMOS tube is connected with the power supply end, and the source electrode of the fourth NMOS tube is grounded.
Optionally, the ratio of the width-to-length ratio of the third PMOS transistor to the width-to-length ratio of the first PMOS transistor is N, and the ratio of the width-to-length ratio of the fourth PMOS transistor to the width-to-length ratio of the second PMOS transistor is N;
And the ratio of the width-to-length ratio of the third NMOS tube to the width-to-length ratio of the first NMOS tube is N, and the ratio of the width-to-length ratio of the fourth NMOS tube to the width-to-length ratio of the second NMOS tube is N.
Optionally, the resistances of the third resistor and the fourth resistor are (n+1) times the resistance of the equivalent impedance of the driver in the far-end ethernet transceiver, and the resistance of the equivalent impedance of the driver in the far-end ethernet transceiver is equal to the characteristic impedance of the transmission line.
A second aspect of the present disclosure provides an ethernet transceiver comprising a superior circuit and any one of the drivers of the first aspect, the superior circuit being configured to provide a differential current signal to the driver in accordance with an output swing of a current mode of the ethernet transceiver.
A third aspect of the present disclosure provides a control method of a driver, applied to any one of the drivers described in the first aspect, the method comprising:
generating control signals according to signals received from the first driving module, the second driving module and the transmission line;
and transmitting the control signal to the impedance matching module so as to adjust the impedance of the impedance matching module through the control signal, and enabling the equivalent impedance of the driver to be matched with the characteristic impedance of the transmission line.
Optionally, generating a control signal according to signals received from the first driving module, the second driving module, and the transmission line includes:
generating a differential analog signal based on signals received from the first driving module, the second driving module, and the transmission line, wherein a difference value of the differential analog signal is a difference value between a transmission signal and a mixed residual voltage of the far-end ethernet transceiver;
the differential analog signal is converted to a digital signal, and the control signal is generated based on the digital signal.
Optionally, the control signal adjusts the impedance of the impedance matching module to control the mixed remnant voltage to be minimized.
The beneficial effects of the present disclosure are:
In the driver of the Ethernet transceiver of the disclosure, the signal conversion module converts the differential current signal provided by the upper circuit into a differential voltage signal; the first driving module generates a first voltage signal at a third output end based on one of the differential current signals, and generates a first output signal with a voltage value equal to the first voltage signal at a first output port under the driving of one of the differential voltage signals; the second driving module generates a second voltage signal at the fourth output end based on the other one of the differential current signals, and generates a second output signal with a voltage value equal to the second voltage signal at the second output port under the driving of the other one of the differential voltage signals; the impedance matching module is connected between the third output end and the fourth output end; the adjusting module generates a control signal based on signals received from the first driving module, the second driving module and the transmission line and adjusts the impedance of the impedance matching module through the control signal, so that the equivalent impedance of the driver is matched with the characteristic impedance of the transmission line, the purpose of minimizing the mixed residual voltage is achieved, and compared with a method for adjusting an active device, the method has no nonlinear problem and is low in adjustment difficulty. In addition, the differential current signal provided by the upper circuit is adjusted to meet the output swing requirement of the current mode without voltage loss, so that the differential current circuit can be applied to multiple modes.
Drawings
The above and other objects, features and advantages of the present disclosure will become more apparent from the following description of the embodiments of the present disclosure with reference to the accompanying drawings.
FIG. 1 illustrates a block diagram of a driver in an embodiment of the present disclosure;
FIG. 2 illustrates a circuit diagram of a conditioning module in an embodiment of the present disclosure;
FIG. 3 shows a circuit diagram of a partial structure of a driver in an embodiment of the present disclosure;
FIG. 4 illustrates a block diagram of an Ethernet transceiver in an embodiment of the disclosure;
fig. 5 shows a flow chart of a control method of a driver in an embodiment of the present disclosure.
Detailed Description
In order that the disclosure may be understood, a more complete description of the disclosure will be rendered by reference to the appended drawings. Preferred embodiments of the present disclosure are shown in the drawings. The present disclosure may be embodied in different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used in the description of the present disclosure is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure.
Fig. 1 is a block diagram illustrating a driver of an ethernet transceiver in an embodiment of the present disclosure. Referring to fig. 1, the driver 1100 (hereinafter referred to as driver 1100) of the ethernet transceiver provided in the embodiments of the present disclosure is a local ethernet transceiver, and has a first output port TXN and a second output port TXP, where the first output port TXN and the second output port TXP are connected to a remote ethernet transceiver through transmission lines (including a first transmission line cable_n connected to the first output port TXN and a second transmission line cable_p connected to the second output port TXP).
Referring to fig. 1, the driver 1100 further includes a signal conversion module 110, a first driving module 120, a second driving module 130, an impedance matching module 140, and an adjustment module 150.
The signal conversion module 110 is connected to the upper circuit, and is configured to convert differential current signals I-and i+ provided by the upper circuit into differential voltage signals V-and v+. The first driving module 120 is connected to the first output port TXN, has a third output end ECN, and is configured to generate a first voltage signal V ecn at the third output end ECN based on i+ in the differential current signal, and generate a first output signal V txn having a voltage value equal to the first voltage signal V ecn at the first output port TXN under the driving of V-in the differential voltage signal. The second driving module 130 is connected to the second output port TXP and has a fourth output end ECP for generating a second voltage signal V ecp at the fourth output end ECP based on I-in the differential current signal and generating a second output signal V txp having a voltage value equal to the second voltage signal V ecp at the second output port TXP driven by v+ in the differential voltage signal. The impedance matching module 140 is connected between the third output terminal ECN and the fourth output terminal ECP. The adjusting module 150 is respectively connected to the first driving module 120, the second driving module 130, the first transmission line cable_n and the second transmission line cable_p, and a signal output end of the adjusting module 150 is connected to the impedance matching module 140. The adjusting module 150 is configured to generate a control signal Con based on signals received from the first driving module 120, the second driving module 130, the first transmission line cable_n and the second transmission line cable_p and transmit the control signal Con to the impedance matching module 140, so as to adjust the impedance of the impedance matching module 140 by the control signal Con, and match the impedance between the equivalent impedance of the driver 1100 and the characteristic impedance of the transmission line.
It should be noted that, in the driver 1100, the first driving module 120 and the second driving module 130 form a differential structure, the first voltage signal V ecn and the second voltage signal V ecp have equal amplitudes and opposite phases, and the first output signal V txn and the second output signal V txp have equal amplitudes and opposite phases, and the voltage difference between the first output signal V txn and the second output signal V txp is the output swing of the ethernet transceiver including the driver 1100.
In the case where the impedance between the equivalent impedance of the driver 1100 and the characteristic impedance of the transmission line is not matched or the characteristic impedance of the transmission line is not matched with the equivalent impedance of the driver 2100 (hereinafter referred to as the driver 2100) in the far-end ethernet transceiver, a mixed survivor voltage (also referred to as a mixed leakage voltage, or hybrid leakage voltage) is caused, in which case the first output port TXN also outputs the first mixed survivor signal V ern and the second output port TXP also outputs the second mixed survivor signal V erp, and the amplitudes of the first mixed survivor signal V ern and the second mixed survivor signal V erp are equal and the phases are opposite, and the voltage difference between the first mixed survivor signal V ern and the second mixed survivor signal V erp is the mixed survivor voltage.
Meanwhile, for the driver 1100 operating in duplex mode, there is a transmission signal sent by the far-end ethernet transceiver on the transmission line, where the first transmission line cable_n transmits the first reception signal V rxn, the second transmission line cable_p transmits the second reception signal V rxp, and the first reception signal V rxn and the second reception signal V rxp have equal amplitudes and opposite phases, and a voltage difference between the first reception signal V rxn and the second reception signal V rxp is the transmission signal of the far-end ethernet transceiver.
Based on the above, the first output signal V txn and the first mixed residual signal V ern sent by the driver 1100 and the first receiving signal V rxn sent by the far-end ethernet transceiver are transmitted on the first transmission line cable_n, so that the signal received by the adjusting module 150 from the first transmission line cable_n is V txn+Vern+Vrxn; the second output signal V txp and the second mixed residual signal V erp sent by the driver 1100 and the second receiving signal V rxp sent by the far-end ethernet transceiver are transmitted on the second transmission line cable_p, so that the signal received by the adjusting module 150 from the second transmission line cable_p is V txp+Verp+Vrxp.
It should be noted that, as shown in fig. 1 and 2, the driver 1100 of the local ethernet transceiver includes a transmitting unit 1TX and a receiving unit 1RX, the converting module 110, the first driving module 120, the second driving module 130 and the impedance matching module 140 belong to the transmitting unit 1TX, and the mixing unit 151 and the analog-to-digital converter 152 in the adjusting module 150 belong to the receiving unit 1RX.
Fig. 2 shows a circuit diagram of the adjustment module 150. Referring to fig. 2, the adjustment module 150 includes: a mixing unit 151, an analog-to-digital converter 152, and a control unit 153.
The four input terminals (including the first input terminal CN1, the second input terminal CN2, the third input terminal CN3, and the fourth output terminal CN 4) of the mixing unit 151 are respectively connected to the third output terminal ECN, the second transmission line cable_p, the first transmission line cable_n, and the fourth output terminal ECP in fig. 1 as shown in fig. 1, and the first analog signal output port D1 and the second analog signal output port D2 of the mixing unit 151 are respectively connected to the analog-to-digital converter 152 for generating differential analog signals ana+ and Ana-based on signals received by the four input terminals and transmitting the differential analog signals ana+ and Ana-to the analog-to-digital converter 152. The two input ports E1 and E2 of the analog-to-digital converter 152 are respectively connected to the mixing unit 151 (as shown in fig. 2, the input port E1 of the analog-to-digital converter 152 is connected to the first analog signal output port D1 of the mixing unit 151, the input port E2 of the analog-to-digital converter 152 is connected to the second analog signal output port D2 of the mixing unit 151), and the digital signal output port E3 of the analog-to-digital converter 152 is connected to the control unit 153 for converting the differential analog signals ana+ and Ana-into the digital signals Dig and transmitting to the control unit 153. The input end of the control unit 153 is connected to the analog-to-digital converter 152, i.e. connected to the digital signal output port E3 of the analog-to-digital converter 152, and the signal output end of the control unit 153 is connected to the impedance matching module 140 through the signal output end CF of the adjusting module 150, for generating the control signal Con based on the digital signal Dig and transmitting to the impedance matching module 140.
Referring to fig. 2, the mixing unit 151 specifically includes: a first operational amplifier OPA1; a ninth resistor R9 and a tenth resistor R10 are connected in series between the first input terminal CN1 of the mixing unit 151 and the non-inverting output terminal A3 of the first operational amplifier OPA1, and a node P1 between the ninth resistor R9 and the tenth resistor R10 is connected to the inverting input terminal A2 of the first operational amplifier OPA1; an eleventh resistor R11 connected between the second input terminal CN2 of the mixing unit 151 and the inverting input terminal A2 of the first operational amplifier OPA1; a twelfth resistor R12 connected between the third input terminal CN3 of the mixing unit 151 and the non-inverting input terminal A1 of the first operational amplifier OPA1; a thirteenth resistor R13 and a fourteenth resistor R14 connected in series between the fourth input terminal CN4 of the mixing unit 151 and the inverting output terminal A4 of the first operational amplifier OPA1, and a node P2 between the thirteenth resistor R13 and the fourteenth resistor R14 is connected to the non-inverting input terminal A1 of the first operational amplifier OPA1; the ninth resistor R9, the tenth resistor R10, the eleventh resistor R11, the twelfth resistor R12, the thirteenth resistor R13, and the fourteenth resistor R14 have the same resistance value.
Based on the above-mentioned circuit of the mixing unit 151, when the first input terminal CN1 receives the first voltage signal V ecn from the third output terminal ECN, the second input terminal CN2 receives the signal V txp+Verp+Vrxp from the second transmission line cable_p, the third input terminal CN3 receives the signal V txn+Vern+Vrxn from the first transmission line cable_n, and the fourth input terminal CN4 receives the second voltage signal V ecp from the fourth output terminal ECP, the difference between the differential analog signals ana+ and Ana-is (V rxp-Vrxn)-(Verp-Vern), that is, the difference between the transmission signal and the mixed residual voltage of the far-end ethernet transceiver.
Fig. 3 shows a circuit diagram of a partial structure of the driver. The signal conversion module 110, the first driving module 120, the second driving module 130, and the impedance matching module 140 in the driver will be described in detail with reference to fig. 3.
Circuit structure of signal conversion module 110
The signal conversion module 110 includes a second operational amplifier OPA2.
The second operational amplifier OPA2 has a first current input B1 and a second current input B2. The first current input terminal B1 and the second current input terminal B2 are respectively connected with the upper-stage circuit and are used for receiving differential current signals I-and I+ from the upper-stage circuit.
The second operational amplifier OPA2 further has a first voltage output terminal C1 and a second voltage output terminal C2, the first voltage output terminal C1 and the second voltage output terminal C2 being for outputting differential voltage signals V-and v+.
Further, the first current input terminal B1 of the second operational amplifier OPA2 is a non-inverting input terminal of the second operational amplifier OPA2, and the second current input terminal B2 of the second operational amplifier OPA2 is an inverting input terminal of the second operational amplifier OPA 2; the first voltage output terminal C1 of the second operational amplifier OPA2 is an inverting output terminal of the second operational amplifier OPA2, and the second voltage output terminal C2 of the second operational amplifier OPA2 is an in-phase output terminal of the second operational amplifier OPA 2.
(II) Circuit Structure of first drive Module 120 and second drive Module 130
The first driving module 120 includes: the first resistor R1 is connected in series between the first current input end B1 and the third output end ECN; the third resistor R3 is connected in series between the third output end ECN and the first output port TXN; the drain electrodes of the first PMOS tube PM1 and the first NMOS tube NM1 are connected with the third output end ECN, the grid electrodes of the first PMOS tube PM1 and the first NMOS tube NM1 are connected with the first voltage output end C1, the source electrode of the first PMOS tube PM1 is connected with the power supply end Vcc, and the source electrode of the first NMOS tube NM1 is grounded; the drains of the third PMOS tube PM3 and the third NMOS tube NM3 are connected to the first output port TXN, the gates of the third PMOS tube PM3 are connected to the first voltage output terminal C1, the source of the third PMOS tube PM3 is connected to the power supply terminal Vcc, and the source of the third NMOS tube NM3 is grounded.
The second driving module 130 includes: the second resistor R2 is connected in series between the second current input end B2 and the fourth output end ECP; the fourth resistor R4 is connected in series between the fourth output end ECP and the second output port TXP; the drain electrodes of the second PMOS tube PM2 and the second NMOS tube NM2 are connected with the fourth output end ECP, the grid electrodes of the second PMOS tube PM2 are connected with the second voltage output end C2, the source electrode of the second PMOS tube PM2 is connected with the power supply end Vcc, and the source electrode of the second NMOS tube NM2 is grounded; the drains of the fourth PMOS tube PM4 and the fourth NMOS tube NM4 are both connected to the second output port TXP, the gates of the fourth PMOS tube PM4 are both connected to the second voltage output terminal C2, the source of the fourth PMOS tube PM4 is connected to the power supply terminal Vcc, and the source of the fourth NMOS tube NM4 is grounded.
In the above circuit configuration, the first resistor R1 is operative to generate the first voltage signal V ecn at the third output terminal ECN based on i+ in the differential current signal, and the second resistor R2 is operative to generate the second voltage signal V ecp at the fourth output terminal ECP based on I-in the differential current signal.
Further, the ratio of the width-to-length ratio of the third PMOS tube PM3 to the width-to-length ratio of the first PMOS tube PM1 is N, and the ratio of the width-to-length ratio of the fourth PMOS tube PM4 to the width-to-length ratio of the second PMOS tube PM2 is N.
Because the gate-source voltage of the third PMOS tube PM3 is equal to the gate-source voltage of the first PMOS tube PM1, when the ratio of the width-to-length ratio of the third PMOS tube PM3 to the width-to-length ratio of the first PMOS tube PM1 is N, it is noted that: the current flowing out of the drain of the first PMOS PM1 is I1, and the current I3 flowing out of the drain of the third PMOS PM3 is n·i1 (I1 and I3 are defined herein unless otherwise specified in the following description).
Similarly, since the gate-source voltage of the fourth PMOS tube PM4 is equal to the gate-source voltage of the second PMOS tube PM2, when the ratio of the width-to-length ratio of the fourth PMOS tube PM4 to the width-to-length ratio of the second PMOS tube PM2 is N, it is noted that: the current flowing out of the drain of the second PMOS PM2 is I2, and the current I4 flowing out of the drain of the fourth PMOS PM4 is n·i2 (I2 and I4 are defined herein unless otherwise specified in the following description).
It should be noted that, in the driver shown in fig. 3, the first NMOS transistor NM1 and the third NMOS transistor NM3 and the second NMOS transistor NM2 and the fourth NMOS transistor NM4 are disposed, so that the first driving module 120 and the second driving module 130 are both in an AB structure (i.e. a Class AB structure). Thus, the third NMOS transistor NM3 is also set to have a ratio of N to the first NMOS transistor NM1, and the fourth NMOS transistor NM4 is also set to have a ratio of N to the second NMOS transistor NM 2.
Circuit structure of impedance matching module 140
The impedance matching module 140 includes: a first and a second varistor Rp1, rp2 connected in series between the third and fourth output terminals ECN, ECP. The first varistor Rp1 and the second varistor Rp2 are connected to the adjusting module 150 through respective resistance control terminals to respectively adjust respective resistance values according to the control signal Con.
The signal conversion module 110 receives the differential current signal and provides a differential voltage signal, the first driving module 120 and the second driving module 130 form a differential structure, the impedance matching module 140 forms a symmetrical structure between the third output terminal ECN and the fourth output terminal ECP through the first varistor Rp1 and the second varistor Rp2, and the resistance values of the first varistor Rp1 and the second varistor Rp2 are equal after the resistance adjustment, so that the circuit of the driver 1100 is a fully differential structure.
Further, the resistances of the third resistor R3 and the fourth resistor R4 are set to be (n+1) times the resistance of the equivalent impedance R0 of the driver 2100, and the resistance of the equivalent impedance R0 of the driver 2100 is equal to the characteristic impedance of the transmission line, so that the input end and the output end of the transmission line are respectively in the impedance matching state, and the first output port TXN can be prevented from outputting the first mixed residual signal V ern and the second output port TXP can be prevented from outputting the second mixed residual signal V erp.
It should be noted that, when rp1=n·r0 and rp2=n·r0, impedance matching is performed between the equivalent impedance of the driver 1100 and the characteristic impedance of the transmission line, which is an ideal case, that is, all the electrical components in the driver 1100 are ideal components. For the case where all the electrical components in the driver 1100 are unlikely to be ideal components in practice, the control unit 153 cannot directly achieve impedance matching between the equivalent impedance of the driver 1100 and the characteristic impedance of the transmission line by adjusting rp1=n·r0 and rp2=n·r0, but generates the control signal Con according to the voltage value of the mixed residual voltage to adjust the resistance value of the first varistor Rp1 and the resistance value of the second varistor Rp 2.
Specifically, in the adjustment module 150: the mixing unit 151 generates differential analog signals ana+ and Ana-; the analog-to-digital converter 152 converts the differential analog signals ana+ and Ana-into a digital signal Dig, which is, for example, M bits of data, representing the difference in magnitude between the differential analog signals ana+ and Ana-, i.e.: (V rxp-Vrxn)-(Verp-Vern); the control unit 153 analyzes the voltage value of the mixed residual voltage (i.e., V erp-Vern) from the digital signal Dig based on a predetermined transmission signal (the magnitude is V rxp-Vrxn) of the far-end ethernet transceiver, so as to generate a control signal Con according to the voltage value of the mixed residual voltage to adjust the resistance value of the first varistor Rp1 and the resistance value of the second varistor Rp2, so that the equivalent impedance of the driver 1100 is matched with the characteristic impedance of the transmission line, and further, the magnitude of the mixed residual voltage is changed so as to minimize the mixed residual voltage, thereby realizing the self-adaptive function.
The control unit 153 adjusts the resistance value of the first varistor Rp1 and the resistance value of the second varistor Rp2, which is the circuit of the driver 1100 by controlling the circuit of the analog part of the driver 1100, and thus the adjustment accuracy is high. In addition, the difference between the differential analog signals Ana+ and Ana-is: (V rxp-Vrxn)-(Verp-Vern) whereby the dynamic range of the analog-to-digital converter 152 is maximally applied to quantify the transmission signal of the far-end ethernet transceiver, as little as possible to quantify the voltage value of the mixed survivor voltage, the final adjustment result being: the difference between (V rxp-Vrxn) and (V erp-Vern) is a predetermined voltage value of the transmission signal of the remote ethernet transceiver, which contributes to the overall improvement of the signal reception performance.
In practice, the control unit 153 generates the control signal Con to minimize the mixed residual voltage according to the voltage value of the mixed residual voltage, which may be a process of multiple adjustments. That is, if the mixed residual voltage decreases after the previous adjustment, the control unit 153 adjusts the dicing of the first varistor Rp1 in the same direction and the dicing of the second varistor Rp2 in the same direction in the current adjustment; if the mixed residual voltage increases after the last adjustment, the control unit 153 adjusts the dicing of the first varistor Rp1 and the dicing of the second varistor Rp2 in opposite directions in this adjustment until the mixed residual voltage is small enough to meet the demand.
The driver 1100 provided by the embodiments of the present disclosure can adaptively control the minimization of the mixed residual voltage, and can effectively improve the signal quality and the transmission performance. Since the driver 1100 is configured to minimize the mixed residual voltage by adjusting the resistance values of the first varistor Rp1 and the second varistor Rp2, the method has the advantages of no non-linearity problem and low adjustment difficulty compared with the method of adjusting the active device in the prior art. Moreover, since the differential current signal provided by the upper circuit can be adjusted to meet the output swing requirement of the current mode without voltage loss, the differential current signal can be applied to various modes, such as 1000BASE-T, 1000BASE-T1, 100BASE-T1, 10BASE-T1S, 10BASE-T1 and any other full-duplex (full-duplex) specifications; in addition, the first input CN1 and the fourth input CN4 of the mixing unit 151 are turned off, and the method can be applied to unidirectional transmission specifications such as 10BASE-T and 100 BASE-TX.
Corresponding to the driver of the ethernet transceiver provided above, the embodiment of the present disclosure further provides an ethernet transceiver. Referring to fig. 4, the ethernet transceiver includes a superior circuit 1200 and a driver 1100, the superior circuit 1200 being configured to provide differential current signals I-and i+ to the driver 1100 according to an output swing of a current mode of the ethernet transceiver. The upper circuit 1200 is, for example, a digital-to-analog converter (digital to analog converter, DAC for short) that provides differential current signals I-and I+. The driver 1100 is the driver provided in the above embodiment, so that the ethernet transceiver can adaptively control the minimization of the mixed residual voltage, can effectively improve the signal quality and the transmission performance, has the advantages of no nonlinearity problem and low adjustment difficulty, and can be applied to multiple modes.
In response to the above-provided driver of the ethernet transceiver, the embodiment of the present disclosure further provides a control method of the driver, which is applied to any one of the drivers 1100 described above to adaptively control the mixed residual voltage minimization. Referring to fig. 5, the control method includes:
in step S110, a control signal Con is generated according to signals received from the first driving module 120, the second driving module 130, and the transmission line.
In step S120, the control signal Con is transmitted to the impedance matching module 140, so as to adjust the impedance of the impedance matching module 140 by the control signal Con, and match the impedance between the equivalent impedance of the driver and the characteristic impedance of the transmission line.
In an alternative embodiment, step S110, generating the control signal Con according to the signals received from the first driving module 120, the second driving module 130, and the transmission line includes: the differential analog signals Ana+ and Ana-are generated based on the signals received from the first driving module 120, the second driving module 130, and the transmission line, and the difference between the differential analog signals Ana+ and Ana-is: (V rxp-Vrxn)-(Verp-Vern) which is the difference between the transmission signal of the far-end ethernet transceiver and the mixed residual voltage; the differential analog signal is then converted to a digital signal and a control signal is generated based on the digital signal.
In an alternative embodiment, the control signal adjusts the impedance of the impedance matching module to match the impedance between the equivalent impedance of the driver and the characteristic impedance of the transmission line, so as to control the mixed residual voltage to be minimized. The mixed residual voltage minimization is adaptively controlled by adjusting the resistance value, and compared with the mixed residual voltage minimization realized by adjusting an active device, the mixed residual voltage minimization is easier to adjust and has no nonlinear problem.
Since the embodiment of the driver 1100 has been described in detail, the execution of the control method of the driver 1100 is not described in detail here.
Furthermore, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
Finally, it should be noted that: it is apparent that the above examples are merely illustrative of the present disclosure and are not limiting of the embodiments. Other variations or modifications of the above teachings will be apparent to those of ordinary skill in the art. It is not necessary here nor is it exhaustive of all embodiments. And obvious variations or modifications thereof are contemplated as falling within the scope of the present disclosure.

Claims (11)

1. A driver for an ethernet transceiver, the driver having a first output port and a second output port, the first output port and the second output port being connected to a remote ethernet transceiver by a transmission line, the driver comprising:
the signal conversion module is connected with the upper circuit and used for converting the differential current signal provided by the upper circuit into a differential voltage signal;
A first driving module connected with the first output port and provided with a third output end, wherein the first driving module is used for generating a first voltage signal at the third output end based on one of the differential current signals and generating a first output signal with a voltage value equal to the first voltage signal at the first output port under the driving of one of the differential voltage signals;
A second driving module connected to the second output port and having a fourth output terminal for generating a second voltage signal at the fourth output terminal based on another one of the differential current signals, and generating a second output signal having a voltage value equal to the second voltage signal at the second output port under the driving of the other one of the differential voltage signals;
the impedance matching module is connected between the third output end and the fourth output end;
The signal output end of the adjusting module is connected with the impedance matching module;
The adjusting module is used for generating a control signal based on signals received from the first driving module, the second driving module and the transmission line and transmitting the control signal to the impedance matching module so as to adjust the impedance of the impedance matching module through the control signal, so that the equivalent impedance of the driver is matched with the characteristic impedance of the transmission line;
the adjustment module includes: the device comprises a mixing unit, an analog-to-digital converter and a controller;
The four input ends of the mixing unit are respectively connected with the third output end, the transmission line connected with the first output port, the fourth output end and the transmission line connected with the second output port, the first analog signal output port and the second analog signal output port of the mixing unit are respectively connected with the analog-to-digital converter, and are used for generating differential analog signals based on signals received by the four input ends and transmitting the differential analog signals to the analog-to-digital converter, wherein the difference value of the differential analog signals is the difference value of the transmission signals and the mixed residual voltage of the far-end Ethernet transceiver;
The two input ports of the analog-to-digital converter are respectively connected with the mixing unit, and the digital signal output port of the analog-to-digital converter is connected with the controller and is used for converting the differential analog signals into digital signals and transmitting the digital signals to the controller;
The input end of the controller is connected with the analog-to-digital converter, and the signal output end of the controller is connected with the impedance matching module and is used for generating the control signal based on the digital signal and transmitting the control signal to the impedance matching module.
2. The driver according to claim 1, wherein the mixing unit comprises:
A first operational amplifier;
a ninth resistor and a tenth resistor are connected in series between the first input end of the mixing unit and the in-phase output end of the first operational amplifier, and a node between the ninth resistor and the tenth resistor is connected with the inverting input end of the first operational amplifier;
an eleventh resistor connected between the second input terminal of the mixing unit and the inverting input terminal of the first operational amplifier;
a twelfth resistor connected between the third input terminal of the mixing unit and the non-inverting input terminal of the first operational amplifier;
A thirteenth resistor and a fourteenth resistor connected in series between the fourth input terminal of the mixing unit and the inverting output terminal of the first operational amplifier, and a node between the thirteenth resistor and the fourteenth resistor is connected with the non-inverting input terminal of the first operational amplifier;
wherein the ninth resistor, the tenth resistor, the eleventh resistor, the twelfth resistor, the thirteenth resistor, and the fourteenth resistor have the same resistance value.
3. The driver of claim 1, wherein the impedance matching module comprises:
A first varistor and a second varistor connected in series between the third output terminal and the fourth output terminal;
the first rheostat and the second rheostat are connected with the adjusting module through respective resistance control ends so as to respectively adjust respective resistance values according to the control signals.
4. The driver of claim 2 or 3, wherein the signal conversion module comprises a second operational amplifier, wherein,
The second operational amplifier is provided with a first current input end and a second current input end, and the first current input end and the second current input end are respectively connected with the upper-level circuit and are used for receiving the differential current signal from the upper-level circuit;
The second operational amplifier further has a first voltage output terminal and a second voltage output terminal for outputting the differential voltage signal.
5. The driver of claim 4, wherein the first drive module comprises:
the first resistor is connected in series between the first current input end and the third output end;
the third resistor is connected in series between the third output end and the first output port;
The drain electrodes of the first PMOS tube and the first NMOS tube are connected with the third output end, the grid electrodes of the first PMOS tube and the first NMOS tube are connected with the first voltage output end, the source electrode of the first PMOS tube is connected with the power supply end, and the source electrode of the first NMOS tube is grounded;
The drain electrodes of the third PMOS tube and the third NMOS tube are connected with the first output port, the grid electrodes of the third PMOS tube and the third NMOS tube are connected with the first voltage output end, the source electrode of the third PMOS tube is connected with the power supply end, and the source electrode of the third NMOS tube is grounded.
6. The driver of claim 5, wherein the second drive module comprises:
the second resistor is connected in series between the second current input end and the fourth output end;
the fourth resistor is connected in series between the fourth output end and the second output port;
The drain electrodes of the second PMOS tube and the second NMOS tube are connected with the fourth output end, the grid electrodes of the second PMOS tube and the second NMOS tube are connected with the second voltage output end, the source electrode of the second PMOS tube is connected with the power supply end, and the source electrode of the second NMOS tube is grounded;
The drain electrodes of the fourth PMOS tube and the fourth NMOS tube are connected with the second output port, the grid electrodes of the fourth PMOS tube and the fourth NMOS tube are connected with the second voltage output end, the source electrode of the fourth PMOS tube is connected with the power supply end, and the source electrode of the fourth NMOS tube is grounded.
7. The actuator of claim 6, wherein the actuator comprises a plurality of actuators,
The ratio of the width-to-length ratio of the third PMOS tube to the width-to-length ratio of the first PMOS tube is N, and the ratio of the width-to-length ratio of the fourth PMOS tube to the width-to-length ratio of the second PMOS tube is N;
And the ratio of the width-to-length ratio of the third NMOS tube to the width-to-length ratio of the first NMOS tube is N, and the ratio of the width-to-length ratio of the fourth NMOS tube to the width-to-length ratio of the second NMOS tube is N.
8. The actuator of claim 6, wherein the actuator comprises a plurality of actuators,
The resistance of the third resistor and the fourth resistor are (n+1) times the resistance of the equivalent impedance of the driver in the far-end Ethernet transceiver, and the resistance of the equivalent impedance of the driver in the far-end Ethernet transceiver is equal to the characteristic impedance of the transmission line.
9. An ethernet transceiver comprising a higher level circuit and the driver of any one of claims 1-8, the higher level circuit being operable to provide a differential current signal to the driver in dependence upon an output swing of a current mode of the ethernet transceiver.
10. A control method of a drive, characterized by being applied to the drive of any one of claims 1-8, the method comprising:
generating control signals according to signals received from the first driving module, the second driving module and the transmission line;
Transmitting the control signal to the impedance matching module to adjust the impedance of the impedance matching module through the control signal so as to match the impedance between the equivalent impedance of the driver and the characteristic impedance of the transmission line;
Wherein generating a control signal from signals received from the first drive module, the second drive module, the transmission line, comprises: generating a differential analog signal based on signals received from the first driving module, the second driving module, and the transmission line, wherein a difference value of the differential analog signal is a difference value between a transmission signal and a mixed residual voltage of the far-end ethernet transceiver; the differential analog signal is converted to a digital signal, and the control signal is generated based on the digital signal.
11. The control method of claim 10, wherein the control signal adjusts an impedance of the impedance matching module to control the mixed residual voltage to be minimized.
CN202210494899.1A 2022-05-07 2022-05-07 Driver of Ethernet transceiver, control method thereof and Ethernet transceiver Active CN115001878B (en)

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